CN115050655A - 层叠封装及其制造方法 - Google Patents

层叠封装及其制造方法 Download PDF

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Publication number
CN115050655A
CN115050655A CN202111461996.2A CN202111461996A CN115050655A CN 115050655 A CN115050655 A CN 115050655A CN 202111461996 A CN202111461996 A CN 202111461996A CN 115050655 A CN115050655 A CN 115050655A
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China
Prior art keywords
semiconductor die
package
layer
forming
offset
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CN202111461996.2A
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Inventor
成基俊
李采城
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SK Hynix Inc
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SK Hynix Inc
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Publication of CN115050655A publication Critical patent/CN115050655A/zh
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Abstract

本公开涉及一种层叠封装及其制造方法。层叠封装包括形成在载体上的第一包封层。半导体管芯顺序地偏移层叠在第一包封层上。形成连接到半导体管芯的垂直连接件。形成联接到第一包封层的第二包封层以包封垂直连接件和半导体管芯。在第二包封层上形成连接到垂直连接件的再分布层。

Description

层叠封装及其制造方法
技术领域
本公开大体上涉及一种半导体封装技术，并且更具体地说，涉及层叠封装(stackpackage)及其制造方法。
背景技术
半导体封装需要具有高密度和高性能。已经进行了各种尝试来将多个半导体管芯(semiconductor die)集成到单个半导体封装结构中。期望这种半导体封装执行高速操作、大容量数据处理操作或多功能操作。为了使半导体封装适于应用于移动设备，需要具有更小形状因数(form factor)的半导体封装结构。已经对具有小宽度和薄厚度的封装结构进行了各种尝试。正在尝试其中多个半导体管芯基本上彼此垂直地层叠的结构。
发明内容
根据一个实施例，一种制造半导体封装的方法可以包括以下步骤：在载体上形成第一包封层；在第一包封上顺序地偏移层叠半导体管芯；形成连接到所述半导体管芯的垂直连接件；形成连接到所述第一包封层并且包封所述垂直连接件和所述半导体管芯的第二包封层；以及在所述第二包封层上形成连接到所述垂直连接件的再分布层。
根据另一实施例，一种半导体封装可以包括：半导体管芯，其偏移层叠在第一包封层上；第二包封层，其联接到所述第一包封层并且包封所述半导体管芯；再分布层，其形成在第二包封层上；以及垂直连接件，其穿透所述第二包封层并且将所述半导体管芯连接到所述再分布层。
附图说明
图1到图14是示出根据本公开的实施例的层叠封装及其制造方法的示意性截面图。
图15到图21是示出根据本公开的另一实施例的层叠封装及其制造方法的示意性截面图。
图22是示出采用包括根据本公开的实施例的封装的存储卡的电子系统的框图。
图23是示出包括根据本公开的实施例的封装的电子系统的框图。
具体实施方式
这里使用的术语可以对应于考虑到它们在所呈现的实施例中的功能而选择的词语，并且根据实施例所属领域的普通技术人员，这些术语的含义可以被解释为不同的。如果进行了详细定义，则术语可根据定义来解释。除非另有定义，否则本文使用的术语(包括技术和科学术语)具有与实施例所属领域的普通技术人员通常理解的含义相同地含义。
应当理解，虽然术语“第一”和“第二”，“侧部”，“顶部”和“底部或下部”可能在本文中用于描述各种装置，但这些装置不应受这些术语限制。这些术语仅用于区分一个设备与另一个设备，而不用于指示设备的特定顺序或数量。
半导体装置可以包括半导体基板或其中多个半导体基板进行层叠的结构。半导体装置可以是其中半导体基板进行层叠的半导体封装结构。半导体基板可以是其中集成了电子元件和器件的半导体芯片、半导体晶片或半导体管芯。半导体芯片可以表示其中集成了诸如动态随机存取存储器(DRAM)电路、静态随机存取存储器(SRAM)电路、NAND型闪存存储器电路、NOR型闪存存储器电路、磁性随机存取存储器(MRAM)电路、电阻式随机存取存储器(ReRAM)电路、铁电随机存取存储器(FeRAM)电路或相变随机存取存储器(PcRAM)的存储器集成电路的存储器芯片，其中将逻辑电路集成在半导体基板中的ASIC芯片或逻辑管芯，或诸如应用处理器(Ap)、图形处理单元(GPU)、中央处理单元(CPU)或片上系统(SoC)的处理器。所述半导体装置可用于诸如移动电话的信息通信系统、与生物技术或医疗保健相关联的电子系统或可穿戴电子系统中。半导体封装可应用于物联网(IoT)。
在整个说明书中，相同的附图标记表示相同的装置。即使可能未参考一个附图提及或描述一个附图标记，也可能参考另一附图提及或描述该附图标记。此外，尽管在一个附图中可能没有示出一个附图标记，但是可以参考其他附图对其进行描述。
图1至图14是示出根据本公开的实施例的制造层叠封装的方法的工艺步骤的示意性截面图。
图1是示出在根据本公开的实施例的制造层叠封装的方法中引入的载体100的示意性截面图。
参考图1，可以在载体100上执行根据实施例的用于制造层叠封装的工艺步骤。载体100可用作工作台(work table)、处理晶片或支撑基板。载体100可以由硬质材料制成。载体100可以由玻璃材料、硅(Si)材料或金属材料制成。载体100可以具有半导体晶片的形状。载体粘合层110可以设置在载体100的表面上。载体粘合层110可包括用于将其它构件附接到载体100的粘合剂。
图2和图3是示出根据本公开的实施例的形成层叠封装的第一包封(encapsulant)层200的步骤的截面图。
参考图2和图3，第一包封层200可以形成在载体100上。可以将第一包封膜200F层压在载体100上，如图2所示，以在载体100上形成第一包封层200，如图3所示。载体粘合层110可以将第一包封膜200F附接到载体100。第一包封层200可具有约几微米(μm)至几十μm的厚度。
第一包封膜200F可以是其中各种包封材料以膜的形式加工的构件。包封材料可以包括各种类型的填料(filler)和树脂，并且可以是构成半导体封装中的保护层的材料，该保护层保护半导体管芯免受外部环境的影响。第一包封膜200F可以包括通过将环氧模塑料(EMC)加工成膜的形式而获得的环氧模塑料(EMC)膜。
图4是示出根据本公开的实施例的设置层叠封装的下半导体管芯410的步骤的示意性截面图。
参考图4，下半导体管芯410可以设置在第一包封层200上。多个下半导体管芯410可以设置在第一包封层200上，同时在水平方向上彼此基本上(substantially)间隔开。每个下半导体管芯410可以是层叠在第一包封层200上的半导体管芯400中的一个。每个半导体管芯400可以是其中集成有存储器装置的半导体管芯。
每个下半导体管芯410可以通过第一粘合层310附接到第一包封层200。第一粘合层310可以涂覆在作为下半导体管芯410的背面的第一表面410BS上，使得第一粘合层310可以在下半导体管芯410设置在第一包封层200上时将下半导体管芯410粘合到第一包封层200。构成第一包封层200的第一包封膜(图2中的200F)可以不包含粘合剂，从而在将下半导体管芯410安装到第一包封层200时可以使用第一粘合层310。
每个下半导体管芯410可以包括第二表面410FS上的第一接触焊盘411。第一接触焊盘411可以构成电连接和信号连接到下半导体管芯410的连接端子。第二表面410FS可以是下半导体管芯410的与第一表面410BS相对的前表面。
图5是示出根据本公开的实施例的层叠封装的半导体管芯400的层叠的示意性截面图。
参考图5，半导体管芯400可以在第一包封层200上顺序地偏移层叠(offsetstacked)。具体地，下半导体管芯410可以设置在第一包封层200上，并且第二中间半导体管芯420、第一中间半导体管芯430和上半导体管芯440可以顺序地层叠在每个下半导体管芯410上。可在上半导体管芯440与下半导体管芯410之间层叠额外的半导体管芯。第二粘合层320可以将第二中间半导体管芯420中的每个附接到下半导体管芯410中的对应的一个。第三粘合层330可以将第一中间半导体管芯430中的每个附接到第二中间半导体管芯420中的对应的一个。第四粘合层340可将上半导体管芯440中的每个附接到第一中间半导体管芯430中的对应的一个。
第一中间半导体管芯430可以以第一偏移层叠在下半导体管芯410上。第一中间半导体管芯430可以在第一偏移方向D1上从设置下半导体管芯410的位置移动第一距离S1。
第一中间半导体管芯430可以与第二中间半导体管芯420部分交叠，同时暴露第二中间半导体管芯420的第二接触焊盘421。第一中间半导体管芯430可以与下半导体管芯410部分交叠。
上半导体管芯440可以在与第一偏移方向D1相反的第二偏移方向D2上以第二偏移层叠在第一中间半导体管芯430上。上半导体管芯440可以在第二偏移方向D2上从第一中间半导体管芯430层叠的位置移动第二距离S2。上半导体管芯440可以与第一中间半导体管芯430部分交叠，同时暴露第一中间半导体管芯430的第三接触焊盘431。上半导体管芯440可以被放置为暴露第二中间半导体管芯420的一部分，同时暴露第一中间半导体管芯430的一部分。上半导体管芯440可被放置为暴露第二中间半导体管芯420的第二接触焊盘421，同时暴露第一中间半导体管芯430的第三接触焊盘431。上半导体管芯440可以包括上表面上的第四接触焊盘441。
第二中间半导体管芯420可以在与第一偏移方向D1基本相同的方向上以第三偏移层叠在下半导体管芯410和第一中间半导体管芯430之间。第二中间半导体管芯420可以在第一偏移方向D1上从设置下半导体管芯410的位置移动第三距离S3。第三距离S3可以比第一距离S1短。第二距离S2可以与第三距离S3基本相同。第二中间半导体管芯420可与下半导体管芯410部分交叠，同时暴露下半导体管芯410的第一接触焊盘411。
由于上半导体管芯440在与第一中间半导体管芯430和第二中间半导体管芯420的第一偏移方向D1相反的第二偏移方向D2上以第二偏移层叠，与其中上半导体管芯440以与第一中间半导体管芯430和第二中间半导体管芯420相同的方式在第一偏移方向D1上偏移层叠的层叠相比，半导体管芯400的层叠的总宽度可以减小。因此，可以减小层叠封装的宽度。
图6是示出根据本公开的实施例的形成层叠封装的垂直连接件500的步骤的示意性截面图。
参考图6，在形成半导体管芯400的层叠之后，可形成分别连接到半导体管芯400的垂直连接件500。每个垂直连接件500可以包括导电材料，并且可以提供将电信号连接到半导体管芯400的路径。每个垂直连接件500可以包括导电金属材料，例如金(Au)或铜(Cu)。垂直连接件500可包括从半导体管芯400的表面基本垂直延伸或基本垂直于半导体管芯400的表面直立的互连构件。
每个垂直连接件500可以包括第一接合引线(bonding wire)510、第二接合引线530、第三接合引线520和导电凸块540。第一接合引线510可以连接到下半导体管芯410，并且可以被形成为基本垂直地延伸，同时在第二中间半导体管芯420、第一中间半导体管芯430和上半导体管芯440旁边通过。第二接合引线530可以连接到第一中间半导体管芯430，并且可以被形成为基本垂直地延伸，同时在上半导体管芯440旁边通过。第一接合引线510和第二接合引线530可以形成在彼此相对的位置处，并使上半导体管芯440插置其间。第三接合引线520可以连接到第二中间半导体管芯420，并且可以被形成为基本垂直地延伸，同时在第一中间半导体管芯430和上半导体管芯440旁边通过。
接合引线510、530和520中的每一个可以通过使用引线接合设备(未示出)的引线接合工艺来形成。
图7是示出根据本公开的实施例的形成层叠封装的第二接合引线530的步骤的示意性截面图。
参考图7，引线接合设备的劈刀(capillary)509可以移动以将引线530W引导为放置在第一中间半导体管芯430的第三接触焊盘431上方。可以降低劈刀509，以使得引线530W的第一端530E可以接合到第三接触焊盘431。此后，通过升高劈刀509，第二接合引线530可以从接合的第一端530E基本垂直地延伸，并且第二接合引线530可以被切割(cut)并与引线530W分离。因此，第二接合引线530可被形成为具有第一端530E和与第一端530E相对的第二端530T的垂直连接构件。通过这样的引线接合工艺，可以形成基本上垂直地连接到第一中间半导体管芯430的第二接合引线530。通过应用这种引线接合工艺，如图6所示，还可以形成第一接合引线510和第三接合引线520。
再次参考图6，形成垂直连接件500的步骤还可以包括形成连接到上半导体管芯440的导电凸块540的步骤。接合引线530W可以不连接到上半导体管芯440，并且可以使用凸块形成工艺分别在第四接触焊盘441上形成导电凸块540。每个导电凸块540可以由铜(Cu)材料形成。在另一实施例中，可形成接合到第四接触焊盘441的接合引线(未示出)。接合引线可以被引入作为用于替换导电凸块540的连接构件。
图8是示出根据本公开的实施例的形成层叠封装的第二包封层601的步骤的示意性截面图。
参考图8，可形成第二包封层601以覆盖并包封(encapsulate)层叠的半导体管芯400。第二包封层601可以被形成为覆盖第一包封层200的暴露表面部分，并联接到第一包封层200。第一包封层200和第二包封层601可经联接以将层叠的半导体管芯400作为整体进行包封。第二包封层601可以通过使用液体包封材料的模制工艺形成。模制工艺可以通过以下操作来执行：将其上层叠有半导体管芯400的载体100安装在模具(未示出)中，将液体包封材料引入到模具中，按压模具且固化所引入的包封材料。第二包封层601可以由液体环氧模塑料(EMC)模制。构成第二包封层601的环氧模塑料(EMC)可以与构成第一包封层200的EMC具有基本上相同的组分和组分比。构成第二包封层601的环氧模塑料(EMC)可以与构成第一包封层200的EMC具有不同的组分和组分比。
图9是示出根据本公开的实施例的使层叠封装的第二包封层601凹陷(recessing)的步骤的示意性截面图。
参考图9，可以去除第二包封层601的一部分。第二包封层601可以凹陷以形成第二包封层602。可以通过研磨第二包封层601的上表面来去除第二包封层601的该部分。垂直连接件500的端部可以暴露在第二包封层602的表面处。例如，第二包封层602可以凹陷以使得第二接合引线530的第二端530T暴露。
当第二包封层601和半导体管芯400附接到载体100时，可以执行使第二包封层601凹陷的研磨工艺。因为第二包封层601和半导体管芯400附接到载体100，所以可以基本上防止或减少包括第二包封层602和半导体管芯400的结构的翘曲现象(warpage phenomenon)。如上所述，因为基本上抑制了翘曲现象，所以可以基本上减小凹陷的第二包封层602的厚度变化。因此，可以有效地防止或抑制由翘曲现象引起的工艺缺陷。
图10是示出根据本公开的实施例的形成层叠封装的再分布层(redistributionlayer)720的步骤的示意性截面图。
参照图10，可在第二包封层602上方形成再分布层720。再分布层720可以被形成为电连接和信号连接到垂直连接件500的导电图案。再分布层720可以被形成为通过垂直连接件500连接到半导体管芯400的电路布线。再分布层720可以通过电介质层710彼此绝缘。再分布层720可以构成诸如印刷电路板(PCB)的互连结构。再分布层720可以提供比印刷电路板(PCB)结构更薄的互连结构。因此，与包括印刷电路板(PCB)的层叠封装相比，可以减小层叠封装的总厚度。
图11是示出根据本公开的实施例的形成层叠封装的外部连接端子800的步骤的示意性截面图。
参考图11，可以形成电连接到再分布层720的外部连接端子800。每个外部连接端子800可以具有焊球(solder ball)的形状。
图12是示出根据本公开的实施例的移除层叠封装的载体100的步骤的示意性截面图。
参考图12和图11，可以形成包封外部连接端子800的保护层900。可以通过将包括粘合剂的膜附接到包封再分布层720的介电层710来形成保护层900。可通过移除载体100来暴露第一包封层200。
图13是示出根据本公开的实施例的层叠封装的单个化(singulation)步骤的示意性截面图。图14是示出根据本公开的实施例的经单个化的层叠封装的截面形状的示意性截面图。
参考图13，另一载体(未示出)可以附接到保护层900，并且可以执行沿着切割线切割层叠封装的锯切工艺。在锯切工艺中，可以使用锯切刀片(未示出)去除介电层710的一部分、第二包封层602的一部分和第一包封层200的一部分。在锯切工艺中，可以使用激光去除介电层710的该一部分，第二包封层602的该一部分和第一包封层200的该一部分。锯切工艺可以作为隐形划片工艺(stealth dicing process)来执行。在锯切工艺之后，可从单个层叠封装10去除保护层900。因此，如图14所示，可以分离单个层叠封装10。
图15到图21是示出根据本公开的另一实施例的制造层叠封装的方法的工艺步骤的示意性截面图。在图15至图21中，以与图1至图14所示的形状类似或基本相同的形状描绘的构件可以被理解为表示基本相同的构件。
图15是示出根据本公开的实施例的形成层叠封装的第一包封层2200的步骤的示意性截面图。
参考图15，第一包封层2200可以形成在载体2100上。具体地，作为第一包封层2200的第一包封膜可以通过载体粘合层2110层压在载体2100上。可在第一包封层2200的表面上提供凹形空腔(concave cavity)2200C。其上具有空腔2200C的第一包封膜可以层压在载体2100上作为第一包封层2200。在另一个实施例中，可以通过在形成第一包封层2200之后去除第一包封层2200的一部分来在第一包封层2200中形成空腔2200C。空腔2200C可以形成在要设置图16的下半导体管芯2410的位置处，使得图16的下半导体管芯2410可以在随后的工艺步骤中被插入到空腔2200C中。
图16是示出根据本公开的实施例的设置层叠封装的下半导体管芯2410的步骤的示意性截面图。
参照图16，下半导体管芯2410可设置在第一包封层2200上。下半导体管芯2410可以设置在第一包封层2200的空腔2200C中。每个下半导体管芯2410可以设置在第一包封层2200上，使得下半导体管芯2410的一部分或全部插入到第一包封层2200的每个空腔2200C中。第一包封层2200的空腔2200C可用作指示要设置下半导体管芯2410的位置的标记，使得在将下半导体管芯2410设置在第一包封层2200上时，可以将下半导体管芯2410设置在更准确的位置处。因为空腔2200C在第一包封层2200的表面上提供凸形表面结构，所以第一包封层2200可具有更高的对翘曲的抵抗性。因此，在用于形成层叠封装的后续工艺期间，可以有效地抑制或减少翘曲的发生。
下半导体管芯2410可以通过第一粘合层2310附接到第一包封层2200的空腔2200C的底部。每个下半导体管芯2410可以在其表面上包括第一接触焊盘2411。
图17是示出根据本公开的实施例的层叠封装的半导体管芯2400的层叠的示意性截面图。
参考图17，半导体管芯2400可以顺序地偏移层叠在第一包封层2200上。下半导体管芯2410可以设置在第一包封层2200上，并且第二中间半导体管芯2420、第一中间半导体管芯2430和上半导体管芯2440可以顺序地层叠在下半导体管芯2410上。可在上半导体管芯2440与下半导体管芯2410之间层叠额外半导体管芯。第二粘合层2320可以将第二中间半导体管芯2420附接到下半导体管芯2410。第三粘合层2330可以将第一中间半导体管芯2430附接到第二中间半导体管芯2420。第四粘合层2340可以将上半导体管芯2440附接到第一中间半导体管芯2430。
每个第一中间半导体管芯2430可以在第一偏移方向上以第一偏移层叠在下半导体管芯2410上。第一中间半导体管芯2430可以与第二中间半导体管芯2420部分交叠，同时暴露第二中间半导体管芯2420的第二接触焊盘2421。第一中间半导体管芯2430可以与下半导体管芯2410部分交叠。上半导体管芯2440可以在与第一偏移方向相反的方向上以第二偏移层叠在第一中间半导体管芯2430上。上半导体管芯2440可以与第一中间半导体管芯2430部分交叠，同时暴露第一中间半导体管芯2430的第三接触焊盘2431。上半导体管芯2440可包括上表面上的第四接触焊盘2441。
第二中间半导体管芯2420可以在与第一偏移方向基本相同的方向上以第三偏移层叠在下半导体管芯2410和第一中间半导体管芯2430之间。第二中间半导体管芯2420可以与下半导体管芯2410部分交叠，同时暴露下半导体管芯2410的第一接触焊盘2411。
图18是示出根据本公开的实施例的形成层叠封装的垂直连接件2500的步骤的示意性截面图。
参考图18，在形成半导体管芯2400的层叠之后，可形成分别连接到半导体管芯2400的垂直连接件2500。每个垂直连接件2500可以包括第一接合引线2510、第二接合引线2530、第三接合引线2520和导电凸块2540。
图19是示出根据本公开的实施例的形成层叠封装的再分布层2720的步骤的示意性截面图。
参考图19，可形成第二包封层2602以覆盖并包封层叠的半导体管芯2400。再分布层2720可以形成在第二包封层602上方。再分布层2720可以嵌入在介电层2710中。再分布层2720可以被形成为电连接和信号连接到垂直连接件2500的导电图案。
图20是示出根据本公开的实施例的形成层叠封装的外部连接端子2800的步骤的示意性截面图。
参考图20，可以形成电连接到再分布层2720的外部连接端子2800。
图21是示出根据本公开的实施例的单个层叠封装20的形状的示意性截面图。
参考图21和图20，可以通过移除载体2100来暴露第一包封层2200。此后，可执行锯切工艺以单个化层叠封装20。
再次参考图14，根据实施例的层叠封装10可以包括在第一包封层200上顺序地偏移层叠的半导体管芯400。层叠封装10还可包括在包封半导体管芯400的同时联接到第一包封层200的第二包封层602。层叠封装10可包含形成于第二包封层602上的再分布层720和在穿过第二包封层602同时将半导体管芯400连接到再分布层720的垂直连接件500。
再次参考图21，根据实施例的层叠封装20可以包括第一包封层2200、半导体管芯2400、第二包封层2602、再分布层2720和垂直连接件2500。空腔2200C可以设置在第一包封层2200中，下半导体管芯2410部分地插入空腔2200C中。
如上所述，根据本公开的一些实施例，可以提供一种层叠封装结构和制造方法，其中多个半导体管芯彼此偏移层叠，并且层叠的半导体管芯和再分布层通过垂直连接件连接。
图22是示出包括采用根据本公开的实施例的半导体封装中的至少一个的存储卡7800的电子系统的框图。存储卡7800包括诸如非易失性存储器装置的存储器7810和存储器控制器7820。存储器7810和存储器控制器7820可以存储数据或读出所存储的数据。存储器7810和存储器控制器7820中的至少一个可以包括根据本公开的实施例的半导体封装中的至少一者。
存储器7810可以包括应用了本公开的实施例的技术的非易失性存储器装置。存储器控制器7820可以控制存储器7810，使得响应于来自主机7830的读/写请求而读出所存储的数据或存储数据。
图23是示出包括根据本公开的实施例的半导体封装中的至少一个的电子系统8710的框图。电子系统8710可以包括控制器8711、输入/输出装置8712和存储器8713。控制器8711、输入/输出装置8712和存储器8713可以通过总线8715彼此联接，总线8715提供数据移动通过的路径。
在一个实施例中，控制器8711可以包括微处理器、数字信号处理器、微控制器和/或能够与这些组件执行相同功能的逻辑器件中的一个或更多个。控制器8711或存储器8713可以包括根据本公开的实施例的半导体封装中的至少一个。输入/输出设备8712可以包括从小键盘、键盘、显示装置和触摸屏等中选择的至少一个。存储器8713是用于存储数据的装置。存储器8713可以存储将由控制器8711执行的命令和/或数据等。
存储器8713可以包括诸如DRAM的易失性存储器装置和/或诸如闪存存储器的非易失性存储器装置。例如，闪存存储器可以安装到诸如移动终端或台式计算机的信息处理系统。闪存存储器可以构成固态盘(SSD)。在这种情况下，电子系统8710可以在闪存存储器系统中稳定地存储大量数据。
电子系统8710还可以包括被配置为向通信网络发送数据和从通信网络接收数据的接口8714。接口8714可以是有线或无线类型的。例如，接口8714可以包括天线或有线或无线收发器。
电子系统8710可以被实现为执行各种功能的移动系统、个人计算机、工业计算机或逻辑系统。例如，移动系统可以是个人数字助理(PDA)、便携式计算机、平板计算机、移动电话、智能电话、无线电话、膝上型计算机、存储卡、数字音乐系统和信息发送/接收系统中的任何一种。
如果电子系统8710是能够执行无线通信的设备，则电子系统8710可以用在使用CDMA(码分多址)、GSM(全球移动通信系统)、NADC(北美数字蜂窝)、E-TDMA(增强型时分多址)、WCDMA(宽带码分多址)、CDMA2000、LTE(长期演进)或Wibro(无线宽带互联网)的技术的通信系统中。
已经结合如上所述的一些实施例公开了本教导。本领域技术人员将理解，在不脱离本公开的范围和精神的情况下，各种修改、添加和替换是可能的。因此，在本说明书中公开的实施例不应该被认为是限制性的，而应该被认为是说明性的。本教导的范围不限于上述描述，而是由所附权利要求限定，并且等同范围内的所有区别特征应被解释为包括在本教导中。
相关申请的交叉引用
本申请要求于2021年3月9日提交的韩国申请No.10-2021-0031082的优先权，其全部内容通过引用并入本文。

Claims (24)

1.一种制造层叠封装的方法，所述方法包括以下步骤：
在载体上形成第一包封层；
在所述第一包封层上顺序地偏移层叠半导体管芯；
形成连接到所述半导体管芯的垂直连接件；
形成第二包封层，所述第二包封层联接到所述第一包封层并且包封所述垂直连接件和所述半导体管芯；以及
在所述第二包封层上形成连接到所述垂直连接件的再分布层。
2.根据权利要求1所述的方法，其中，形成所述第一包封层的步骤包括以下步骤：将第一包封膜层压到所述载体。
3.根据权利要求2所述的方法，其中，所述第一包封膜包括环氧模塑料EMC膜。
4.根据权利要求1所述的方法，其中，所述第一包封层包括空腔，层叠的所述半导体管芯当中的下半导体管芯设置在所述空腔中。
5.根据权利要求1所述的方法，其中，形成所述第二包封层的步骤包括以下步骤：使用液体环氧模塑料EMC形成所述第二包封层。
6.根据权利要求1所述的方法，其中，偏移层叠所述半导体管芯的步骤包括以下步骤：
将所述半导体管芯中的下半导体管芯设置在所述第一包封层上；
以第一偏移将所述半导体管芯中的第一中间半导体管芯层叠在所述下半导体管芯上；以及
以在与所述第一偏移相反的方向上的第二偏移在所述第一中间半导体管芯上层叠所述半导体管芯中的上半导体管芯。
7.根据权利要求6所述的方法，其中，将所述下半导体管芯设置在所述第一包封层上的步骤包括以下步骤：通过粘合层将所述下半导体管芯附接至所述第一包封层。
8.根据权利要求6所述的方法，其中，偏移层叠所述半导体管芯的步骤还包括以下步骤：以在与所述第一偏移相同的方向上的第三偏移在所述下半导体管芯与所述第一中间半导体管芯之间层叠所述半导体管芯中的第二中间半导体管芯。
9.根据权利要求8所述的方法，其中，层叠所述上半导体管芯的步骤包括以下步骤：放置所述上半导体管芯以暴露所述第二中间半导体管芯的一部分同时暴露所述第一中间半导体管芯的一部分。
10.根据权利要求6所述的方法，其中，形成所述垂直连接件的步骤包括以下步骤：
形成第一接合引线，所述第一接合引线连接到所述下半导体管芯并且垂直地延伸经过所述上半导体管芯和所述第一中间半导体管芯；以及
形成第二接合引线，所述第二接合引线连接到所述第一中间半导体管芯并且垂直地延伸经过所述上半导体管芯。
11.根据权利要求10所述的方法，其中，形成所述垂直连接件的步骤包括以下步骤：在彼此相对的位置处形成所述第一接合引线和形成所述第二接合引线，并且使所述上半导体管芯插置在所述第一接合引线与所述第二接合引线之间。
12.根据权利要求10所述的方法，其中，形成所述垂直连接件的步骤还包括以下步骤：形成连接到所述上半导体管芯的导电凸块。
13.根据权利要求1所述的方法，其中，形成所述再分布层的步骤还包括以下步骤：使所述第二包封层凹陷以暴露所述垂直连接件的端部。
14.根据权利要求1所述的方法，所述方法还包括以下步骤：
形成电连接到所述再分布层的连接端子；以及
移除所述载体。
15.一种层叠封装，所述层叠封装包括：
半导体管芯，所述半导体管芯偏移层叠在第一包封层上；
第二包封层，所述第二包封层联接到所述第一包封层并包封所述半导体管芯；
再分布层，所述再分布层形成在所述第二包封层上；以及
垂直连接件，所述垂直连接件穿透所述第二包封层，并且将所述半导体管芯连接到所述再分布层。
16.根据权利要求15所述的层叠封装，其中，所述第一包封层包括环氧模塑料EMC膜。
17.根据权利要求15所述的层叠封装，其中，所述第一包封层包括空腔，层叠的所述半导体管芯当中的下半导体管芯设置在所述空腔中。
18.根据权利要求15所述的层叠封装，其中，所述半导体管芯包括：
下半导体管芯；
第一中间半导体管芯，所述第一中间半导体管芯以第一偏移层叠在所述下半导体管芯上；以及
上半导体管芯，所述上半导体管芯以在与所述第一偏移相反的方向上的第二偏移层叠在所述第一中间半导体管芯上。
19.根据权利要求18所述的层叠封装，所述层叠封装还包括粘合层，所述粘合层将所述下半导体管芯附接至所述第一包封层。
20.根据权利要求18所述的层叠封装，其中，所述半导体管芯还包括第二中间半导体管芯，所述第二中间半导体管芯以在与所述第一偏移相同的方向上的第三偏移层叠在所述下半导体管芯与所述第一中间半导体管芯之间。
21.根据权利要求20所述的层叠封装，其中，所述上半导体管芯被放置为暴露所述第二中间半导体管芯的一部分同时暴露所述第一中间半导体管芯的一部分。
22.根据权利要求18所述的层叠封装，其中，所述垂直连接件包括：
第一接合引线，所述第一接合引线连接到所述下半导体管芯并且垂直地延伸经过所述上半导体管芯和所述第一中间半导体管芯；以及
第二接合引线，所述第二接合引线连接到所述第一中间半导体管芯并且垂直地延伸经过所述上半导体管芯。
23.根据权利要求22所述的层叠封装，其中，所述第一接合引线和所述第二接合引线形成在彼此相对的位置处，并且所述上半导体管芯插置在所述第一接合引线和所述第二接合引线之间。
24.根据权利要求22所述的层叠封装，其中，所述垂直连接件还包括连接到所述上半导体管芯的导电凸块。
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