CN110875291A - 基板组件、半导体封装件和制造该半导体封装件的方法 - Google Patents

基板组件、半导体封装件和制造该半导体封装件的方法 Download PDF

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CN110875291A
CN110875291A CN201910731355.0A CN201910731355A CN110875291A CN 110875291 A CN110875291 A CN 110875291A CN 201910731355 A CN201910731355 A CN 201910731355A CN 110875291 A CN110875291 A CN 110875291A
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substrate
semiconductor chip
semiconductor
columnar conductor
top surface
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CN110875291B (zh
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金度贤
吴琼硕
姜善远
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

提供了基板组件、半导体封装件以及制造该半导体封装件的方法。所述半导体封装件包括基板、位于所述基板上的第一半导体芯片、位于所述第一半导体芯片上的第二半导体芯片和连接结构。所述第二半导体芯片包括向外突出超过所述第一半导体芯片的一侧的第一节段和位于所述第二半导体芯片的所述第一节段的底表面上的第二连接焊盘。所述连接结构包括位于所述基板与所述第二半导体芯片的所述第一节段之间的第一结构和穿过所述第一结构以与所述基板接触且设置在所述第二连接焊盘与所述基板之间的第一柱状导体，从而将所述第二半导体芯片电连接到所述基板。

Description

基板组件、半导体封装件和制造该半导体封装件的方法
相关申请的交叉引用
本专利申请要求于2018年9月4日在韩国知识产权局提交的韩国专利申请No.10-2018-0105380的优先权，该韩国专利申请的全部内容通过引用的方式结合于本申请中。
技术领域
本发明构思涉及基板组件、包括该基板组件的半导体封装件以及制造该半导体封装件的方法。
背景技术
随着电子工业的发展，电子产品要求在紧凑尺寸下的高性能操作。为了满足这种需求，半导体芯片被堆叠在基板上，或者封装件被堆叠在另一封装件上。
可能需要使用诸如结合引线的各种方法将堆叠在基板上的半导体芯片连接到基板。或者，每一个半导体芯片被穿孔以形成其中可以提供贯穿硅通路(TSV)的孔，以将上芯片连接到基板或下芯片。
发明内容
根据本发明构思的示例性实施例，一种半导体封装件包括基板、位于所述基板上的第一半导体芯片、位于所述第一半导体芯片上的第二半导体芯片和连接结构。所述第二半导体芯片包括向外突出超过所述第一半导体芯片的一侧的第一节段和位于所述第二半导体芯片的所述第一节段的底表面上的第二连接焊盘。所述连接结构包括位于所述基板与所述第二半导体芯片的所述第一节段之间的第一结构和穿过所述第一结构以与所述基板接触且设置在所述第二连接焊盘与所述基板之间的第一柱状导体，从而将所述第二半导体芯片电连接到所述基板。
根据本发明构思的示例性实施例，一种基板组件包括基板和组装在所述基板的顶表面上的连接结构。所述连接结构包括从所述基板向上延伸的第一结构和穿透所述第一结构以与所述基板接触的第一柱状导体。
根据本发明构思的示例性实施例，一种制造半导体封装件的方法包括：准备设置有柱状导体的基板；以及在所述基板上堆叠多个半导体芯片，使得所述多个半导体芯片中的至少一个半导体芯片经由所述柱状导体电连接到所述基板，并且所述多个半导体芯片设置在所述柱状导体的外部。所述柱状导体从所述基板向上延伸。
附图说明
图1示出了显示出根据本发明构思的一些示例实施例的半导体封装件的截面图。
图2示出了显示出根据本发明构思的一些示例实施例的制造半导体封装件的方法的流程图。
图3示出了显示出根据本发明构思的一些示例实施例的基板的截面图。
图4示出了显示出根据本发明构思的一些示例实施例的基板和连接结构彼此组装的示例的截面图。
图5示出了显示出根据本发明构思的一些示例实施例的在连接结构中形成孔的示例的截面图。
图6示出了显示出根据本发明构思的一些示例实施例的导电材料填充连接结构的孔的示例的截面图。
图7示出了显示出根据本发明构思的一些示例实施例的堆叠第一半导体芯片的步骤的截面图。
图8示出了显示出根据本发明构思的一些示例实施例的堆叠第二半导体芯片的步骤的截面图。
图9示出了显示出根据本发明构思的一些示例实施例的完成半导体芯片的堆叠的示例的截面图。
图10示出了显示出根据本发明构思的一些示例实施例的模制步骤的截面图。
图11示出了显示出根据本发明构思的一些示例实施例的外部球附接到半导体封装件的示例的截面图。
图12示出了显示出根据本发明构思的一些示例实施例的半导体封装件的截面图。
图13示出了显示出根据本发明构思的一些示例实施例的半导体封装件的截面图。
图14示出了显示出根据本发明构思的一些示例实施例的半导体封装件的截面图。
图15示出了显示出根据本发明构思的一些示例实施例的半导体封装件的截面图。
图16示出了显示出根据本发明构思的一些示例实施例的制造图15的半导体封装件的方法的流程图。
图17示出了显示出根据本发明构思的一些示例实施例的半导体封装件的截面图。
图18示出了显示出根据本发明构思的一些示例实施例的制造图17的半导体封装件的方法的流程图。
图19示出了显示出根据本发明构思的一些示例实施例的将基板组装到连接结构的过程的截面图。
图20示出了显示出根据本发明构思的一些示例实施例的半导体封装件的截面图。
图21示出了显示出根据本发明构思的一些示例实施例的制造图20的半导体封装件的方法的流程图。
图22示出了显示出根据本发明构思的一些示例实施例的半导体封装件的截面图。
图23示出了显示出根据本发明构思的一些示例实施例的制造图22的半导体封装件的方法的流程图。
具体实施方式
下面将参考附图描述本发明构思的一些示例实施例。在整个说明书中，相同的附图标记可以表示相同的组件。
图1示出了显示出根据本发明构思的一些示例实施例的半导体封装件的截面图。
图1示出了作为第一方向的方向D1、作为第二方向的方向D2以及作为第三方向的方向D3。向上的方向可以指示第一方向D1，向下的方向可以指示与第一方向D1相反的方向，右侧可以指向第二方向D2，左侧可以指向与第二方向D2相反的方向。
参考图1，半导体封装件可以包括基板1、半导体芯片3、连接结构5、模制层7和外部连接端子8。例如，外部连接端子8可以包括外部球。
基板1可以电连接到半导体芯片3。基板1可以是印刷电路板(PCB)。例如，基板1可以是晶片。基板1可以不同地配置用于与半导体芯片3电连接。
半导体芯片3可以堆叠在基板1上。可以提供两个或更多个半导体芯片3。图1示出了包括第一半导体芯片31、第二半导体芯片32、第三半导体芯片33、第四半导体芯片34、第五半导体芯片35、第六半导体芯片36、第七半导体芯片37和第八半导体芯片38的示例。然而，本发明构思不限于上述示例。例如，半导体芯片3可以仅包括第一半导体芯片31和第二半导体芯片32，或者可以包括九个或更多个半导体芯片。每一个半导体芯片3可以是逻辑芯片、存储芯片等。
半导体芯片3可以均具有相同的面积。可选地，至少一个半导体芯片3的面积可以不同于其他芯片的面积。半导体芯片3可以是相同的芯片。可选地，半导体芯片3中的至少一个可以与其他芯片具有不同的特征(例如，不同类型、不同尺寸、不同操作等)。
连接结构5可以将基板1电连接到一个、一些或全部半导体芯片3。连接结构5可以支撑一个、一些或全部半导体芯片3。
模制层7可以封装半导体芯片3。模制层7可以保护半导体芯片3免受外部环境的影响。例如，模制层7可以保护半导体芯片3免受外部热、湿气或冲击。模制层7可以向外排放从半导体芯片3和/或基板1产生的热。模制层7可以包括例如环氧模制化合物(EMC)。或者，模制层7可以包括除环氧模制化合物之外的介电材料。
外部连接端子8可以附接到基板1的底表面。外部连接端子8可以将基板1电连接到半导体封装件外部的封装件、板等。
下面将进一步详细讨论基板1、半导体芯片3、连接结构5、模制层7和外部连接端子8。
图2示出了显示出根据本发明构思的一些示例实施例的制造半导体封装件的方法的流程图。图3至图11示出了显示出制造半导体封装件的方法的截面图，该方法基于图2的流程图。
参考图2，半导体封装件制造方法S可以包括封装准备步骤S1和封装步骤S2。封装准备步骤S1可以包括基板制造步骤S11和连接结构形成步骤S12。封装步骤S2可以包括芯片堆叠步骤S21和模制步骤S22。
参考图2和图3，在基板制造步骤S11，可以制造基板1。基板1可以包括中间介电层11、上导电层131、下导电层133、上介电层151和下介电层153。
中间介电层11可以是基板1的主体。中间介电层11可以包括介电材料。中间介电层11可以是基板1的核心。中间介电层11可以包括例如树脂。或者，中间介电层11可以包括不同于树脂的介电材料。中间介电层11可以具有但不限于矩形截面。
上导电层131可以设置在中间介电层11上。上导电层131可以具有各种图案。图3示出了其中多个上导电层131都彼此电断开，但是至少两个上导电层131可以在第三方向D3上彼此电连接的截面图。上导电层131可以包括金属。例如，上导电层131可以包括铜。
下导电层133可以结合在中间介电层11下方。例如，下导电层133可以设置在中间介电层11下方。下导电层133可以具有各种图案。图3示出了其中多个下导电层133都彼此断开，但是某些下导电层133可以在第三方向D3上彼此连接的截面图。下导电层133可以包括导电材料。例如，下导电层133可以包括铜。
上介电层151可以设置在上导电层131上。上介电层151可以包括介电材料。上介电层151可以保护上导电层131免受外部环境的影响。在某些实施例中，上介电层151可以包括阻焊剂(SR)或感光型阻焊剂(PSR)。然而，本发明构思不限于此。上介电层151可以具有上孔151x。上孔151x可以从上介电层151的顶表面朝向上导电层131延伸。上孔151x可以包括第一上孔151a、第二上孔151b、第三上孔151c、第四上孔151d、第五上孔151e、第六上孔151f、第七上孔151g和第八上孔151h。上孔151x的数量不必限于八个，而是可以少于或多于八个。上介电层151可以通过丝网印刷或辊涂形成。
下介电层153可以设置在下导电层133下方。下介电层153可以包括介电材料。下介电层153可以保护下导电层133免受外部环境的影响。在某些实施例中，下介电层153可以包括阻焊剂(SR)。例如，下介电层153可以包括感光型阻焊剂(PSR)。然而，本发明构思不限于此。下介电层153可以具有下孔153y。下孔153y可以从下介电层153的底表面朝向下导电层133延伸。下孔153y可以包括第一下孔153a、第二下孔153b、第三下孔153c、第四下孔153d和第五下孔153e。下孔153y的数量不必限于五个，而是可以少于或多于五个。下介电层153可以通过丝网印刷或辊涂形成。
基板制造步骤S11可以在与执行封装步骤S2的位置不同的位置执行。或者，基板制造步骤S11和封装步骤S2可以在相同的位置执行。
参照图2和图4，连接结构形成步骤S12可以包括在基板1上形成连接结构5。连接结构5可以包括介电材料。例如，连接结构5可以包括阻焊剂(SR)或光致阻焊剂(PSR)。然而，本发明构思不限于此。连接结构5可以堆叠在上介电层151上。
连接结构5可以从上介电层151的顶表面沿第一方向D1延伸到特定高度。连接结构5可以包括一个或更多个结构。例如，连接结构5可以包括第一结构5a、第二结构5b、第三结构5c、第四结构5d、第五结构5e、第六结构5f和第七结构5g。第一结构5a至第七结构5g可以在第一方向D1上具有彼此不同的高度。或者，当仅堆叠两个半导体芯片时，连接结构5可以仅包括一个结构。
第一结构5a至第七结构5g中的每一个结构可以与上介电层151一体地形成。例如，上介电层151与第一结构5a至第七结构5g中的每一个结构可以由相同的材料形成而在它们之间没有边界(例如，在单个工艺中)。第一结构5a至第七结构5g可以通过重复执行使用掩模等的堆叠和蚀刻工艺来形成。或者，第一结构5a至第七结构5g可以通过注射成型工艺形成。可以采用任何其他工艺来形成第一结构5a至第七结构5g。
第一结构5a可以从上介电层151向上延伸到特定高度。第一结构5a可以设置在第二上孔151b上。第一结构5a可以具有第一顶表面51a。第一顶表面51a可以基本上平行于基板1。然而，本发明构思不限于上述内容。
第二结构5b可以设置在第一结构5a的右侧。可选地，第二结构5b可以相对于第一结构5a在第三方向D3上设置。第二结构5b可以直接连接到第一结构5a。可选地，第二结构5b可以与第一结构5a间隔开。
第二结构5b可以从上介电层151沿第一方向D1延伸到特定高度。第二结构5b可以设置在第三上孔151c上。第二结构5b可以具有第二顶表面51b。第二顶表面51b可以基本平行于上介电层151的顶表面。然而，本发明构思不限于此。第二顶表面51b可以高于第一顶表面51a。在该构造中，第二顶表面51b与上介电层151之间的距离可以大于第一顶表面51a与上介电层151之间的距离。第二结构5b可以在第一方向D1上比第一结构5a长。
第三结构5c至第七结构5g可以被构造为与上述结构相同。例如，第三结构5c至第七结构5g可以分别设置在第四上孔151d至第八上孔151h上，并且可以分别具有基本平行于上介电层151的顶表面的第三顶表面51c至第七顶表面51g。第一结构5a至第七结构5g的高度可以在从第一结构5a朝向第七结构5g的方向上增加。第一结构5a至第七结构5g可以全部布置在相邻结构的右侧。可选地，第一结构5a至第七结构5g中的一个或更多个结构可以布置在相邻结构的右侧，并且第一结构5a至第七结构5g中的另一个或更多个结构可以在第三方向D3上布置。
第一结构5a至第七结构5g的底表面可以在相同的高度水平上，从而可以形成单个平面55。或者，第一结构5a至第七结构5g的底表面可以位于彼此不同的水平。
参照图5，可以在连接结构5中形成一个或更多个孔。第一孔511a可以形成为从第一顶表面51a延伸到上介电层151。第二孔511b可以形成为从第二顶表面51b延伸到上介电层151。同样，第三孔511c至第七孔511g中的每一个可以形成为从第三顶表面51c至第七顶表面51g中的相应一个顶表面延伸到上介电层151。例如，第一孔511a至第七孔511g中的每一个可以通过激光钻孔或机械钻孔形成。作为另一个示例，当堆叠连接结构5时，可以使用掩模等来同时形成第一孔511a至第七孔511g。
第一孔511a至第七孔511g可以分别在空间上连接到第二上孔151b至第八上孔151h。上导电层131可以通过第二上孔151b至第八上孔151h暴露至第一孔511a至第七孔511g。
参照图6，可以在第一孔511a至第七孔511g中的每一个中形成柱状导体。在示例性实施例中，柱状导体的在第一方向D1上的高度可以大于在第二方向D2上的宽度。在示例性实施例中，柱状导体可以具有等于或大于一个要堆叠的半导体芯片的高度。第一柱状导体513a可以形成在第一孔511a中。第二柱状导体513b可以形成在第二孔511b中。同样，第三柱状导体513c至第七柱状导体513g可以分别形成在第三孔511c至第七孔511g中。图6示出了第一柱状导体513a至第七柱状导体513g设置在形成于第一结构5a至第七结构5g中的第一孔511a至第七孔511g中的示例，但是本发明构思不限于此。第一柱状导体513a至第七柱状导体513g可以分别沿着第一结构5a至第七结构5g延伸。例如，第一柱状导体513a至第七柱状导体513g可以分别附接到第一结构5a至第七结构5g的侧壁。第一柱状导体513a至第七柱状导体513g可以不同地设置以分别由第一结构5a至第七结构5g支撑。
基板1和组装在基板1的顶表面上的连接结构5可以构成基板组件。连接结构5可以包括从基板1向上延伸的结构5a至5g和分别穿透结构5a至5g以与基板1接触的柱状导体513a至513g。
第一柱状导体513a的顶表面可以处于与第一顶表面51a的高度水平相同的高度水平。可选地，第一柱状导体513a的顶表面的高度水平可以高于或低于第一顶表面51a的高度水平。以上描述也可以同样地或类似地适用于第二柱状导体513b至第七柱状导体513g。
连接结构形成步骤S12可以在与执行封装步骤S2的位置不同的位置执行。可选地，连接结构形成步骤S12和封装步骤S2可以在相同的位置执行。
参照图2和图7，可以提供其上设置有连接结构5的基板1。芯片堆叠步骤S21可以包括第一芯片堆叠步骤S211。在第一芯片堆叠步骤S211，可以将第一半导体芯片31堆叠在基板1上。例如，可以使用未示出的连接结构或任何其他组件将第一半导体芯片31堆叠到基板1上。再例如，可以将第一半导体芯片31直接堆叠在基板1上。第一半导体芯片31可以包括第一连接焊盘311、第一连接端子311a、第一普通焊盘313和第一普通端子313a。
第一连接焊盘311可以设置在第一半导体芯片31的一侧处的底表面上。第一连接焊盘311可以包括导电材料。第一连接焊盘311可以具有但不限于矩形截面。第一连接端子311a可以安置在第一连接焊盘311下方。第一连接端子311a可以包括导电材料。例如，第一连接端子311a可以包括焊料。第一连接端子311a可以位于暴露于第一上孔151a的上导电层131上。第一连接焊盘311可以通过第一连接端子311a连接到上导电层131。第一半导体芯片31可以通过第一连接焊盘311和第一连接端子311a电连接到基板1。
第一普通焊盘313可以位于第一半导体芯片31的另一侧处的底表面上。第一普通焊盘313可以包括导电材料。可选地，第一普通焊盘313可以不包括导电材料。第一普通端子313a可以安置在第一普通焊盘313下方。第一普通端子313a可以包括导电材料。可选地，第一普通端子313a可以不包括导电材料。第一普通端子313a可以安置在上介电层151上。第一普通焊盘313和第一普通端子313a不需要用于将第一半导体芯片31电连接到基板1。第一普通焊盘313和第一普通端子313a可以机械地支撑第一半导体芯片31。
粘合层9可以涂覆在第一半导体芯片31上。粘合层9可以将第一半导体芯片31附接到其他部件。可选地，粘合层9可以不存在。
参照图2、图8和图9，芯片堆叠步骤S21可以包括第n芯片堆叠步骤S212。在某些实施例中，n可以是等于或大于2的自然数。
参照图8，第n芯片堆叠步骤S212可以包括在第一半导体芯片31上堆叠第二半导体芯片32。当第二半导体芯片32堆叠在第一半导体芯片31上时，第二半导体芯片32的一部分可以与第一半导体芯片31交叠，并且第二半导体芯片32的另一部分可以向外突出超过第一半导体芯片31的一侧。第二半导体芯片32可以位于具有第一柱状导体513a的连接结构5之外。从第一半导体芯片31向外突出的另一部分可以被称为第二半导体芯片32的第一节段32a。例如，第一节段32a可以在第二方向D2或第三方向D3上向外突出超过第一半导体芯片31的一侧。本发明构思不限于此。例如，第一节段32a可以在第二方向D2和第三方向D3两者上向外突出超过第一半导体芯片31的两侧。
第二半导体芯片32的第一节段32a可以设置在第一结构5a上。第二半导体芯片32的第一节段32a可以包括第二连接焊盘321和第二连接端子321a。第二连接焊盘321可以包括导电材料。第二连接焊盘321可以位于第二半导体芯片32的一侧处的底表面上，或者位于第一节段32a的底表面上。第二连接端子321a可以安置在第二连接焊盘321下方。第二连接端子321a可以包括导电材料。例如，第二连接端子321a可以包括焊料。第二连接端子321a可以安置在第一柱状导体513a上。第二连接端子321a可以将第二连接焊盘321连接到第一柱状导体513a。第二半导体芯片32可以通过第二连接端子321a和第一柱状导体513a电连接到基板1。
第二半导体芯片32还可以包括第二普通焊盘323和第二普通端子323a。第二普通焊盘323可以位于第二半导体芯片32的另一侧处的底表面上。第二普通焊盘323可以包括导电材料。可选地，第二普通焊盘323可以不包括导电材料。第二普通端子323a可以安置在第二普通焊盘323下方。第二普通端子323a可以包括导电材料。可选地，第二普通端子323a可以不包括导电材料。第二普通端子323a可以位于第一半导体芯片31的粘合层9上。可选地，第二普通端子323a可以与第一半导体芯片31的顶表面接触。第二普通焊盘323和第二普通端子323a不需要用于将第二半导体芯片32电连接到基板1。第二普通焊盘323和第二普通端子323a可以机械地支撑第二半导体芯片32。这里使用的术语“接触”或“与......接触”指的是直接连接(例如，触及)。
第二半导体芯片32可以基本平行于第一半导体芯片31。然而，本发明构思不限于此。如图8所示，第二半导体芯片32的尺寸可以与第一半导体芯片31的尺寸相同。或者，第二半导体芯片32的尺寸可以与第一半导体芯片31的尺寸不同。第二半导体芯片32的面积可以大于第一半导体芯片31的面积。第一半导体芯片31和第二半导体芯片32可以是相同或不相同的芯片。
粘合层9可以涂覆在第二半导体芯片32上。粘合层9可以将第二半导体芯片32附接到其他部件。可选地，粘合层9可以不存在。
尽管第二半导体芯片32包括从第一半导体芯片31的一侧伸出的第一节段32a，但是第二半导体芯片32可以由第一柱状导体513a刚性地支撑。例如，第一柱状导体513a可以在结构上支撑第二半导体芯片32的第一节段32a。以这种方式，尽管第二半导体芯片32包括第一节段32a，但因为第一结构5a支撑第二半导体芯片32的第一节段32a，所以第二半导体芯片32仍可以被刚性地支撑。
参照图9，第三半导体芯片33至第八半导体芯片38可以以与用于堆叠第二半导体芯片32的方式相同的方式堆叠。第三半导体芯片33至第八半导体芯片38可以分别由第二柱状导体513b至第七柱状导体513g支撑。第三半导体芯片33至第八半导体芯片38可以分别通过第二柱状导体513b至第七柱状导体513g电连接至基板1。
图9示出当堆叠第二半导体芯片32至第八半导体芯片38时，第n半导体芯片的第一节段可以沿向右方向突出超过第(n-1)半导体芯片的第一节段的一侧。然而，本发明构思不限于上述内容。例如，第n半导体芯片的第一节段可以在第三方向D3上突出超过第(n-1)半导体芯片的一侧。再例如，第n半导体芯片的第一部分可以在向右方向上突出超过第(n-1)半导体芯片的第一节段的一侧，并且第n半导体芯片的第二部分可以在第三方向D3上突出超过第(n-1)半导体芯片的与第(n-1)半导体芯片的所述一侧不同的另一侧。换句话说，第n半导体芯片可以在第二方向D2和第三方向D3上突出超过彼此相邻的第(n-1)半导体芯片的两侧。
在堆叠半导体芯片3之后，可以执行结合步骤以将半导体芯片的球联结到柱状导体513a至513g。可以采用回流工艺或热压工艺来执行结合步骤。在结合步骤中，可以施加热和/或压力，使得球和柱状导体全部或部分地熔化并联结。
可以在完成芯片堆叠步骤S21之后执行结合步骤。球可以同时联结到柱状导体。或者，可以在堆叠第一半导体芯片31至第八半导体芯片38中的每一个半导体芯片之后执行结合步骤。球可以在每一个结合步骤中联结到柱状导体。
参照图2和图10，可以在完成芯片堆叠步骤S21之后执行模制步骤S22。在模制步骤S22，可以由模制层7封装半导体芯片3。例如，模具可以接纳其上堆叠有半导体芯片3的基板1，并且还接纳模制材料以形成模制层7。例如，模制层7可以保护半导体芯片3免受外部热、冲击或湿气的影响。模制层7可以向外排出从半导体芯片3产生的热。
参照图11，在完成模制步骤S22之后，可以形成外部连接端子8。例如，外部连接端子8可以包括外部球。外部连接端子8可以通过下孔153y联结到暴露在基板1的底表面处的下导电层133。外部连接端子8可以包括导电材料。外部连接端子8可以包括焊料。可以执行回流工艺以将外部连接端子8联结到下导电层133。半导体封装件可以通过外部连接端子8电连接到其他封装件或板。
按照根据本发明构思的一些示例实施例的制造半导体封装件的方法，堆叠的芯片可以直接连接到基板。可能不需要形成结合引线或执行引线结合所需的附加工艺。半导体封装件制造方法可以变得简化，并且可以降低制造成本。可以省略引线结合所需的结合指状物的形成。半导体封装件可以减小尺寸。该方法还可以以比基于贯穿硅通路(TSV)方案的其他方法的成本低的成本制造半导体封装件。
按照根据本发明构思的一些示例实施例的制造半导体封装件的方法，堆叠的芯片可以包括直接连接到基板的柱状导体，因此，可以减少信号路径。例如，堆叠的芯片可以包括与基板接触的用于减少信号路径的柱状导体。因此，该方法可以制造具有低功耗、高信号传递速度和低噪声的半导体封装件。此外，从半导体封装件可以产生更少的热。
按照根据本发明构思的一些示例实施例的制造半导体封装件的方法，尽管上面的半导体芯片包括从下面的半导体芯片向外突出的第一节段(或伸出结构)，但上面的半导体芯片可以由连接结构支撑以稳定地堆叠半导体芯片。即使当上面的半导体芯片大于下面的半导体芯片时，或者即使存在第一节段，也可以防止由伸出结构引起的在上面的或下面的半导体芯片的一侧的应力集中。更具体地，可以防止由伸出结构引起的在上面的半导体芯片的第一节段上的应力集中。即使在结合步骤或模制步骤时施加热，因为第一节段由连接结构支撑，所以仍可以避免应力集中。半导体封装件可以没有诸如翘曲或裂纹的缺陷。因此，可以提高半导体封装工艺的制造良率并且降低半导体封装件的制造成本。
图12示出了显示出根据本发明构思的一些示例实施例的半导体封装件的截面图。
在随后的实施例中，为了描述方便，将省略与上面参考图1至图11讨论的部件和/或工艺基本相同或相似的部件和/或工艺。
参照图12，连接结构5可以包括彼此连接的第一柱状导体513a'至第七柱状导体513g'。例如，第七柱状导体513g'可以连接到第六柱状导体513f'。连接结构5还可以包括第七连接器513g"。第七连接器513g"可以将第七柱状导体513g'连接到第六柱状导体513f'。第七连接器513g"可以包括导电材料。第七连接器513g"可以在与第七柱状导体513g'的延伸方向垂直的方向上延伸。可选地，第七连接器513g"可以倾斜地连接到第七柱状导体513g'。类似地，还可以提供第n连接器以将第n柱状导体连接到第(n-1)柱状导体。第n连接器可以是第二连接器513b"、第三连接器513c"、第四连接器513d"、第五连接器513e"和第六连接器513f"之一。
第二柱状导体513b'至第七柱状导体513g'均可以不直接连接到基板1的上导电层131。例如，第二柱状导体513b'至第七柱状导体513g'均可以不与基板1的上导电层131接触。第二柱状导体513b'至第七柱状导体513g'均可以通过第一柱状导体513a'连接到基板1的上导电层131。
在某些实施例中，可以在模制步骤之前形成连接结构5，因此内孔和位于内孔中的第一柱状导体513a'至第七柱状导体513g'在形状上可以没有限制。如果需要，第一柱状导体513a'至第七柱状导体513g'均可以不同地分支以连接到与其相邻的柱状导体。
图13示出了显示出根据本发明构思的一些示例实施例的半导体封装件的截面图。
在随后的实施例中，为了描述方便，将省略与上面参考图1至图12讨论的部件和/或工艺基本相同或相似的部件和/或工艺。
参照图13，连接结构5可以包括第一柱状导体513a'至第七柱状导体513g'，第一柱状导体513a'至第七柱状导体513g'中的一些柱状导体彼此连接而另一些柱状导体不彼此连接。例如，第二连接器513b"至第七连接器513g"中的一个或更多个连接器可以不存在。图13示出了存在第二连接器513b"、第三连接器513c"、第五连接器513e"、第六连接器513f"和第七连接器513g"但不存在第四连接器(参见图12的513d")的示例。第四柱状导体513d'可以连接到基板1的上导电层131。第二柱状导体513b'、第三柱状导体513c'、第五柱状导体513e'、第六柱状导体513f'和第七柱状导体513g'均可以不直接连接到基板1的上导电层131。第二柱状导体513b'和第三柱状导体513c'均可以通过第一柱状导体513a'连接到基板1的上导电层131。第五柱状导体513e'至第七柱状导体513g'均可以通过第四柱状导体513d'连接到基板1的上导电层131。
以上描述了第一柱状导体513a'和第四柱状导体513d'直接连接到上导电层131并且其他柱状导体513b'、513c'、513e'、513f'和513g'不直接连接到上导电层131的示例，但是根据需要，可以选择第一柱状导体513a'至第七柱状导体513g'中的任何柱状导体与上导电层131直接连接。
图14示出了显示出根据本发明构思的一些示例实施例的半导体封装件的截面图。
在随后的实施例中，为了描述方便，将省略与上面参考图1至图11讨论的部件和/或工艺基本相同或相似的部件和/或工艺。
参照图14，连接结构5的第一柱状导体513a至第七柱状导体513g可以直接联结到第二半导体芯片32至第八半导体芯片38的相应的连接焊盘321至381。第一柱状导体513a可以包括第一柱状导体端部5131a。第一柱状导体端部5131a可以在第一表面(见图4的51a)处暴露。第一柱状导体端部5131a的顶表面可以与第二连接焊盘321的底表面接触。第二连接焊盘321可以通过第一柱状导体端部5131a电连接到第一柱状导体513a。第二柱状导体513b可以包括第二柱状导体端部5131b。第二柱状导体端部5131b可以在第二顶表面(见图4的51b)处暴露。第二柱状导体端部5131b的顶表面可以与第三连接焊盘331的底表面接触。第三连接焊盘331可以通过第二柱状导体端部5131b电连接到第二柱状导体513b。其他柱状导体可以联结到其他连接焊盘。可以执行热压工艺以将第一柱状导体端部5131a到第七柱状导体端部5131g中的每一个柱状导体端部联结到第二连接焊盘321到第八连接焊盘381中的相应一个连接焊盘。
第二半导体芯片32可以通过涂覆在第一半导体芯片31的顶表面上的粘合层9附接到第一半导体芯片31。其他半导体芯片33至38中的每一个半导体芯片可以通过粘合层附接到相应的下面的半导体芯片。
图15示出了显示出根据本发明构思的一些示例实施例的半导体封装件的截面图。图16示出了显示出根据本发明构思的一些示例实施例的制造图15的半导体封装件的方法的流程图。
在随后的实施例中，为了描述方便，将省略与上面参考图1至图14讨论的部件和/或工艺基本相同或相似的部件和/或工艺。
参考图16，封装步骤S'2还可以包括虚设基板准备步骤S'21以及基板和连接结构堆叠步骤S'23。
参考图15，在虚设基板准备步骤S'21，可以提供虚设基板1'。半导体芯片3可以堆叠在虚设基板1'上。半导体芯片3可以相对于虚设基板1'以面朝上的方式堆叠。例如，每一个半导体芯片3可以定向为使得其有源表面和连接焊盘相对于虚设基板1'向上。当完成芯片堆叠步骤S'22时，可以执行基板和连接结构堆叠步骤S'23。基板1和连接结构5可以位于相对于虚设基板1'以面朝上的方式堆叠的半导体芯片3上。
图17示出了显示出根据本发明构思的一些示例实施例的半导体封装件的截面图。图18示出了显示出根据本发明构思的一些示例实施例的制造图17的半导体封装件的方法的流程图。
在随后的实施例中，为了描述方便，将省略与上面参考图1至图14讨论的部件和/或工艺基本相同或相似的部件和/或工艺。
参考图17和图18，封装步骤S"2可以包括芯片堆叠步骤S"21和引线结合步骤S"22。芯片堆叠步骤S"21可以包括第一芯片堆叠步骤S"211、第(n")芯片堆叠步骤S"212和第m芯片堆叠步骤S"213。第一芯片堆叠步骤S"211可以与参考图2讨论的第一芯片堆叠步骤S211基本相同或相似。第(n")芯片堆叠步骤S"212可以与参考图2讨论的第n芯片堆叠步骤S212基本相同或相似。
在完成第(n")芯片堆叠步骤S"212之后，可以执行第m芯片堆叠步骤S"213，使得与第(n")芯片堆叠步骤S"212相比，第m半导体芯片的第一节段指向相反的方向。在第(n")芯片堆叠步骤S"212中，半导体芯片31至33可以以面朝下的方式堆叠，其中半导体芯片31至33均可以定向为使得其有源表面和连接焊盘相对于基板1朝下。第m半导体芯片可以相对于基板1以面朝上的方式堆叠。例如，m可以是介于5与8之间的自然数。第八半导体芯片38可以在其右顶端处包括第八连接焊盘381。第八连接焊盘381可以联结到第八结合球381b。第八结合球381b可以设置在第八连接焊盘381的顶表面上。
在引线结合步骤S"22，可以将第八结合球381b联结到线W。线W也可以连接到另一结合球或第四柱状导体513d的顶端5133。第五半导体芯片35至第七半导体芯片37可以与第八半导体芯片38相同或相似地构造。
在图17和图18的实施例中，连接结构5和线W可以同时用于半导体芯片3与基板1之间的连接。
图19和图20示出了显示出根据本发明构思的一些示例实施例的半导体封装件的截面图。图21示出了显示出根据本发明构思的一些示例实施例的制造图20的半导体封装件的方法的流程图。
在随后的实施例中，为了描述方便，将省略与上面参考图1至图11讨论的部件和/或工艺基本相同或相似的部件和/或工艺。
参照图19，基板1和连接结构5可以彼此单独地且分开地形成。在单独地形成基板1和连接结构5之后，可以将连接结构5组装到基板1。可以使用各种技术将基板1和连接结构5彼此组装。例如，可以使用回流工艺或热压工艺来将连接结构5的第一柱状导体513a至第七柱状导体513g联结到填充第二上孔151b至第八上孔151h的导电材料。再例如，连接结构5可以可拆卸地组装到基板1。在这种情况下，可以在连接结构5上形成对准突起，对准并可以在基板1上形成孔，在这种情况下，可以通过将对准突起插入到对准孔中来将连接结构5和基板1彼此组装。连接结构5和基板1的组装可以在封装步骤(见图2的S2)或封装准备步骤(见图2的S1)进行。
参考图20和图21，半导体封装件制造方法S"'可以包括基板制造步骤S"'1、第一连接结构形成步骤S"'2、第一芯片堆叠步骤S"'3、第(n"')芯片堆叠步骤S"'4、第二连接结构安置步骤S"'5、第(m')芯片堆叠步骤S"'6和模制步骤S"'7。基板制造步骤S"'1、第一连接结构形成步骤S"'2和第一芯片堆叠步骤S"'3可以分别与参考图2讨论的基板制造步骤S11、连接结构形成步骤S12和第一芯片堆叠步骤S211基本相同或相似。第(n"')芯片堆叠步骤S"'4可以与参考图18讨论的第(n")芯片堆叠步骤S"212基本相同或相似。
在第二连接结构安置步骤S"'5，可以将第二连接结构5"安置在按照第(n"')芯片堆叠步骤S"'4堆叠的第(n"')半导体芯片上。在某些实施例中，n"'可以是1与4之间的自然数。第二连接结构5"可以与第(n"')半导体芯片直接接触，通过粘合层联结到第(n"')半导体芯片，或者与第(n"')半导体芯片间隔开。第二连接结构5"可以设置成与第(n"')半导体芯片的第一节段相对。第二连接结构5"可以具有与在第一连接结构形成步骤S"'2形成的第一连接结构5'的阶梯结构类似的阶梯结构。在第(m')芯片堆叠步骤S"'6，可以将第(m')半导体芯片堆叠在第二连接结构5"上。例如，m'可以是介于5与8之间的自然数。
按照根据本发明构思的一些示例实施例的制造半导体封装件的方法，基板和连接结构相对于彼此单独地形成，然后彼此组装，因此连接结构可以在形状和位置上不同地改变。当如图20所示使用第二连接结构5"时，可以改变半导体芯片的堆叠方向，同时第二连接结构5"刚性地支撑第(m')半导体芯片。当堆叠方向从右向左改变时，可以减小半导体封装件的尺寸。
图22示出了显示出根据本发明构思的一些示例实施例的半导体封装件的截面图。图23示出了显示出根据本发明构思的一些示例实施例的制造图22的半导体封装件的方法的流程图。
在随后的实施例中，为了描述方便，将省略与上面参考图1至11讨论的部件和/或工艺基本相同或相似的部件和/或工艺。
参考图23，封装准备步骤S""1可以包括延伸导体形成步骤S""12。参考图22，在延伸导体形成步骤S""12，可以在基板1上形成延伸导体50。延伸导体50也可以被称为以上描述的柱状导体。延伸导体50可以包括第一延伸导体51'至第七延伸导体57'。第一延伸导体51'可以从上导电层131向上延伸。第二半导体芯片32可以设置在第一延伸导体51'上。第二半导体芯片32可以通过第一延伸导体51'连接到基板1的上导电层131。第二延伸导体52'可以与第一延伸导体51'间隔开。第二延伸导体52'的在第一方向D1上的高度可以大于第一延伸导体51'的在第一方向D1上的高度。第三延伸导体53'至第七延伸导体57'可以与第一延伸导体51'或第二延伸导体52'相同或相似地构造。第一延伸导体51'至第七延伸导体57'可以支撑半导体芯片3中的相应的半导体芯片，并且可以将半导体芯片3连接到基板1。
根据本发明构思，半导体封装件可以具有缩短的信号路径。
半导体封装件可以以低成本制造。
半导体封装件可以具有低功耗。
根据本发明构思的制造半导体封装件的方法，可以避免应力集中，以防止半导体封装件或芯片的缺陷。
本发明构思的效果不限于上面提到的，本领域技术人员从上面的描述中将清楚地理解上面未提及的其他效果。
尽管已经结合附图中示出的本发明的实施例描述了本发明，但是本领域技术人员将理解，在不脱离本发明的技术精神和基本特征的情况下，可以进行各种改变和修改。因此，将理解的是，上述实施例在所有方面仅是说明性的，而非限制性的。

Claims (20)

1.一种半导体封装件，所述半导体封装件包括：
基板；
第一半导体芯片，所述第一半导体芯片位于所述基板上；
第二半导体芯片，所述第二半导体芯片位于所述第一半导体芯片上；以及
连接结构，
其中，所述第二半导体芯片包括：
第一节段，所述第一节段向外突出超过所述第一半导体芯片的一侧；以及
第二连接焊盘，所述第二连接焊盘位于所述第二半导体芯片的所述第一节段的底表面上，并且
其中，所述连接结构包括：
第一结构，所述第一结构位于所述基板与所述第二半导体芯片的所述第一节段之间；以及
第一柱状导体，所述第一柱状导体穿透所述第一结构以与所述基板接触，并且设置在所述第二连接焊盘与所述基板之间，从而将所述第二半导体芯片电连接到所述基板。
2.根据权利要求1所述的半导体封装件，所述半导体封装件还包括：
模制层，所述模制层覆盖所述第一半导体芯片、所述第二半导体芯片和所述连接结构，
其中，所述第一结构包括与所述模制层的材料不同的材料。
3.根据权利要求1所述的半导体封装件，
其中，所述第一结构包括感光型阻焊剂。
4.根据权利要求3所述的半导体封装件，
其中，所述基板包括：
上导电层；以及
上介电层，所述上介电层具有多个孔，
其中，所述上介电层设置在所述上导电层上，
其中，所述第一柱状导体经由所述多个孔中的一个孔连接到所述上导电层，并且
其中，所述第一结构和所述上介电层具有相同的介电材料。
5.根据权利要求1所述的半导体封装件，
其中，所述第一柱状导体的顶表面与所述第二连接焊盘的底表面接触。
6.根据权利要求1所述的半导体封装件，
其中，所述第二半导体芯片还包括第一球，
其中，所述第一柱状导体和所述第二连接焊盘通过所述第一球彼此电连接。
7.根据权利要求1所述的半导体封装件，所述半导体封装件还包括：
第三半导体芯片，所述第三半导体芯片位于所述第二半导体芯片上，
其中，所述第三半导体芯片包括：
第一节段，所述第一节段向外突出超过所述第二半导体芯片的一侧；以及
第三连接焊盘，所述第三连接焊盘位于所述第三半导体芯片的所述第一节段的底表面上，并且
其中，所述连接结构还包括：
第二结构，所述第二结构位于所述基板与所述第三半导体芯片的所述第一节段之间；以及
第二柱状导体，所述第二柱状导体设置在所述第二结构中并且连接到所述第一柱状导体，从而经由所述第一柱状导体将所述第三半导体芯片电连接到所述基板。
8.根据权利要求7所述的半导体封装件，其中，
所述第一结构包括第一顶表面，
所述第二结构包括第二顶表面，并且
所述第二顶表面与所述基板之间的距离大于所述第一顶表面与所述基板之间的距离。
9.根据权利要求1所述的半导体封装件，其中，所述第一半导体芯片的面积与所述第二半导体芯片的面积相同。
10.一种基板组件，所述基板组件包括：
基板；以及
连接结构，所述连接结构组装在所述基板的顶表面上，
其中，所述连接结构包括：
第一结构，所述第一结构从所述基板向上延伸；以及
第一柱状导体，所述第一柱状导体穿透所述第一结构以与所述基板接触。
11.根据权利要求10所述的基板组件，
其中，所述基板包括：
上导电层，所述上导电层连接到所述第一柱状导体。
12.根据权利要求10所述的基板组件，
其中，所述第一结构包括感光型阻焊剂。
13.根据权利要求11所述的基板组件，
其中，所述基板还包括：
上介电层，所述上介电层具有多个孔，并且设置在所述上导电层上，
其中，所述第一柱状导体经由所述多个孔中的一个孔连接到所述上导电层，并且
其中，所述第一结构和所述上介电层具有相同的介电材料。
14.根据权利要求10所述的基板组件，
其中，所述基板和所述连接结构可拆卸地彼此组装。
15.根据权利要求10所述的基板组件，
其中，所述连接结构还包括：
第二结构，所述第二结构设置在所述基板上且设置在所述第一结构的一侧；以及
第二柱状导体，所述第二柱状导体设置在所述第二结构中并且连接到所述第一柱状导体。
16.根据权利要求15所述的基板组件，其中，
所述第一结构包括第一顶表面，
所述第二结构包括第二顶表面，并且
所述第二顶表面与所述基板之间的距离大于所述第一顶表面与所述基板之间的距离。
17.一种制造半导体封装件的方法，所述方法包括：
准备设置有柱状导体的基板；以及
在所述基板上堆叠多个半导体芯片，使得所述多个半导体芯片中的至少一个半导体芯片经由所述柱状导体电连接到所述基板，并且所述多个半导体芯片设置在所述柱状导体的外部，
其中，所述柱状导体从所述基板向上延伸。
18.根据权利要求17所述的方法，所述方法还包括：
形成模制层以覆盖所述多个半导体芯片。
19.根据权利要求17所述的方法，
其中，堆叠所述多个半导体芯片包括：
在所述基板上堆叠第一半导体芯片；以及
在所述第一半导体芯片上堆叠第二半导体芯片，
其中，所述第二半导体芯片包括向外突出超过所述第一半导体芯片的一侧的第一节段，并且
其中，所述第二半导体芯片的所述第一节段包括位于所述第一节段的底表面上的第二连接焊盘，所述第二连接焊盘位于所述柱状导体上。
20.根据权利要求17所述的方法，所述方法还包括：
执行回流工艺或热压工艺，以将所述多个半导体芯片和所述基板彼此结合和电连接。
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