CN103165505A - 制造扇出晶体级封装的方法以及由该方法形成的封装 - Google Patents

制造扇出晶体级封装的方法以及由该方法形成的封装 Download PDF

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CN103165505A
CN103165505A CN2012105302367A CN201210530236A CN103165505A CN 103165505 A CN103165505 A CN 103165505A CN 2012105302367 A CN2012105302367 A CN 2012105302367A CN 201210530236 A CN201210530236 A CN 201210530236A CN 103165505 A CN103165505 A CN 103165505A
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semiconductor chip
insulating barrier
fan
semiconductor
out wafer
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CN103165505B (zh
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朴辰遇
宋昊建
李锡贤
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明提供了制造扇出晶片级封装的方法以及由该方法形成的封装。该扇出晶片级封装包括：至少两个半导体芯片；绝缘层，覆盖第一半导体芯片的部分；模制层，覆盖第二半导体芯片的部分；再分布线图案，在绝缘层中；和/或外部端子，在绝缘层上。第一半导体芯片可以相对于第二半导体芯片堆叠。再分布线图案可以电连接到该至少两个半导体芯片。外部端子可以电连接到再分布线图案。扇出晶片级封装可以包括：至少三个半导体芯片；绝缘层，覆盖第一半导体芯片的部分；模制层，覆盖第二半导体芯片的部分；再分布线图案，在绝缘层中；和/或在绝缘层上的外部端子。第一半导体芯片可以相对于第二半导体芯片堆叠。

Description

制造扇出晶体级封装的方法以及由该方法形成的封装
技术领域
本发明构思的示例实施例涉及制造扇出（fan-out）晶片级封装的方法和/或由该方法形成的封装。
背景技术
制造半导体封装的封装工艺指的是将半导体芯片连接到外部连接端子并密封半导体芯片用于保护半导体芯片免受外部冲击的一系列工艺。
随着电子产业的发展，半导体封装已经为了小尺寸、轻重量和低制造成本的目的而被不同地发展。另外，随着在各种应用领域诸如数字显示装置、MP3播放器、移动电话和大容量存储装置中的广泛使用，提出各种半导体封装。例如，各种半导体封装可以包括球栅阵列（BGA）封装和晶片级封装（WLP）等。
半导体芯片可以安装在印刷电路板上，可以进行模制工艺。然后焊球可以接合在印刷电路板的底表面上，从而形成BGA封装。BGA封装肯定需要模制工艺。此外，由于BGA封装使用印刷电路板，所以在减小BGA封装的厚度上受到限制。
为了解决BGA封装的这些问题，已经提出WLP。WLP不需要模制工艺。再分布线图案可以形成在半导体芯片的底表面上，焊球可以直接在再分布线图案上，从而形成WLP。因此，由于WLP不需要模制工艺和印刷电路板，所以WLP的结构可以是简单的并且WLP的厚度可以被减小。
同时，随着半导体芯片变得越来越集成，半导体芯片的尺寸会变得越来越小。然而，焊球之间的间隔会被国际半导体标准固定。因此，难以接合期望数目的焊球到WLP。另外，随着半导体芯片的尺寸变得减小，难以操纵和测试WLP。而且，随着半导体芯片的尺寸变得减小，需要不同地改变其上安装WLP的板。
为了解决以上问题，已经提出扇出WLP。在扇出WLP中，模制层可以设置在半导体芯片周围，再分布线图案也可以形成在模制层的底表面上，一些焊球可以接合到在模制层下面的再分布线图案。
发明内容
本发明构思的示例实施例可以提供能够稳定实现各种堆叠结构的扇出晶片级封装的制造方法。
本发明构思的示例实施例还可以提供具有各种堆叠结构的扇出晶片级封装。
在一些示例实施例中，一种制造扇出晶片级封装的方法可以包括：制备其中形成有空腔的接收部件；在接收部件上共形地形成隔离层；将第一半导体芯片设置在空腔中；在第一半导体芯片上设置至少一个第二半导体芯片；形成覆盖第二半导体芯片的模制层，该模制层具有大于第二半导体芯片的宽度的宽度；去除隔离层以使接收部件与第一半导体芯片分离并同时暴露第一半导体芯片；形成覆盖暴露的第一半导体芯片的绝缘层；形成再分布线图案，该再分布线图案贯穿绝缘层以将第一半导体芯片电连接到至少一个第二半导体芯片；和/或在绝缘层上形成电连接到再分布线图案的外部端子。
在一些示例实施例中，接收部件可以是载体或辅助模具。
在一些示例实施例中，隔离层可以是双面粘合带或粘合层。
在一些示例实施例中，将第一半导体芯片设置在空腔中可以包括设置第一半导体芯片使得第一半导体芯片的一个侧壁邻近空腔的至少一个内侧壁。
在一些示例实施例中，空腔的至少一个内侧壁可以形成为台阶形状。第一半导体芯片和至少一个第二半导体芯片的端部可以在空腔中为台阶形状。
在一些示例实施例中，至少两个第一半导体芯片可以在空腔中。
在一些示例实施例中，第一半导体芯片可以包括第一焊垫，至少一个第二半导体芯片包括第二焊垫。第一半导体芯片可以配置为将第一焊垫与隔离层接触。至少一个第二半导体芯片可以配置为使第二焊垫与隔离层接触。
在一些示例实施例中，一种扇出晶片级封装可以包括：依次堆叠的至少两个半导体芯片；绝缘层，覆盖至少两个半导体芯片的最下面的半导体芯片的底表面和一个侧壁；模制层，覆盖至少两个半导体芯片的最上面的半导体芯片的顶表面，该模制层具有大于至少两个半导体芯片的宽度的宽度；再分布线图案，在绝缘层中，再分布线图案电连接到至少两个半导体芯片；和/或外部端子，在绝缘层上，外部端子与再分布线图案接触。
在一些示例实施例中，至少两个半导体芯片的端部可以形成为台阶形状。模制层可以延伸以覆盖最上面的半导体芯片的两个侧壁。绝缘层可以延伸以覆盖最下面的半导体芯片的两个侧壁。
在一些示例实施例中，模制层可以包括突起，该突起延伸以与在最上面的半导体芯片下面的半导体芯片的一个端部接触。绝缘层可以延伸以与在最上面的半导体芯片下面的半导体芯片的另一个端部接触。
在一些示例实施例中，绝缘层可以延伸以覆盖突起的侧壁。
在一些示例实施例中，最上面的半导体芯片可以具有大于最下面的半导体芯片的宽度的宽度，使得最上面的半导体芯片覆盖最下面的半导体芯片的整个顶表面。绝缘层可以延伸以覆盖最下面的半导体芯片的两个侧壁。模制层可以延伸以覆盖绝缘层的侧壁。
在一些示例实施例中，最上面的半导体芯片可以同时覆盖至少两个半导体芯片中彼此相邻的至少两个最下面的半导体芯片。绝缘层可以填充彼此相邻的至少两个最下面的半导体芯片之间的空间。
在一些示例实施例中，模制层可以延伸以同时覆盖彼此相邻的至少两个最下面的半导体芯片的侧壁。
在一些示例实施例中，绝缘层可以延伸以覆盖最上面的半导体芯片的两个侧壁。
在一些示例实施例中，一种扇出晶片级封装可以包括：至少两个半导体芯片；绝缘层，覆盖至少两个半导体芯片中的第一半导体芯片的部分；模制层，覆盖至少两个半导体芯片中的第二半导体芯片的部分；再分布线图案，在绝缘层中；和/或外部端子，在绝缘层上。第一半导体芯片可以相对于第二半导体芯片堆叠。再分布线图案可以电连接到至少两个半导体芯片。外部端子可以电连接到再分布线图案。
在一些示例实施例中，绝缘层可以覆盖第二半导体芯片的部分。
在一些示例实施例中，绝缘层可以覆盖至少两个半导体芯片的部分。
在一些示例实施例中，模制层可以覆盖第一半导体芯片的部分。
在一些示例实施例中，模制层可以覆盖至少两个半导体芯片的部分。
在一些示例实施例中，绝缘层可以覆盖至少两个半导体芯片的侧壁部分。
在一些示例实施例中，模制层可以覆盖至少两个半导体芯片的侧壁部分。
在一些示例实施例中，一种扇出晶片级封装可以包括：至少三个半导体芯片；绝缘层，覆盖至少三个半导体芯片中的第一半导体芯片的部分；模制层，覆盖至少三个半导体芯片中的第二半导体芯片的部分；再分布线图案，在绝缘层中；和/或在绝缘层上的外部端子。第一半导体芯片可以相对于第二半导体芯片堆叠。再分布线图案可以电连接到至少三个半导体芯片。外部端子可以电连接到再分布线图案。
在一些示例实施例中，绝缘层可以覆盖第二半导体芯片的部分。
在一些示例实施例中，绝缘层可以覆盖至少三个半导体芯片的部分。
在一些示例实施例中，模制层可以覆盖第一半导体芯片的部分。
在一些示例实施例中，模制层可以覆盖至少三个半导体芯片的部分。
附图说明
从以下结合附图对示例实施例的详细描述，以上和/或其他的方面和优点将变得更加明显并更易于理解，附图中：
图1至图9是示出根据本发明构思一些示例实施例的制造扇出晶片级封装的方法的截面图；
图10至图15是示出根据本发明构思一些示例实施例的制造扇出晶片级封装的方法的截面图；
图16至图20是示出根据本发明构思一些示例实施例的制造扇出晶片级封装的方法的截面图；
图21至图23是示出根据本发明构思一些示例实施例的制造扇出晶片级封装的方法的截面图；
图24和图25是示出根据本发明构思一些示例实施例的制造扇出晶片级封装的方法的截面图；
图26是示出包括根据本发明构思一些示例实施例的半导体封装的封装模块的示例的视图；
图27是示出包括根据本发明构思一些示例实施例的半导体封装的电子系统的示例的示意方框图；以及
图28是示出包括根据本发明构思一些示例实施例的半导体封装的存储器系统的示例的示意方框图。
具体实施方式
现在将参照附图更充分地描述示例实施例。然而，实施例可以以多种不同的形式实施，而不应被解释为限于这里阐述的实施例。而是，提供这些示例实施例使得本公开透彻和完整，并将本发明的范围充分传达给本领域技术人员。附图中，为了清晰，层和区域的厚度可以被夸大。
将理解，当称一个元件在另一部件“上”、“连接到”、“电连接到”或“耦接到”另一部件时，它可以直接在该另一部件上、连接到、电连接到或耦接到该另一部件，或者还可以存在插入的部件。相反，当称一个部件“直接在”另一部件上、“直接连接到”、“直接电连接到”、或“直接耦接到”该另一部件时，不存在插入的部件。如这里所用的，术语“和/或”包括一个或多个所列相关项目的任何及所有组合。
将理解，尽管这里可以使用术语第一、第二、第三等描述各个元件、部件、区域、层和/或部分，但这些元件、部件、区域、层和/或部分不应受这些术语限制。这些术语仅用于将一个元件、部件、区域、层和/或部分与另一元件、部件、区域、层和/或部分区别开。例如，第一元件、部件、区域、层和/或部分可以被称为第二元件、部件、区域、层和/或部分，而不背离示例实施例的教导。
为便于描述，这里可以使用空间相对性术语诸如“在…之下”、“在...下面”、“下”、“在…之上”、“上”等以描述如附图所示的一个部件或特征与另一个（些）部件或特征之间的关系。将理解，空间相对性术语旨在概括除附图所示取向之外器件在使用或操作中的不同取向。
这里所用的术语仅是为了描述特定示例实施例的目的，并非要限制示例实施例。如这里所用的，除非上下文另有明确表述，否则单数形式“一”和“该”均同时旨在包括复数形式。将进一步理解的是，术语“包括”和/或“包含”，当在本说明书中使用时，指定了所述特征、整体、步骤、操作、元件和/或部件的存在，但并不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其组合的存在或增加。
这里可以参照截面图描述示例实施例，这些图为理想化示例实施例（和中间结构）的示意图。因而，由例如制造技术和/或公差引起的图示形状的变化是可能发生的。因此，示例实施例不应被解释为仅限于这里示出的区域的特定形状，而是包括由例如制造引起的形状偏差在内。例如，图示为矩形的注入区将通常具有圆化或弯曲的特征和/或在其边缘处的注入浓度的梯度而不是从注入区到非注入区的二元变化。类似地，通过注入形成的埋入区可以导致在埋入区与通过其发生注入的表面之间的区域中的一些注入。因此，附图所示的区域在本质上是示意性的，它们的形状并非要示出器件的区域的真实形状，并且它们的形状也并非要限制示例实施例的范围。
除非另行定义，否则这里使用的所有术语（包括技术术语和科学术语）都具有本发明所属领域内的普通技术人员所通常理解的同样的含义。将进一步理解的是，诸如通用词典中所定义的术语，除非此处加以明确定义，否则应当被解释为具有与它们在相关领域的语境中的含义相一致的含义，而不应被解释为理想化的或过度形式化的意义。
现在将参照示例实施例，其在附图中示出，其中相似的附图标记可以始终指代相似的部件。
[第一实施例]
图1至图9是示出根据本发明构思一些示例实施例的制造扇出晶片级封装的方法的截面图。
参照图1，可以制备其中形成空腔CV的接收部件CR。接收部件CR可以是载体或设置在载体上的辅助模具。接收部件CR可以由各种材料诸如玻璃、塑料或金属中的至少一种形成。空腔CV可以利用模制工艺、激光工艺或蚀刻工艺形成在接收部件CR中。在本实施例中，空腔CV可以提供对应于将设置在空腔CV中的第一半导体芯片CP1的尺寸的空间。
参照图2，隔离层IL共形地形成在其上形成空腔CV的接收部件CR的整个表面上。隔离层IL可以是双面粘合带或粘合层。当隔离层IL是双面粘合带时，隔离层IL可以通过利用真空的层叠工艺粘合在接收部件CR上。当隔离层IL是粘合层时，隔离层IL可以通过涂覆粘合材料而形成。
参照图3，半导体芯片CP1设置在空腔CV中。当隔离层IL是双面粘合带或粘合层时，第一半导体芯片CP1可以粘合到空腔CV中的粘合层IL。第一半导体芯片CP1可以包括第一芯片钝化层PS1和第一焊垫PD1。第一半导体芯片CP1可以设置为使第一焊垫PD1与隔离层IL接触。粘合层AD形成在第一半导体芯片CP1上。粘合层AD可以是双面粘合带。第二半导体芯片CP2利用粘合层AD粘合在第一半导体芯片CP1上。第二半导体芯片CP2可以在空腔CV外面设置在接收部件CR的顶表面上。第二半导体芯片CP2可以包括第二芯片钝化层PS2和第二焊垫PD2。第二半导体芯片CP2可以设置为使第二焊垫PD2与隔离层IL接触。第一半导体芯片CP1和第二半导体芯片CP2的端部可以形成为台阶形状。第一焊垫PD1和第二焊垫PD2可以分别设置在第一和第二半导体芯片CP1和CP2的构成台阶形状的端部处。空腔CV可以用作防止第一和第二半导体芯片CP1和CP2掉落的支承物。并且空腔CV可以保护第一和第二焊垫PD1和PD2。
参照图4，模制层MD形成在接收部件CR上。模制层MD可以由环氧模制化合物材料形成。模制层MD形成为覆盖第二半导体芯片CP2的顶表面和侧壁。由于第一和第二焊垫PD1和PD2设置为与隔离层IL接触，所以第一和第二焊垫PD1和PD2不与模制层MD接触。
参照图5，隔离层IL被选择性去除以使第一半导体芯片CP1从接收部件CR分离。当隔离层IL是例如双面粘合带时，约170摄氏度或更高的热可以施加到隔离层IL。因此，双面粘合带会失去粘合力，然后从第一半导体芯片CP1分离。这里，可以控制粘合层AD的硬化温度，使得当隔离层IL从第一半导体芯片CP1分离时，粘合层不从第一和第二半导体芯片CP1和CP2分离。在其他的实施例中，当接收部件CR由玻璃形成时，紫外线可以辐照到接收部件CR的背侧从而硬化双面粘合带的粘合剂。因此，双面粘合带会失去粘合力，然后从第一半导体芯片CP1分离。在另一些实施例中，隔离层IL可以利用化学物质溶解并去除。因而，可以暴露第一半导体芯片CP1的底表面和侧壁、第二半导体芯片CP2的底表面的一部分和模制层MD的底表面。因此，可以暴露第一焊垫PD1和第二焊垫PD2。
参照图6，在接收部件CR被分离的状态下，图5的所得结构被翻转。因此，第一半导体芯片CP1位于第二半导体芯片CP2上。然后第一绝缘层DL1形成在模制层MD上。第一绝缘层DL1形成为与第一和第二焊垫PD1和PD2接触。第一绝缘层DL1可以由无机绝缘层（例如，硅氧化物层、硅氮化物层、硅氮氧化物层）或聚合物绝缘层（例如，聚酰亚胺有机材料）形成。第一绝缘层DL1可以通过旋涂工艺、物理气相沉积（PVD）工艺、化学气相沉积（CVD）工艺、溅射工艺、原子层沉积（ALD）工艺和/或印刷工艺形成。当第一绝缘层DL1通过旋涂工艺形成时，小的台阶差异可能在第一绝缘层DL1的顶表面上发生，然而，第一绝缘层DL1可以基本上被平坦化。当第一绝缘层DL1由沉积工艺形成时，台阶差异可能在第一绝缘层DL1的顶表面上发生。因此，可以在第一绝缘层DL1上额外地进行平坦化工艺。
继续参照图6，第一绝缘层DL1被图案化以形成分别暴露第一焊垫PD1和第二焊垫PD2的第一再分布线过孔H1和第二再分布线过孔H2。第一和第二再分布线过孔H1和H2可以利用光刻工艺和蚀刻工艺形成。如果第一和第二焊垫PD1和PD2与模制层MD接触，则为了形成第一和第二再分布线过孔H1和H2，需要通过激光一个接一个地去除模制层MD的部分。该方法的复杂化会比光刻工艺和蚀刻工艺更坏。另外，第一和第二再分布线过孔H1和H2两者可以通过一个光刻工艺和一个蚀刻工艺同时形成。因此，与利用激光的方法相比，光刻工艺和蚀刻工艺可以快速地形成第一和第二再分布线过孔H1和H2。因而，根据本发明构思的一些示例实施例，可以更快速地制造具有改善的可靠性的扇出晶片级封装。
参照图7，第一再分布线过孔H1和第二再分布线过孔H2用金属层填充，从而形成第一再分布线通路V1和第二再分布线通路V2。再分布线图案W1形成在第一绝缘层DL1上。再分布线图案W1可以与第一和第二再分布线通路V1和V2接触。再分布线图案W1可以用作互连和焊垫。第二绝缘层DL2形成为覆盖再分布线图案W1。第二绝缘层DL2可以由无机绝缘层（例如，硅氧化物层、硅氮化物层、硅氮氧化物层）或聚合物绝缘层（例如，聚酰亚胺有机材料）形成。
参照图8，第二绝缘层DL2被图案化以部分暴露再分布线图案W1，然后焊球SB焊接到暴露的再分布线图案W1。
参照图9，进行分割（singulation）工艺以切割模制层MD以及第一和第二绝缘层DL1和DL2，使得扇出晶片级封装100彼此分离。因此，制造扇出晶片级封装100。
第一和第二半导体芯片CP1和CP2堆叠在图9的扇出晶片级封装100中，第一和第二半导体芯片CP1和CP2的端部形成为台阶形状。第一和第二焊垫PD1和PD2设置在形成为台阶形状的端部上。第一和第二半导体芯片CP1和CP2可以是相同种类的芯片或不同种类的芯片。另外，第一和第二半导体芯片CP1和CP2可以是逻辑芯片或存储器芯片。设置在最下面水平处的第一半导体芯片CP1的底表面和侧壁被第一绝缘层DL1覆盖。设置在最上面水平处的第二半导体芯片CP2的顶表面和侧壁被模制层MD覆盖。模制层MD的宽度大于第一和第二半导体芯片CP1和CP2的宽度。第一半导体芯片CP1和第二半导体芯片CP2通过再分布线图案W1电连接到彼此。
[第二实施例]
图10至图15是示出根据本发明构思一些示例实施例的制造扇出晶片级封装的方法的截面图。
参照图10，制备具有空腔CV的接收部件CR。接收部件CR可以是载体或设置在载体上的辅助模具。接收部件CR可以由各种材料诸如玻璃、塑料和金属中的至少一种形成。空腔CV的一个内侧壁可以具有台阶形状。空腔CV可以提供具有能够接收多个半导体芯片的深度和尺寸的空间。隔离层IL共形地形成在具有空腔CV的接收部件CR上。隔离层IL可以是双面粘合带或粘合层。
参照图11，第一至第三半导体芯片CP1、CP2和CP3设置在空腔CV中。第一半导体芯片CP1可以包括第一芯片钝化层PS1和第一焊垫PD1。第二半导体芯片CP2可以包括第二芯片钝化层PS2和第二焊垫PD2。第三半导体芯片CP3可以包括第三芯片钝化层PS3和第三焊垫PD3。第一至第三半导体芯片CP1、CP2和CP3可以设置为与空腔CV的具有台阶形状的一个内侧壁对准。第一至第三焊垫PD1、PD2和PD3分别设置在第一至第三半导体芯片CP1、CP2和CP3的一个端部处，该第一至第三半导体芯片CP1、CP2和CP3设置在空腔CV的具有台阶形状的一个内侧壁上。第一至第三焊垫PD1、PD2和PD3设置为与隔离层IL接触。如果第一至第三半导体芯片CP1、CP2和CP3具有相同的尺寸，则第一至第三半导体芯片CP1、CP2和CP3的另一端部也形成为台阶形状。这里，空区域SP（其没有被第二和第三半导体芯片CP2和CP3填充）可以保留在空腔CV中。空腔CV可以用作防止第一至第三半导体芯片CP1、CP2和CP3掉落的支承物。并且空腔CV可以保护第一至第三焊垫PD1、PD2和PD3。第四半导体芯片CP4设置在第三半导体芯片CP3上。第四半导体芯片CP4可以包括第四芯片钝化层PS4和第四焊垫PD4。第四半导体芯片CP4可以设置为使得第四焊垫PD4与隔离层IL接触并且第三和第四半导体芯片CP3和CP4的一个端部形成为台阶形状。粘合层AD设置在第一至第四半导体芯片CP1、CP2、CP3和CP4之间，使得第一至第四半导体芯片CP1、CP2、CP3和CP4粘合且固定到彼此。
参照图12，模制层MD形成在接收部件CR上。模制层MD可以由环氧模制化合物材料形成。模制层MD覆盖设置在最上面水平处的第四半导体芯片CP4的顶表面和侧壁。此外，模制层MD填充空腔CV中的空区域SP。换句话说，模制层MD包括覆盖第一至第三半导体芯片CP1、CP2和CP3的被空区域SP暴露的端部的突起MDP。
参照图13，隔离层IL被选择性去除以使接收部件CP与第一至第三半导体芯片CP1、CP2和CP3分离。因此，可以暴露第一半导体芯片CP1的底表面和侧壁、第二和第三半导体芯片CP2和CP3的底表面的部分和侧壁的一些、第四半导体芯片CP4的底表面的一部分、模制层MD的底表面以及突起MDP的侧壁。另外，可以暴露第一至第四焊垫PD1、PD2、PD3和PD4。
参照图14，在接收部件CR分离的状态下，图13的所得结构被翻转。然后第一绝缘层DL1形成在模制层MD上。第一绝缘层DL1覆盖第一半导体芯片CP1的顶表面和侧壁、第二至第四半导体芯片CP2、CP3和CP4的端部、突起MDP的侧壁以及模制层MD的顶表面。第一绝缘层DL1形成为与第一至第四焊垫PD1、PD2、PD3和PD4接触。第一至第四再分布线通路V1、V2、V3和V4形成为贯穿第一绝缘层DL1。第一至第四再分布线通路V1、V2、V3和V4分别与第一至第四焊垫PD1、PD2、PD3和PD4接触。再分布线图案W1形成在第一绝缘层DL1上。再分布线图案W1电连接到第一至第四再分布线通路V1、V2、V3和V4。第二绝缘层DL2形成在第一绝缘层DL1和再分布线图案W1上。
参照图15，第二绝缘层DL2的部分被去除以部分暴露再分布线图案W1，然后焊球SB接合到暴露的再分布线图案W1。进行分割工艺，使得扇出晶片级封装101彼此分离。
参照图15，在根据本实施例的扇出晶片级封装中，第一至第四半导体芯片CP1、CP2、CP3和CP4堆叠并且其端部形成为台阶形状。第一至第四焊垫PD1、PD2、PD3和PD4分别设置在形成为台阶形状的端部上。第一至第四半导体芯片CP1、CP2、CP3和CP4可以是相同种类的芯片或不同种类的芯片。第一至第四半导体芯片CP1、CP2、CP3和CP4通过再分布线图案W1电连接到彼此。设置在最上面水平处的第四半导体芯片CP4的顶表面和侧壁被模制层MD覆盖。模制层MD的宽度比第一至第四半导体芯片CP1、CP2、CP3和CP4的宽度更宽。模制层MD包括覆盖第一至第四半导体芯片CP1、CP2、CP3和CP4的一个端部的突起MDP。设置在最下面水平处的第一半导体芯片CP1的底表面和侧壁被第一绝缘层DL1覆盖。第一绝缘层DL1延伸以覆盖第一至第四半导体芯片CP1、CP2、CP3和CP4的另一端部。另外，第一绝缘层DL1可以覆盖突起MDP的侧壁。
其他方法和其他结构可以与本发明构思的一些其他示例实施例中的相同或相似。
在本实施例中，利用四个半导体芯片说明了堆叠方法/堆叠结构。然而，本发明构思的示例实施例不限于堆叠的半导体芯片的数目。
[第三实施例]
图16至图20是示出根据本发明构思一些示例实施例的制造扇出晶片级封装的方法的截面图。
参照图16，制备其中形成第一空腔CV1和第二空腔CV2的接收部件CR。接收部件CR可以是载体或设置在载体上的辅助模具。接收部件CR可以由各种材料诸如玻璃、塑料和金属中的至少一种形成。第一空腔CV1可以用于接收半导体芯片，第二空腔CV2可以用作相邻封装之间的分割区域。隔离层IL共形地形成在具有第一和第二空腔CV1和CV2的接收部件CR上。第一半导体芯片CP1设置在第一空腔CV1中。然后第二半导体芯片CP2设置在第一半导体芯片CP1上，粘合层AD在两者之间。第二半导体芯片CP2设置在第一空腔CV1外面。第二半导体芯片CP2可以具有比第一半导体芯片CP1的宽度更大的宽度。第一半导体芯片CP1可以包括第一芯片钝化层PS1和第一焊垫PD1。第二半导体芯片CP2可以包括第二芯片钝化层PS2和第二焊垫PD2。第一半导体芯片CP1的第一焊垫PD1和第二半导体芯片CP2的第二焊垫PD2设置为与隔离层IL接触。
参照图17，模制层MD形成在接收部件CR上。模制层MD覆盖第二半导体芯片CP2的顶表面和侧壁并填充第二空腔CV2。
参照图18，隔离层IL被选择性去除以使接收部件CR与第一半导体芯片分离。因此，第一和第二焊垫PD1和PD2被暴露。
参照图19，在分离接收部件CR的状态下，图18的所得结构被翻转。接着，第一绝缘层DL1形成在模制层MD上，然后被平坦化以暴露模制层MD的顶表面。因此，第一绝缘层DL1填充第一半导体芯片CP1与模制层MD之间的空间。模制层MD可以覆盖第一绝缘层DL1的侧壁。再分布线通路V1和V2形成为贯穿第一绝缘层DL1。再分布线通路V1和V2分别连接到焊垫PD1和PD2。再分布线图案W1形成在第一绝缘层DL1上。第二绝缘层DL2形成在第一绝缘层DL1和再分布线图案W1上。第二绝缘层LD2形成为也覆盖模制层MD的顶表面。
参照图20，第二绝缘层DL2的部分被去除以部分暴露再分布线图案W1，然后焊球SB接合到暴露的再分布线图案W1。接着，进行分割工艺，使得扇出晶片级封装102彼此分离。
再次参照图20，在根据本实施例的扇出晶片级封装102中，第一和第二半导体芯片CP1和CP2堆叠，其端部形成为台阶形状。第一和第二焊垫PD1和PD2分别设置在形成为台阶形状的端部上。第一和第二半导体芯片CP1和CP2可以是不同种类的芯片。第一和第二半导体芯片CP1和CP2通过再分布线图案W1电连接到彼此。设置在最上面水平处的第二半导体芯片CP2的顶表面和侧壁被模制层MD覆盖。模制层MD的宽度大于第一和第二半导体芯片CP1和CP2的宽度。设置在最下面水平处的第一半导体芯片CP1的底表面和侧壁被第一绝缘层DL1覆盖。模制层MD延伸以覆盖第一绝缘层DL1的侧壁并与第二绝缘层DL2接触。
其他方法和其他结构可以与第一实施例中的相同或相似。
[第四实施例]
图21至图23是示出根据本发明构思一些示例实施例的制造扇出晶片级封装的方法的截面图。
参照图21，制备其中形成空腔CV的接收部件CR。接收部件CR可以是载体或设置在载体上的辅助模具。空腔CV的两个内侧壁的每个可以具有台阶形状。隔离层IL共形地形成在其中形成空腔CV的接收部件CR上。第一半导体芯片CP1和第二半导体芯片CP2都设置在空腔CV中。第一和第二半导体芯片CP1和CP2的第一和第二焊垫PD1和PD2设置为与隔离层IL接触。粘合层AD设置在第一半导体芯片CP1和第二半导体芯片CP2之间。模制层形成在接收部件CR上。模制层MD形成为覆盖第二半导体芯片CP2的顶表面。
参照图22，隔离层IL被选择性去除以使接收部件CR与第一半导体芯片CP1分离。因此，第一和第二焊垫PD1和PD2被暴露。图22的所得结构（接收部件从其分离）被翻转。第一绝缘层DL1形成在模制层MD上。第一绝缘层DL1形成为覆盖第一半导体芯片CP1的顶表面和侧壁以及第二半导体芯片CP2的侧壁。第一和第二再分布线通路V1和V2形成为贯穿第一绝缘层DL1并连接到第一和第二焊垫PD1和PD2。再分布线图案W1形成在第一绝缘层DL1上。第二绝缘层DL2形成在第一绝缘层DL1和再分布线图案W1上。
参照图23，第二绝缘层DL2的部分被去除以部分暴露再分布线图案W1，然后焊球SB接合到暴露的再分布线图案W1。接着，进行分割工艺，使得扇出晶片级封装103彼此分离。
参照图23，在根据本实施例的扇出晶片级封装103中，第一和第二半导体芯片CP1和CP2堆叠并且其端部形成为台阶形状。第一和第二焊垫PD1和PD2分别设置在形成为台阶形状的端部上。第一和第二半导体芯片CP1和CP2可以是不同种类的芯片。设置在最上面水平处的第二半导体芯片的顶表面被模制层MD覆盖。模制层MD的宽度大于第一和第二半导体芯片CP1和CP2的宽度。设置在最下面水平处的第一半导体芯片CP1的底表面和侧壁以及第二半导体芯片CP2的侧壁被第一绝缘层DL1覆盖。
其他方法和其他结构可以与一些其他示例实施例的相同或相似。
[第五实施例]
图24和25是示出根据本发明构思一些示例实施例的制造扇出晶片级封装的方法的截面图。
参照图24，制备具有空腔CV的接收部件CR。接收部件CR可以是载体或设置在载体上的辅助模具。隔离层IL共形地形成在具有空腔CV的接收部件CR上。两个第一半导体芯片CP1设置在一个空腔CV中。空腔CV的宽度大于第一半导体芯片CP1的宽度的两倍。两个第一半导体芯片CP1在空腔CV中彼此间隔开。一个第一半导体芯片CP1设置为邻近空腔CV的一个内侧壁，另一个第一半导体芯片CP1设置为邻近空腔CV的另一个内侧壁。粘合层AD形成在第一半导体芯片CP1上。第二半导体芯片CP2设置在第一半导体芯片CP1上。第二半导体芯片CP2设置为同时覆盖分别设置在相邻空腔CV中的一对第一半导体芯片CP1。每个第一半导体芯片CP1包括分别设置在每个第一半导体芯片CP1的两个端部上的第一焊垫PD1。第一焊垫PD1接触隔离层IL。第二半导体芯片CP2包括设置在第二半导体芯片CP2的中央部分处的第二焊垫PD2。第二焊垫PD2与隔离层IL接触。模制层MD形成为覆盖第一和第二半导体芯片CP1和CP2。
参照图25，隔离层IL被选择性去除以分离接收部件CR。然后如参照第一至第四实施例所述的，形成第一绝缘层DL1、再分布线通路V1和V2、再分布线图案W1和第二绝缘层DL2。焊球SB接合到再分布线图案W1，然后进行分割工艺，从而形成扇出晶片级封装104。
参照图25，在根据本实施例的扇出晶片级封装104中，第一和第二半导体芯片CP1和CP2堆叠并且其端部形成为台阶形状。第二半导体芯片CP2同时覆盖彼此相邻的两个第一半导体芯片CP1。模制层MD覆盖第二半导体芯片CP2的顶表面和侧壁以及第一半导体芯片CP1的顶表面的部分和侧壁。第一半导体芯片CP1的底表面被第一绝缘层DL1覆盖。第一绝缘层DL1延伸并填充彼此相邻的两个第一半导体芯片CP1之间的空间。第一和第二半导体芯片CP1和CP2通过再分布线图案W1彼此电连接。连接到第二焊垫PD2的第二再分布线通路V2设置在相邻的第一半导体芯片CP1之间。
其他方法和其他结构可以与一些其他示例实施例中的相同或相似。
上述半导体封装技术可以应用到各种半导体器件和包括其的封装模块。
图26是示出包括根据本发明构思一些示例实施例的半导体封装的封装模块的示例的视图。参照图26，封装模块1200可以包括以四边扁平封装（QFP）型封装的半导体器件1220和半导体器件1230。由于应用根据本发明构思一些示例实施例的半导体技术的半导体器件1220和1230安装在基板1210上，可以形成封装模块1200。封装模块1200可以通过设置在基板1210的一侧处的外部连接端子1240连接到外部电子装置。
上述半导体封装技术可以应用到电子系统。图27是包括根据本发明构思一些示例实施例的半导体封装的电子系统的示例的示意方框图。参照图27，电子系统1300可以包括控制器1310、输入/输出（I/O）单元1320和存储器件1330。控制器1310、I/O单元1320和存储器件1330可以通过数据总线1350彼此结合。数据总线1350可以对应于电信号通过其传输的路径。控制器1310可以包括微处理器、数字信号处理器、微控制器或另一逻辑器件中的至少一个。另一逻辑器件可以具有与微处理器、数字信号处理器和微控制器中的任一个相似的功能。I/O单元1320可以包括键板、键盘和/或显示单元。存储器件1330可以存储数据和/或由控制器1310执行的指令。存储器件1330可以包括易失性存储器件和/或非易失性存储器件。或者，存储器件1330可以形成为闪存器件。闪存器件可以实现为固态盘（SSD）。在此情形下，电子系统1300可以稳定地存储大量数据到闪存系统。电子系统1300还可以包括传输电子数据到通讯网络或从通讯网络接收电子数据的接口单元1340。接口单元1340可以通过无线或电缆操作。例如，接口单元1340可以包括用于无线通讯的天线或用于电缆通讯的收发器。尽管没有在附图中示出，但是应用芯片组和/或照相机图像处理器（CIS）还可以提供在电子系统1300中。
电子系统1300可以实现为移动系统、个人计算机、工业计算机或执行各种功能的逻辑系统。例如，移动系统可以是个人数字助理（PDA）、便携式计算机、上网本、无线电话、手机、膝上型计算机、数字音乐系统和信息发送/接收系统之一。当电子系统1300执行无线通讯时，电子系统1300可以使用在通讯接口协议诸如第三代通讯系统（例如，码分多址（CDMA）、全球移动通讯系统（GSM）、北美数字蜂窝（NADC）、扩展时分多址（E-TDMA）、宽带CDMA（WCDMA）、CDMA2000）中。
上述半导体封装技术可以应用到存储器系统。图28是示出包括根据本发明构思一些示例实施例的半导体封装的存储器系统的示例的示意方框图。参照图28，存储器系统1400可以包括非易失性存储器件1410和存储器控制器1420。非易失性存储器件1410和存储器控制器1420可以存储数据或读取所存储的数据。非易失性存储器件1410可以包括应用有根据本发明构思一些示例实施例的半导体封装技术的非易失性存储器件中的至少一个。存储器控制器1420可以控制非易失性存储器件1410从而响应主机1430的读/写要求而读取所存储的数据和/或存储数据。
根据本发明构思的一些示例实施例，半导体芯片可以利用其中形成空腔的接收部件堆叠。因此，可以防止半导体芯片掉落，使得可以稳定地制造堆叠结构的扇出晶片级封装。
此外，由于设置在半导体芯片的端部处的焊垫设置为与隔离层接触，所以模制层不与焊垫接触。因此，再分布线过孔不形成在模制层中而是形成在绝缘层中。如果再分布线过孔形成在模制层中，其可以利用激光形成。在此情形下，难以控制其端点和宽度的检测，使得难以准确地形成它。然而，由于绝缘层中的再分布线过孔利用光刻工艺和蚀刻工艺形成，所以可以容易地控制再分布线过孔的蚀刻端点和宽度的检测。另外，所有的过孔可以通过光刻工艺和蚀刻工艺同时形成。因此，根据本发明构思一些示例实施例的过孔可以快速地形成。因而，根据本发明构思的一些示例实施例，可以更快速地形成具有改善的可靠性的扇出晶片级封装。
此外，在根据本发明构思一些示例实施例的制造扇出晶片级封装的方法中，由于半导体芯片通过再分布线图案电连接到彼此而不用引线接合或贯穿硅通路（TSV），所以可以降低扇出晶片级封装的制造成本。
根据本发明构思一些示例实施例的扇出晶片级封装可以包括半导体芯片的各种堆叠结构。
尽管已经具体示出和描述了本发明构思的示例实施例，但是本领域技术人员将理解，可以在其中进行形式和细节上的各种变化，而不背离本发明的精神和范围，本发明的范围由权利要求书限定。
本申请要求于2011年12月9日在韩国知识产权局（KIPO）提交的韩国专利申请No.10-2011-0131696的优先权，其全部内容通过引用结合于此。

Claims (20)

1.一种制造扇出晶片级封装的方法，该方法包括：
制备其中形成有空腔的接收部件；
在所述接收部件上共形地形成隔离层；
将第一半导体芯片设置在所述空腔中；
在所述第一半导体芯片上设置至少一个第二半导体芯片；
形成覆盖所述第二半导体芯片的模制层，该模制层具有大于所述第二半导体芯片的宽度的宽度；
去除所述隔离层以使所述接收部件与所述第一半导体芯片分离并同时暴露所述第一半导体芯片；
形成覆盖暴露的第一半导体芯片的绝缘层；
形成再分布线图案，该再分布线图案贯穿所述绝缘层以将所述第一半导体芯片电连接到所述至少一个第二半导体芯片；以及
在所述绝缘层上形成电连接到所述再分布线图案的外部端子。
2.如权利要求1所述的方法，其中所述接收部件是载体或辅助模具。
3.如权利要求1所述的方法，其中所述隔离层是双面粘合带或粘合层。
4.如权利要求1所述的方法，其中将所述第一半导体芯片设置在所述空腔中包括：
设置所述第一半导体芯片使得所述第一半导体芯片的一个侧壁邻近所述空腔的至少一个内侧壁。
5.如权利要求1所述的方法，其中所述空腔的至少一个内侧壁形成为台阶形状，并且
其中所述第一半导体芯片和所述至少一个第二半导体芯片的端部在所述空腔中为台阶形状。
6.如权利要求1所述的方法，其中至少两个第一半导体芯片在所述空腔中。
7.如权利要求1所述的方法，其中所述第一半导体芯片包括第一焊垫，所述至少一个第二半导体芯片包括第二焊垫，
其中所述第一半导体芯片配置为将所述第一焊垫与所述隔离层接触，并且
其中所述至少一个第二半导体芯片配置为使所述第二焊垫与所述隔离层接触。
8.一种扇出晶片级封装，包括:
依次堆叠的至少两个半导体芯片；
绝缘层，覆盖所述至少两个半导体芯片的最下面的半导体芯片的底表面和一个侧壁；
模制层，覆盖所述至少两个半导体芯片的最上面的半导体芯片的顶表面，该模制层具有大于所述至少两个半导体芯片的宽度的宽度；
再分布线图案，在所述绝缘层中，所述再分布线图案电连接到所述至少两个半导体芯片；以及
外部端子，在所述绝缘层上，所述外部端子与所述再分布线图案接触。
9.如权利要求8所述的扇出晶片级封装，其中所述至少两个半导体芯片的端部形成为台阶形状，
其中所述模制层延伸以覆盖所述最上面的半导体芯片的两个侧壁，并且
其中所述绝缘层延伸以覆盖所述最下面的半导体芯片的两个侧壁。
10.如权利要求9所述的扇出晶片级封装，其中所述模制层包括突起，该突起延伸以与在所述最上面的半导体芯片下面的半导体芯片的一个端部接触，并且
其中所述绝缘层延伸以与在所述最上面的半导体芯片下面的半导体芯片的另一个端部接触。
11.如权利要求10所述的扇出晶片级封装，其中所述绝缘层延伸以覆盖所述突起的侧壁。
12.如权利要求8所述的扇出晶片级封装，其中所述最上面的半导体芯片具有大于所述最下面的半导体芯片的宽度的宽度，使得所述最上面的半导体芯片覆盖所述最下面的半导体芯片的整个顶表面，
其中所述绝缘层延伸以覆盖所述最下面的半导体芯片的两个侧壁，并且
其中所述模制层延伸以覆盖所述绝缘层的侧壁。
13.如权利要求8所述的扇出晶片级封装，其中所述最上面的半导体芯片同时覆盖所述至少两个半导体芯片中彼此相邻的至少两个最下面的半导体芯片，并且
其中所述绝缘层填充彼此相邻的所述至少两个最下面的半导体芯片之间的空间。
14.如权利要求13所述的扇出晶片级封装，其中所述模制层延伸以同时覆盖彼此相邻的所述至少两个最下面的半导体芯片的侧壁。
15.如权利要求8所述的扇出晶片级封装，其中所述绝缘层延伸以覆盖所述最上面的半导体芯片的两个侧壁。
16.一种扇出晶片级封装，包括：
至少两个半导体芯片；
绝缘层，覆盖所述至少两个半导体芯片中的第一半导体芯片的部分；
模制层，覆盖所述至少两个半导体芯片中的第二半导体芯片的部分；
再分布线图案，在所述绝缘层中；以及
外部端子，在所述绝缘层上，
其中所述第一半导体芯片相对于所述第二半导体芯片堆叠，
其中所述再分布线图案电连接到所述至少两个半导体芯片，并且
其中所述外部端子电连接到所述再分布线图案。
17.如权利要求16所述的扇出晶片级封装，其中所述绝缘层覆盖所述第二半导体芯片的部分。
18.如权利要求16所述的扇出晶片级封装，其中所述绝缘层覆盖所述至少两个半导体芯片的部分。
19.如权利要求16所述的扇出晶片级封装，其中所述模制层覆盖所述第一半导体芯片的部分。
20.如权利要求16所述的扇出晶片级封装，其中所述模制层覆盖所述至少两个半导体芯片的部分。
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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104659001A (zh) * 2013-11-25 2015-05-27 爱思开海力士有限公司 薄嵌入式封装、其制造方法、包括其的电子系统及存储卡
CN104766839A (zh) * 2014-01-06 2015-07-08 爱思开海力士有限公司 芯片层叠封装体、制造方法、包括其的电子系统和存储卡
CN105097990A (zh) * 2014-05-22 2015-11-25 精材科技股份有限公司 半导体结构的制造方法
CN105655310A (zh) * 2015-12-31 2016-06-08 华为技术有限公司 封装结构、电子设备及封装方法
CN106129016A (zh) * 2016-08-10 2016-11-16 江阴芯智联电子科技有限公司 双向集成埋入式芯片重布线pop封装结构及其制作方法
CN106328605A (zh) * 2015-06-30 2017-01-11 三星电子株式会社 半导体封装件
WO2017049510A1 (en) * 2015-09-23 2017-03-30 Intel Corporation Substrates, assemblies, and techniques to enable multi-chip flip chip packages
WO2018129908A1 (zh) * 2017-01-13 2018-07-19 中芯长电半导体（江阴）有限公司 一种双面扇出型晶圆级封装方法及封装结构
CN108597998A (zh) * 2017-09-30 2018-09-28 中芯集成电路（宁波）有限公司 晶圆级系统封装方法及封装结构
CN110828496A (zh) * 2019-11-15 2020-02-21 华天科技（昆山）电子有限公司 半导体器件及其制造方法
CN110875291A (zh) * 2018-09-04 2020-03-10 三星电子株式会社 基板组件、半导体封装件和制造该半导体封装件的方法
CN111712907A (zh) * 2018-02-09 2020-09-25 迪德鲁科技(Bvi)有限公司 制造具有无载体模腔的扇出型封装的方法

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8097926B2 (en) 2008-10-07 2012-01-17 Mc10, Inc. Systems, methods, and devices having stretchable integrated circuitry for sensing and delivering therapy
US9123614B2 (en) 2008-10-07 2015-09-01 Mc10, Inc. Methods and applications of non-planar imaging arrays
US8389862B2 (en) 2008-10-07 2013-03-05 Mc10, Inc. Extremely stretchable electronics
US9082025B2 (en) 2012-10-09 2015-07-14 Mc10, Inc. Conformal electronics integrated with apparel
US9706647B2 (en) 2013-05-14 2017-07-11 Mc10, Inc. Conformal electronics including nested serpentine interconnects
KR102365120B1 (ko) 2013-11-22 2022-02-18 메디데이타 솔루션즈, 인코포레이티드 심장 활동 감지 및 분석용 등각 센서 시스템
KR102128470B1 (ko) 2013-12-17 2020-06-30 삼성전자주식회사 프로브 카드 검사 장치
KR20160129007A (ko) * 2014-03-04 2016-11-08 엠씨10, 인크 전자 디바이스를 위한 다부분 유연성 봉지 하우징
US9431350B2 (en) * 2014-03-20 2016-08-30 United Microelectronics Corp. Crack-stopping structure and method for forming the same
US9281284B2 (en) * 2014-06-20 2016-03-08 Freescale Semiconductor Inc. System-in-packages having vertically-interconnected leaded components and methods for the fabrication thereof
USD781270S1 (en) 2014-10-15 2017-03-14 Mc10, Inc. Electronic device having antenna
KR102352237B1 (ko) 2014-10-23 2022-01-18 삼성전자주식회사 팬 아웃 웨이퍼 레벨 패키지의 제조 방법 및 그의 구조
KR20160056379A (ko) 2014-11-10 2016-05-20 삼성전자주식회사 트리플 패드 구조를 이용하는 칩 및 그것의 패키징 방법
US10477354B2 (en) 2015-02-20 2019-11-12 Mc10, Inc. Automated detection and configuration of wearable devices based on on-body status, location, and/or orientation
USD764447S1 (en) * 2015-04-17 2016-08-23 Airgain Incorporated Antenna
USD767544S1 (en) * 2015-04-18 2016-09-27 Airgain Incorporated Antenna
US11056373B2 (en) * 2015-07-21 2021-07-06 Apple Inc. 3D fanout stacking
EP3420732B8 (en) 2016-02-22 2020-12-30 Medidata Solutions, Inc. System, devices, and method for on-body data and power transmission
USD801955S1 (en) * 2016-03-04 2017-11-07 Airgain Incorporated Antenna
CN109310340A (zh) 2016-04-19 2019-02-05 Mc10股份有限公司 用于测量汗液的方法和系统
KR102556327B1 (ko) * 2016-04-20 2023-07-18 삼성전자주식회사 패키지 모듈 기판 및 반도체 모듈
TWI567897B (zh) * 2016-06-02 2017-01-21 力成科技股份有限公司 薄型扇出式多晶片堆疊封裝構造與製造方法
KR20180001699A (ko) * 2016-06-27 2018-01-05 에스케이하이닉스 주식회사 웨이퍼 레벨 패키지 및 제조 방법
US11469215B2 (en) * 2016-07-13 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US9825007B1 (en) 2016-07-13 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
KR102549402B1 (ko) 2016-08-04 2023-06-28 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US10447347B2 (en) 2016-08-12 2019-10-15 Mc10, Inc. Wireless charger and high speed data off-loader
KR102509049B1 (ko) * 2016-08-22 2023-03-13 에스케이하이닉스 주식회사 수직 적층된 칩들을 포함하는 팬 아웃 패키지
US20190229093A1 (en) * 2016-10-01 2019-07-25 Intel Corporation Electronic device package
US10600679B2 (en) * 2016-11-17 2020-03-24 Samsung Electronics Co., Ltd. Fan-out semiconductor package
TWI613772B (zh) * 2017-01-25 2018-02-01 力成科技股份有限公司 薄型扇出式多晶片堆疊封裝構造
US10453821B2 (en) * 2017-08-04 2019-10-22 Samsung Electronics Co., Ltd. Connection system of semiconductor packages
DE102018124695A1 (de) * 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrieren von Passivvorrichtungen in Package-Strukturen
US10535636B2 (en) * 2017-11-15 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrating passive devices in package structures
US11024603B2 (en) * 2018-01-10 2021-06-01 Powertech Technology Inc. Manufacturing method and a related stackable chip package
US10734326B2 (en) 2018-02-15 2020-08-04 Didrew Technology (Bvi) Limited Hermetic flat top integrated heat spreader (IHS)/electromagnetic interference (EMI) shield package and method of manufacturing thereof for reducing warpage
US10424524B2 (en) 2018-02-15 2019-09-24 Chengdu Eswin Sip Technology Co., Ltd. Multiple wafers fabrication technique on large carrier with warpage control stiffener
TWI753291B (zh) * 2019-04-17 2022-01-21 力成科技股份有限公司 堆疊式晶片封裝
CN113964102A (zh) * 2019-11-29 2022-01-21 长江存储科技有限责任公司 芯片封装结构及其制造方法
KR102643424B1 (ko) * 2019-12-13 2024-03-06 삼성전자주식회사 반도체 패키지
US11227814B2 (en) * 2020-03-16 2022-01-18 Nanya Technology Corporation Three-dimensional semiconductor package with partially overlapping chips and manufacturing method thereof
US11289130B2 (en) * 2020-08-20 2022-03-29 Macronix International Co., Ltd. Memory device
US11532563B2 (en) 2020-09-21 2022-12-20 Apple Inc. Package integration using fanout cavity substrate
US11810895B2 (en) * 2021-10-14 2023-11-07 Honeywell Federal Manufacturing & Technologies, Llc Electrical interconnect structure using metal bridges to interconnect die
EP4273920A1 (en) * 2022-05-04 2023-11-08 Murata Manufacturing Co., Ltd. Electronic component with aligned die

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6365963B1 (en) * 1999-09-02 2002-04-02 Nec Corporation Stacked-chip semiconductor device
CN1402348A (zh) * 2001-08-03 2003-03-12 精工爱普生株式会社 半导体装置及其制造方法
CN1402349A (zh) * 2001-08-03 2003-03-12 精工爱普生株式会社 半导体装置及其制造方法
KR20060074091A (ko) * 2004-12-27 2006-07-03 주식회사 하이닉스반도체 칩 스택 패키지
CN101207114A (zh) * 2006-12-20 2008-06-25 富士通株式会社 半导体器件及其制造方法
US20110079890A1 (en) * 2009-10-06 2011-04-07 Samsung Electronics Co., Ltd. Semiconductor package, semiconductor package structure including the semiconductor package, and mobile phone including the semiconductor package structure

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6492726B1 (en) * 2000-09-22 2002-12-10 Chartered Semiconductor Manufacturing Ltd. Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
US7459781B2 (en) * 2003-12-03 2008-12-02 Wen-Kun Yang Fan out type wafer level package structure and method of the same
KR100618892B1 (ko) 2005-04-13 2006-09-01 삼성전자주식회사 와이어 본딩을 통해 팬 아웃 구조를 달성하는 반도체패키지
US8178963B2 (en) 2007-01-03 2012-05-15 Advanced Chip Engineering Technology Inc. Wafer level package with die receiving through-hole and method of the same
US20080197469A1 (en) 2007-02-21 2008-08-21 Advanced Chip Engineering Technology Inc. Multi-chips package with reduced structure and method for forming the same
KR20090007120A (ko) 2007-07-13 2009-01-16 삼성전자주식회사 봉지부를 통하여 재배선을 달성하는 웨이퍼 레벨 적층형패키지 및 그 제조방법
JP2009071095A (ja) 2007-09-14 2009-04-02 Spansion Llc 半導体装置の製造方法
US20100193930A1 (en) * 2009-02-02 2010-08-05 Samsung Electronics Co., Ltd. Multi-chip semiconductor devices having conductive vias and methods of forming the same
US8643164B2 (en) 2009-06-11 2014-02-04 Broadcom Corporation Package-on-package technology for fan-out wafer-level packaging
US8446017B2 (en) 2009-09-18 2013-05-21 Amkor Technology Korea, Inc. Stackable wafer level package and fabricating method thereof
US20110156239A1 (en) 2009-12-29 2011-06-30 Stmicroelectronics Asia Pacific Pte Ltd. Method for manufacturing a fan-out embedded panel level package
US8436255B2 (en) 2009-12-31 2013-05-07 Stmicroelectronics Pte Ltd. Fan-out wafer level package with polymeric layer for high reliability
US8372689B2 (en) 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6365963B1 (en) * 1999-09-02 2002-04-02 Nec Corporation Stacked-chip semiconductor device
CN1402348A (zh) * 2001-08-03 2003-03-12 精工爱普生株式会社 半导体装置及其制造方法
CN1402349A (zh) * 2001-08-03 2003-03-12 精工爱普生株式会社 半导体装置及其制造方法
KR20060074091A (ko) * 2004-12-27 2006-07-03 주식회사 하이닉스반도체 칩 스택 패키지
CN101207114A (zh) * 2006-12-20 2008-06-25 富士通株式会社 半导体器件及其制造方法
US20110079890A1 (en) * 2009-10-06 2011-04-07 Samsung Electronics Co., Ltd. Semiconductor package, semiconductor package structure including the semiconductor package, and mobile phone including the semiconductor package structure

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104659001A (zh) * 2013-11-25 2015-05-27 爱思开海力士有限公司 薄嵌入式封装、其制造方法、包括其的电子系统及存储卡
CN104659001B (zh) * 2013-11-25 2019-04-26 爱思开海力士有限公司 薄嵌入式封装、其制造方法、包括其的电子系统及存储卡
CN104766839A (zh) * 2014-01-06 2015-07-08 爱思开海力士有限公司 芯片层叠封装体、制造方法、包括其的电子系统和存储卡
CN104766839B (zh) * 2014-01-06 2019-02-22 爱思开海力士有限公司 芯片层叠封装体、制造方法、包括其的电子系统和存储卡
CN105097990A (zh) * 2014-05-22 2015-11-25 精材科技股份有限公司 半导体结构的制造方法
CN105097990B (zh) * 2014-05-22 2017-04-05 精材科技股份有限公司 半导体结构的制造方法
CN106328605B (zh) * 2015-06-30 2019-01-18 三星电子株式会社 半导体封装件
CN106328605A (zh) * 2015-06-30 2017-01-11 三星电子株式会社 半导体封装件
US10748873B2 (en) 2015-09-23 2020-08-18 Intel Corporation Substrates, assembles, and techniques to enable multi-chip flip chip packages
CN108028233A (zh) * 2015-09-23 2018-05-11 英特尔公司 用于实现多芯片倒装芯片封装的衬底、组件和技术
CN108028233B (zh) * 2015-09-23 2023-02-24 英特尔公司 用于实现多芯片倒装芯片封装的衬底、组件和技术
WO2017049510A1 (en) * 2015-09-23 2017-03-30 Intel Corporation Substrates, assemblies, and techniques to enable multi-chip flip chip packages
CN105655310B (zh) * 2015-12-31 2018-08-14 华为技术有限公司 封装结构、电子设备及封装方法
CN105655310A (zh) * 2015-12-31 2016-06-08 华为技术有限公司 封装结构、电子设备及封装方法
WO2017114323A1 (zh) * 2015-12-31 2017-07-06 华为技术有限公司 封装结构、电子设备及封装方法
CN106129016A (zh) * 2016-08-10 2016-11-16 江阴芯智联电子科技有限公司 双向集成埋入式芯片重布线pop封装结构及其制作方法
WO2018129908A1 (zh) * 2017-01-13 2018-07-19 中芯长电半导体（江阴）有限公司 一种双面扇出型晶圆级封装方法及封装结构
CN108597998A (zh) * 2017-09-30 2018-09-28 中芯集成电路（宁波）有限公司 晶圆级系统封装方法及封装结构
CN108597998B (zh) * 2017-09-30 2022-04-08 中芯集成电路（宁波）有限公司 晶圆级系统封装方法及封装结构
CN111712907A (zh) * 2018-02-09 2020-09-25 迪德鲁科技(Bvi)有限公司 制造具有无载体模腔的扇出型封装的方法
CN110875291A (zh) * 2018-09-04 2020-03-10 三星电子株式会社 基板组件、半导体封装件和制造该半导体封装件的方法
US11664348B2 (en) 2018-09-04 2023-05-30 Samsung Electronics Co., Ltd. Substrate assembly semiconductor package including the same and method of manufacturing 1HE semiconductor package
CN110875291B (zh) * 2018-09-04 2024-03-26 三星电子株式会社 基板组件、半导体封装件和制造该半导体封装件的方法
CN110828496A (zh) * 2019-11-15 2020-02-21 华天科技（昆山）电子有限公司 半导体器件及其制造方法

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