CN107527900A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN107527900A
CN107527900A CN201710310125.8A CN201710310125A CN107527900A CN 107527900 A CN107527900 A CN 107527900A CN 201710310125 A CN201710310125 A CN 201710310125A CN 107527900 A CN107527900 A CN 107527900A
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CN
China
Prior art keywords
semiconductor chip
semiconductor
substrate
group
semiconductor packages
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Pending
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CN201710310125.8A
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English (en)
Inventor
徐光仙
姜明成
金沅槿
朴辰遇
崔容元
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN107527900A publication Critical patent/CN107527900A/zh
Pending legal-status Critical Current

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Abstract

一种半导体封装包括衬底、堆叠在衬底上的多个半导体芯片以及接合到所述多个半导体芯片的下表面的多个接合层。所述多个接合层可以被分成根据到衬底的距离而各自具有不同物理性质的多个组。

Description

半导体封装
本申请要求于2016年6月20日在韩国知识产权局提交的韩国专利申请No.10-2016-0076669的优先权，其公开通过引用全部并入于此。
技术领域
本发明构思涉及一种半导体封装。
背景技术
由于电子工业的快速发展和用户需求，电子设备已经小型化、多功能化并且存储容量增加。因此，已经出现了使在电子设备中使用的半导体封装小型化、多功能化并且存储容量增加的需求。为了满足这些需求，已经开发了包括多个半导体芯片的半导体封装。
发明内容
根据本发明构思的原理的半导体封装可以具有减少的翘曲和提高的可靠性。
根据本发明构思的原理，一种半导体封装可以包括衬底、堆叠在衬底上的多个半导体芯片以及接合到所述多个半导体芯片的下表面的多个接合层。另外，所述多个接合层可以被分成根据到衬底的距离而具有不同物理性质的多个组。
根据本发明构思的原理，一种半导体封装可以包括衬底和通过具有不同物理性质的接合层堆叠在衬底上的多个半导体芯片。
根据本发明构思的原理，一种半导体封装可以包括：衬底；堆叠在衬底上的半导体芯片；穿过半导体芯片的通孔；布置在半导体芯片之间并连接到通孔的凸块；布置在半导体芯片之间、围绕所述凸块并且具有不同物理性质的接合层；以及围绕半导体芯片和接合层的成型部。
在根据本发明构思的原理的示例性实施例中，一种半导体封装包括：衬底；各自堆叠在衬底上的至少一个半导体芯片的第一组、第二组和第三组；穿过半导体芯片的通孔；布置在半导体芯片之间并连接到通孔的凸块；布置在半导体芯片之间、围绕所述凸块的接合层，其中每个接合层根据到衬底的距离而具有不同的物理性质；以及围绕半导体芯片和接合层的成型部。
附图说明
根据结合附图给出的以下详细描述，将更清楚地理解本发明构思的以上和其他方面、特点和其他优点，在附图中：
图1是根据本发明构思的示例实施例的半导体封装的截面图；
图2至图6是根据示例实施例的半导体封装的截面图；
图7至图11是示出了根据示例实施例的制造半导体封装的方法的示图；
图12是根据示例实施例的半导体封装的截面图；
图13是根据示例实施例的包括半导体封装的封装模块的示例的示图；
图14是根据示例实施例的包括半导体封装的电子系统的示例的框图；以及
图15是根据本发明构思的示例实施例的包括半导体封装的存储卡的示例的框图。
具体实施方式
根据本发明构思的原理的半导体封装可以包括堆叠在衬底上的多个半导体芯片，所述多个半导体芯片之间具有接合层。可以改变每个接合层的物理性质(例如热膨胀系数、杨氏模量、固化收缩程度或层厚度)，以便抵消整个封装的翘曲，从而提高可靠性。
图1是根据本发明构思的原理的半导体封装的示例实施例的截面图。
参考图1，半导体封装100可以包括顺序堆叠的第一半导体芯片110、第二半导体芯片120和第三半导体芯片130。此外，半导体封装100可以包括第一接合层140a和第二接合层140b。
第一半导体芯片110可以包括诸如硅的半导体材料，并且可以包括电路布线层111和通孔115。第一半导体芯片110可以被解释为包括安装在其上的第二半导体芯片120在内的衬底。电路布线层111可以布置为与第一半导体芯片110的下表面110a相邻。例如，电路布线层111可以包括集成电路，例如存储器电路、逻辑电路或其组合。通孔115可以穿过第一半导体芯片110以电连接到电路布线层111。氮化硅层113可以覆盖电路布线层111。外部焊球114可以布置在第一半导体芯片110的下表面110a上，并且可以通过焊盘112电连接到电路布线层111。第一半导体芯片110的下表面110a可以用作有源表面。通孔115可以包括形成在其上的连接焊盘117。
第一半导体芯片110可以包括堆叠在其上的多个第二半导体芯片120，第二半导体芯片120可以包括集成电路层121和通孔125。在示例实施例中，集成电路层121可以包括存储器电路。通孔125可以穿过第二半导体芯片120以电连接到集成电路层121。可以形成连接到通孔125的导电焊盘123和127。第二半导体芯片120的下表面120a可以用作有源表面。第一凸块119可以形成在第二半导体芯片120的下表面120a上，以允许第二半导体芯片120电连接到第一半导体芯片110。在示例实施例中，第一凸块119可以形成在第一半导体芯片110和第二半导体芯片120之间。第一凸块119可以与导电焊盘123接触。在图1的示例实施例中，七个第二半导体芯片120被示出为堆叠在第一半导体芯片110上，但是本发明构思不限于此；例如，第二半导体芯片120的数量可以变化。在安装多个第二半导体芯片120的实施例中，第二凸块129可以形成在第二半导体芯片120之间。通过第二凸块129，第二半导体芯片120可以彼此电连接。第二凸块129可以与导电焊盘123和127接触。
第三半导体芯片130可以安装在第二半导体芯片120上。第三半导体芯片130的下表面130a可以用作有源表面。另外，集成电路层131可以包括存储器电路。在示例实施例中，第三半导体芯片130可以通过不包括通孔而与第一半导体芯片110和第二半导体芯片120不同，并且可以具有与第二半导体芯片120的厚度不同的厚度。在示例实施例中，第三半导体芯片130可以比第二半导体芯片120厚。通过控制第三半导体芯片130的厚度，可以控制完成的半导体封装的最终厚度。第三凸块139可以形成在第二半导体芯片120和第三半导体芯片130之间。第三半导体芯片130可以通过第三凸块139电连接到第二半导体芯片120。然而，在示例实施例中，可以省略第三半导体芯片130。
接合层140可以形成在半导体芯片110、120和130之间。在示例实施例中，接合层140可以被设置为包括绝缘材料的非导电聚合物带。接合层140可以插入在凸块119、129和139之间，以防止凸块119、129和139之间发生电短路。
第一凸块119、第二凸块129和接合层140可以接合到相应的第二半导体芯片120的下表面120a，并且第二半导体芯片120可以堆叠在第一半导体芯片110上，使得第二半导体芯片120的下表面120a可以在第一半导体芯片110的上表面110b的方向上取向。第三凸块139和接合层140可以接合到第三半导体芯片130的下表面130a，并且第三半导体芯片130可以堆叠在第二半导体芯片120上，使得第三半导体芯片130的下表面130a可以在第一半导体芯片110的上表面110b的方向上取向。
在示例实施例中，接合到与第一半导体芯片110相邻地布置的四个第二半导体芯片120的下表面120a的第一接合层140a可以具有与接合到剩余的三个第二半导体芯片120的下表面120a和第三半导体芯片130的下表面130a的第二接合层140b不同的物理性质。第一接合层140a和第二接合层140b可以具有不同的固化收缩程度。在示例实施例中，第一接合层140a的固化收缩程度可以比第二接合层140b的固化收缩程度高。相反，在特定示例实施例中，第一接合层140a的固化收缩程度可以比第二接合层140b的固化收缩程度低。可以选择第一接合层140a和第二接合层140b以减少半导体封装100的翘曲。在示例实施例中，在仅使用第一接合层140a将第二半导体芯片120和第三半导体芯片130堆叠在第一半导体芯片110上，从而引起向下凹的翘曲(即，“微笑”翘曲)的情况下，可以选择具有比与第一半导体芯片110相邻地布置的第一接合层140a的固化收缩程度低的固化收缩程度的第二接合层140b，从而减少“微笑”翘曲。相反，在仅使用第一接合层140a将第二半导体芯片120和第三半导体芯片130堆叠在第一半导体芯片110上，从而引起向上凹的翘曲(即，“哭泣”翘曲)的示例实施例中，可以选择具有比与第一半导体芯片110相邻地布置的第一接合层140a的固化收缩程度高的固化收缩程度的第二接合层140b，从而减少“哭泣”翘曲。
另外，第一接合层140a和第二接合层140b可以具有不同的热膨胀系数。第一接合层140a和第二接合层140b的热膨胀系数可以与第一接合层140a和第二接合层140b的固化收缩程度具有相同的趋势。也就是说，具有相对高的固化收缩程度的接合层也可以具有相对高的热膨胀系数。根据本发明构思的原理，以与上述固化收缩的情况相同的方法，可以选择具有不同热膨胀系数的第一接合层140a和第二接合层140b以减少翘曲。
具有相对高的固化收缩程度的接合层可以具有相对低的杨氏模量，并且可以具有相对低的玻璃化转变温度(Tg)。
半导体封装100还可以包括覆盖第二半导体芯片120和接合层140的模制膜180。
模制膜180可以包括垂直侧壁。模制膜180的垂直侧壁可以与第一半导体芯片110的侧壁共面。模制膜180的垂直侧壁可以与垂直于第一半导体芯片110的上表面的方向平行地布置。模制膜180的垂直侧壁可以布置为与第二半导体芯片120和第三半导体芯片130间隔开。模制膜180可以允许第三半导体芯片130的上表面暴露。
图2至图6是根据示例实施例的半导体封装的截面图。由于图2至图6的示例实施例与参照图1描述的示例实施例具有基本相同的组成(除了接合层之外)，因此在此不再重复对其他元件的详细描述，并且在下文将仅详细提供对接合层的描述。
参考图2，在示例实施例中，半导体封装100A可以包括根据到第一半导体芯片110的距离而具有不同物理性质的多个接合层140。多个接合层140可以被分成根据到第一半导体芯片110的距离而具有不同固化收缩程度的四个组。
为了减少半导体封装100A的翘曲，在示例实施例中，可以在远离第一半导体芯片110的方向上减小每个组的固化收缩程度。换言之，固化收缩程度可以在从第一组的接合层140a朝第四组的接合层140d的方向上减小。相反，在其他示例实施例中，可以在远离第一半导体芯片110的方向上增大每个组的固化收缩程度。换言之，固化收缩程度可以在从第一组的接合层140a朝第四组的接合层140d的方向上增大。
参考图3，在示例实施例中，半导体封装100B可以包括根据到第一半导体芯片110的距离而具有不同物理性质的多个接合层140。在示例实施例中，八个接合层140a、140b、140c、140d、140e、140f、140g和140h可以被分成根据到第一半导体芯片110的距离而具有不同固化收缩程度的八个组。
为了减少半导体封装100B的翘曲，在示例实施例中，各个接合层140a、140b、140c、140d、140e、140f、140g和140h的固化收缩程度可以在远离第一半导体芯片110的方向上逐渐减小。相反，在其他示例实施例中，各个接合层140a、140b、140c、140d、140e、140f、140g和140h的固化收缩程度可以在远离第一半导体芯片110的方向上逐渐增大。
参考图4，在示例实施例中，在半导体封装100C中，接合到与第一半导体芯片110相邻地布置的四个第二半导体芯片120的下表面120a的接合层140’的厚度t1可以不同于接合到剩余的三个半导体芯片120的下表面120a和第三半导体芯片130的下表面130a的接合层140’的厚度t2。在示例实施例中，与第一半导体芯片110相邻地布置的四个接合层140’的厚度t1可以大于剩余的三个接合层140’的厚度t2。相反，在其他示例实施例中，与第一半导体芯片110相邻地布置的四个接合层140’的厚度t1可以小于剩余的三个接合层140’的厚度t2。
可以选择接合层140’的厚度以减少半导体封装100C的翘曲。在示例实施例中，在使用具有相同厚度的接合层140’将第二半导体芯片120和第三半导体芯片130堆叠在第一半导体芯片110上，从而引起向下凹的翘曲(即，“微笑”翘曲)的示例实施例中，与第一半导体芯片110相邻地布置的接合层140’的厚度t1可以形成为相对增大，从而减少“微笑”翘曲。相反，在使用具有相同厚度的接合层140’将第二半导体芯片120和第三半导体芯片130堆叠在第一半导体芯片110上，从而引起向上凹的翘曲(即，“哭泣”翘曲)的示例实施例中，与第一半导体芯片110相邻地布置的接合层140’的厚度t1可以形成为相对减小(即，更薄)，从而减少“哭泣”翘曲。在示例实施例中，形成为厚的接合层140’的固化收缩可以导致相对大量的压缩应力。
参考图5，在示例实施例中，半导体封装100D可以包括多个接合层140’，这些接合层140’包括相同的材料并且根据到第一半导体芯片110的距离而具有不同的厚度。多个接合层140’可以被分成根据到第一半导体芯片110的距离而具有不同厚度的四个组。
为了减少半导体封装100D的翘曲，在示例实施例中，可以在远离第一半导体芯片110的方向上减小每个组的厚度。换言之，第一组的接合层140’的厚度t1可以逐步地减小到第四组的接合层140’的厚度t4。相反，在其他示例实施例中，可以在远离第一半导体芯片110的方向上增大每个组的厚度。换言之，第一组的接合层140’的厚度t1可以逐步地增大到第四组的接合层140’的厚度t4。
参考图6，在示例实施例中，半导体封装100E可以包括根据到第一半导体芯片110的距离而具有不同厚度的多个接合层140’。在示例实施例中，八个接合层140’可以根据到第一半导体芯片110的距离而具有不同的厚度t1至t8。
为了减少半导体封装100E的翘曲，在示例实施例中，各个接合层140’的厚度可以在远离第一半导体芯片110的方向上逐渐减小。相反，在其他示例实施例中，各个接合层140’的厚度可以在远离第一半导体芯片110的方向上逐渐增大。
此外，图1至图3中的示例实施例的方法可以与图4至图6中的示例实施例混合。
在示例实施例中，半导体封装可以包括具有不同的固化收缩程度和厚度的多组接合层。
为了减少半导体封装的翘曲，在示例实施例中，每组的固化收缩程度和厚度可以在远离衬底的方向上减小。相反，在其他示例实施例中，每组的固化收缩程度和厚度可以在远离衬底的方向上增大。
图7至图11是示出了根据示例实施例的制造半导体封装的方法的示图。
参考图7，载体衬底105可以在其上包括第一半导体芯片110。在示例实施例中，包括多个第一半导体芯片110的半导体衬底101可以通过载体接合层106接合到载体衬底105。例如，半导体衬底101可以被设置为包括诸如硅的半导体材料的晶片级半导体衬底。
第一半导体衬底110可以包括电路布线层111和通孔115。外部焊球114可以布置在第一半导体芯片110的下表面110a上，并且可以通过焊盘112电连接到电路布线层111。为了使第一半导体芯片电连接到在后续工艺中堆叠的第二半导体芯片，可以在通孔115上布置第一连接焊盘117。
参考图8，多个半导体芯片120和130可以安装在半导体衬底101的第一半导体芯片110上。第二半导体芯片120可以安装在半导体衬底101的第一半导体芯片110上，从而形成晶片上芯片(COW)结构。第二半导体芯片120可以包括集成电路层121和通孔125。第一凸块119可以形成在第二半导体芯片120的下表面120a上，使得第二半导体芯片120可以电连接到第一半导体芯片110。在示例实施例中，第一凸块119可以形成在第一半导体芯片110和第二半导体芯片120之间。在示例实施例中，七个第二半导体芯片120可以堆叠在第一半导体芯片110上。在这样的实施例中，第二凸块129可以形成在各个第二半导体芯片120之间。
第三半导体芯片130可以安装在第二半导体芯片120上。第三半导体芯片130可以不包括通孔。第三凸块139可以形成在第二半导体芯片120和第三半导体芯片130之间。
接合层140可以形成在半导体芯片110、120和130之间。在示例实施例中，接合层140可以被设置为包括绝缘材料的非导电聚合物带。
第一凸块119、第二凸块129和接合层140可以接合到相应的第二半导体芯片120的下表面120a，并且第二半导体芯片120可以堆叠在第一半导体芯片110上，使得第二半导体芯片120的下表面120a可以在第一半导体芯片110的上表面110b的方向上取向。第三凸块139和接合层140可以接合到第三半导体芯片130的下表面130a，并且第三半导体芯片130可以堆叠在第二半导体芯片120上，使得第三半导体芯片130的下表面130a可以在第一半导体芯片110的上表面110b的方向上取向。
在示例实施例中，接合到与第一半导体芯片110相邻地布置的四个第二半导体芯片120的下表面120a的第一接合层140a可以具有与接合到剩余的三个第二半导体芯片120的下表面120a和第三半导体芯片130的下表面130a的第二接合层140b不同的物理性质。例如，第一接合层140a和第二接合层140b可以具有不同的固化收缩程度。
在示例实施例中，堆叠第二半导体芯片120和第三半导体芯片130的工艺可以在大约300℃的温度下执行。在这样的实施例中，接合层140的一部分可以从第二半导体芯片120和第三半导体芯片130的外表面突出。
参考图9，覆盖第二半导体芯片120和第三半导体芯片130的模制膜180可以形成在半导体衬底101的上表面110b上。模制膜180可以包括绝缘聚合物材料(例如，环氧树脂模塑料)。
可以磨削模制膜180的上表面。如使用虚线所示，可以去除模制膜180的一部分，使得第三半导体芯片130的上表面可以向外暴露。在这样的实施例中，也可以磨削第三半导体芯片130，并且以这种方式可以调整第三半导体芯片130的厚度。备选地，可以不磨削第三半导体芯片130。
参考图10，模制膜180和第三半导体芯片130可以接合到粘合膜190。在示例实施例中，半导体衬底101可以倒置地布置在粘合膜190上，使得载体衬底105可以面朝上。随后，可以去除载体衬底105和载体接合层106。参考图11，可以对半导体衬底101和模制膜180应用切割工艺，使得可以完成接合到粘合膜190的半导体封装100的制造。例如，可以使用刀片420或激光器在垂直于半导体衬底101的下表面100a的方向上执行切割工艺。在上述切割工艺的描述中，可以以与图7至图9相同的方式使用术语“上表面”和“下表面”，而与上下方向无关。
随后，可以去除粘合膜190，并且可以分离半导体封装100。
图12是根据示例实施例的半导体封装的截面图。
参考图12，在根据本发明构思的原理的半导体封装200中，第一半导体芯片部分210和第二半导体芯片部分220可以堆叠在基底衬底10上，并且第三半导体芯片230可以堆叠为布置在第一半导体芯片部分210和第二半导体芯片部分220之间。在半导体封装200中，第一半导体芯片部分210、第三半导体芯片230和第二半导体芯片部分220可以顺序地堆叠在基底衬底10上。
外部连接端子12可以形成在基底衬底10的下表面上，而连接焊盘14、16和18可以形成在基底衬底10的上表面上。在示例实施例中，基底衬底10可以被设置为印刷电路板(PCB)或硅衬底。硅衬底可以包括半导体芯片。例如，外部连接端子12可以被设置为焊球。连接焊盘14、16和18可以通过基底衬底10的内部而电连接到外部连接端子12。连接焊盘14、16和18中的单个连接焊盘可以通过基底衬底10内部的上表面而连接到一个或多个不同的连接焊盘。连接焊盘14、16和18可以包括电连接到第一半导体芯片部分210的第一连接焊盘14、电连接到第二半导体芯片部分220的第二连接焊盘16和电连接到第三半导体芯片230的第三连接焊盘18。第一半导体芯片部分210可以通过第一接合线206电连接到第一连接焊盘14。第二半导体芯片部分220可以通过第二接合线216电连接到第二连接焊盘16。第三半导体芯片230可以通过第三接合线236电连接到第三连接焊盘18。
第一半导体芯片部分210可以包括多个第一半导体芯片210a、210b、210c和210d。在示例实施例中，多个第一半导体芯片210a、210b、210c和210d可以具有相同的面积。多个第一半导体芯片210a、210b、210c和210d可以在垂直于基底衬底10(即，垂直于由基底衬底10的顶面所描述的平面)的方向上顺序地堆叠在基底衬底10上。
多个第一半导体芯片210a、210b、210c和210d中的每一个可以包括连接到第一接合线206的第一焊盘202。第一焊盘202可以形成在多个第一半导体芯片210a、210b、210c和210d的有源表面上。多个第一半导体芯片210a、210b、210c和210d中的每一个可以堆叠为使得其有源表面面朝上。多个第一半导体芯片210a、210b、210c和210d中的每一个可以通过第一接合层214a堆叠在基底衬底10上。多个第一半导体芯片210a、210b、210c和210d可以包括预先接合到其下表面的第一接合层214a，并且多个第一半导体芯片210a、210b、210c和210d中的每一个可以顺序地堆叠在基底衬底10上。
多个第一半导体芯片210a、210b、210c和210d中的每一个可以在水平方向上移位之后被堆叠，使得可以暴露形成有第一焊盘202的其上表面的一部分。第一接合线206可以顺序地连接从布置在第一半导体芯片的顶部的第一半导体芯片210d到布置在其底部的第一半导体芯片210a所布置的第一焊盘202，并且可以连接到基底衬底10的第一连接焊盘14。然而，本发明构思不限于此。第一接合线206还可以将多个第一半导体芯片210a、210b、210c和210d的第一焊盘202分别连接到基底衬底10的第一连接焊盘14。
第三半导体芯片230可以堆叠在布置在第一半导体芯片的顶部的第一半导体芯片210d上。在示例实施例中，第三半导体芯片230可以具有比布置在第一半导体芯片的顶部的第一半导体芯片210d的面积小的面积。
第三半导体芯片230可以包括连接到第三接合线236的第三焊盘232。第三半导体芯片230可以通过第三管芯附着膜234接合到布置在第一半导体芯片的顶部的第一半导体芯片210d。第三接合线236可以将第三焊盘232连接到基底衬底10的第三连接焊盘18。
第二半导体芯片部分220可以堆叠在第一半导体芯片部分210和第三半导体芯片230上。第二半导体芯片部分220可以包括多个第二半导体芯片220a、220b、220c和220d。多个第二半导体芯片220a、220b、220c和220d可以具有相同的面积。多个第二半导体芯片220a、220b、220c和220d中的每一个可以具有比第三半导体芯片230的面积大的面积。多个第二半导体芯片220a、220b、220c和220d可以在垂直方向上顺序地堆叠在第一半导体芯片部分210和第三半导体芯片230上。多个第二半导体芯片220a、220b、220c和220d中的每一个可以堆叠为使得其有源表面面朝上。多个第二半导体芯片220a、220b、220c和220d中的每一个可以通过第二接合层214b堆叠在第一半导体芯片部分210和第三半导体芯片230上。多个第二半导体芯片220a、220b、220c和220d可以包括预先接合到其下表面的第二接合层214b，并且多个第二半导体芯片220a、220b、220c和220d中的每一个可以顺序地堆叠在第三半导体芯片230上。在示例实施例中，第二接合层214b可以具有与第一接合层214a不同的物理性质。例如，第二接合层214b可以具有与第一接合层214a不同的固化收缩程度。
多个第二半导体芯片220a、220b、220c和220d中的每一个可以包括连接到第二接合线216的第二焊盘212。多个第二半导体芯片220a、220b、220c和220d中的每一个可以在水平方向上移位之后被堆叠，使得可以暴露形成有第二焊盘212的其上表面的一部分。第二接合线216可以顺序地连接从布置在第二半导体芯片的顶部的第二半导体芯片220d到布置在其底部的第二半导体芯片220a所布置的第二焊盘212，并且可以连接到基底衬底10的第二连接焊盘16。然而，本发明构思不限于此。第二接合线216还可以将多个第二半导体芯片220a、220b、220c和220d的第二焊盘212分别连接到基底衬底10的第二连接焊盘16。
绝缘材料层250可以布置在第二半导体芯片部分220的下部，即布置在布置于第二半导体芯片的底部的第二半导体芯片220a的下表面上。绝缘材料层250可以形成为围绕第三半导体芯片230的至少一部分。绝缘材料层250的厚度t4可以大于第三半导体芯片230的厚度t3。例如，绝缘材料层250的厚度t4可以大于第一接合层214a的厚度t5或第二接合层214b的厚度t6。
因为第三半导体芯片230被绝缘材料层250围绕，第三半导体芯片230的厚度t3可以小于各个第一半导体芯片210a、210b、210c和210d的厚度t1或各个第二半导体芯片220a、220b、220c和220d的厚度t2。
绝缘材料层250可以围绕第三半导体芯片230，并且可以包括支撑堆叠在其上侧的第二半导体芯片部分220的材料。在示例实施例中，绝缘材料层250可以包括环氧树脂、丙烯酸树脂、聚酰亚胺或它们的组合。
绝缘材料层250可以以如下方式形成：将第三半导体芯片230与其接合，形成第一接合线206和第三接合线236，并且将绝缘材料层250涂覆在布置在第一半导体芯片的顶部的第一半导体芯片210d和第三半导体芯片230上。备选地，绝缘材料层250可以以如下方式形成：将绝缘材料层250接合到布置在第二半导体芯片的底部的第二半导体芯片220a的下表面，并且将第二半导体芯片220a接合到布置在第一半导体芯片的顶部的第一半导体芯片210d和第三半导体芯片230。
多个第一半导体芯片210a、210b、210c和210d以及多个第二半导体芯片220a、220b、220c和220d可以被设置为具有相同面积的同质半导体芯片(即，全部都可以是相同类型的半导体芯片)。例如，多个第一半导体芯片210a、210b、210c和210d以及多个第二半导体芯片220a、220b、220c和220d可以被设置为存储器半导体芯片。在示例实施例中，第三半导体芯片230可以被设置为提供在使用多个第一半导体芯片210a、210b、210c和210d以及多个第二半导体芯片220a、220b、220c和220d时所需的控制器、缓冲器、高速缓冲存储器、功率半导体器件的半导体芯片。例如，第三半导体芯片230可以被设置为控制器芯片、动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)或智能功率器件(IPD)。
包围第一半导体芯片部分210、第二半导体芯片部分220和第三半导体芯片230的整体的模制(或成型)层280可以形成在基底衬底10上。模制层280可以包围第一半导体芯片部分210、第二半导体芯片部分220和第三半导体芯片230的整体以及基底衬底10上的第一连接焊盘14、第二连接焊盘16和第三连接焊盘18，并且包围第一接合线206、第二接合线216和第三接合线236。在示例实施例中，模制层280可以包括环氧树脂模塑料(EMC)。
图13是根据本发明构思的原理的包括半导体封装的封装模块的示例的示图。图14是根据本发明构思的原理的包括半导体封装的电子系统的示例的框图。图15是根据本发明构思的原理的包括半导体封装的存储卡的示例的框图。
参考图13，封装模块1200可以被设置为具有与半导体集成电路芯片1220和四方扁平封装(QFP)半导体集成电路芯片1230相同的形式。半导体器件1220和1230可以包括根据本发明构思的原理的示例实施例的半导体封装中的至少一个。封装模块1200可以通过布置在衬底1210的一侧上的外部连接端子1240而连接到外部电子设备。
参考图14，电子系统1300可以包括控制器1310、输入/输出设备1320和存储器设备1330。控制器1310、输入/输出设备1320和存储器设备1330可以通过总线1350组合。
总线1350可以形成可以传送数据的通道。在示例实施例中，控制器1310可以包括以下项中的至少一个：微处理器、数字信号处理器、微控制器和执行与其相同的功能的逻辑元件。控制器1310和存储器设备1330可以包括根据示例实施例的半导体封装中的至少一个。输入/输出设备1320可以包括选自键区、键盘、显示设备等中的至少一个。存储器设备1330可以被设置为存储数据的设备。存储器设备1330可以存储由控制器1310运行的数据和/或命令等。存储器设备1330可以包括易失性存储器设备和/或非易失性存储器设备。备选地，存储器设备1330可以被设置为闪存。例如，应用本发明构思的闪存可以安装在诸如移动设备或台式计算机的信息处理系统上。闪存可以包括或实现为固态盘(SSD)。在这样的示例实施例中，电子系统1300可以在闪存中稳定地存储大量数据。电子系统1300还可以包括用于将数据发送到通信网络或从通信网络接收数据的接口1340。接口1340可以被设置为有线或无线类型。在示例实施例中，接口1340可以包括天线、有线或无线收发器等。在电子系统1300中，可以进一步设置未示出的应用芯片组、相机图像处理器(CIS)、输入/输出设备等。
电子系统1300可以被设置为移动系统、个人计算机、工业计算机、执行各种功能的逻辑系统等。例如，移动系统可以被设置为以下项之一：个人数字助理(PDA)、便携式计算机、web平板电脑、移动电话、无线电话、膝上型计算机、存储卡、数字音乐系统和信息发送/接收系统。在电子系统1300被设置为执行无线通信的装置的实施例中，电子系统1300可以用于通信接口协议，诸如第三代通信系统(例如，CDMA、GSM、NADC、E-TDMA、WCDAM和CDMA2000)。
参考图15，存储卡1400可以包括非易失性存储器设备1410和存储器控制器1420。
非易失性存储器设备1410和存储器控制器1420可以存储数据或读取存储的数据。非易失性存储器件1410可以包括根据本发明构思的原理的半导体封装中的至少一个。存储器控制器1420可以响应于主机的读取/写入请求而读取所存储的数据，或者控制非易失性存储器设备1410存储数据。
如上所述，根据本发明构思的示例实施例，可以提供具有减少的翘曲的半导体封装。另外，根据本发明构思的原理的示例实施例，可以提供具有改进的可靠性的半导体封装。
虽然以上已经示出并描述了示例实施例，但是本领域技术人员将清楚的是，在不脱离由所附权利要求限定的本发明构思的精神和范围的情况下，可以进行修改和改变。

Claims (20)

1.一种半导体封装，包括：
衬底；
多个半导体芯片，堆叠在所述衬底上；以及
多个接合层，接合到所述多个半导体芯片的下表面，
其中所述多个接合层被分成多个组，每个组根据到衬底的距离而具有不同的物理性质。
2.根据权利要求1所述的半导体封装，其中所述多个组中的每个组包括具有不同的固化收缩程度的材料。
3.根据权利要求2所述的半导体封装，其中所述多个组中的每个组包括固化收缩程度在远离所述衬底的方向上减小的材料。
4.根据权利要求2所述的半导体封装，其中所述多个组中的每个组包括固化收缩程度在远离所述衬底的方向上增大的材料。
5.根据权利要求1所述的半导体封装，其中所述多个组中的每个组包括具有不同的热膨胀系数的材料。
6.根据权利要求5所述的半导体封装，其中所述多个组中的每个组包括热膨胀系数在远离所述衬底的方向上减小的材料。
7.根据权利要求5所述的半导体封装，其中所述多个组中的每个组包括热膨胀系数在远离所述衬底的方向上增大的材料。
8.根据权利要求1所述的半导体封装，其中所述多个组中的每个组包括相同的材料，但具有不同的厚度。
9.根据权利要求8所述的半导体封装，其中所述多个组中的每个组的厚度在远离所述衬底的方向上减小。
10.根据权利要求8所述的半导体封装，其中所述多个组中的每个组的厚度在远离所述衬底的方向上增大。
11.根据权利要求1所述的半导体封装，其中所述多个组中的每个组具有不同的固化收缩程度和厚度。
12.根据权利要求11所述的半导体封装，其中所述多个组中的每个组包括固化收缩程度和厚度在远离所述衬底的方向上减小的材料。
13.根据权利要求11所述的半导体封装，其中所述多个组中的每个组包括固化收缩程度和厚度在远离所述衬底的方向上增大的材料。
14.根据权利要求1所述的半导体封装，其中所述多个接合层中的每个接合层被设置为包括绝缘材料的非导电聚合物带。
15.根据权利要求1所述的半导体封装，还包括穿过所述多个半导体芯片的通孔。
16.根据权利要求1所述的半导体封装，还包括插入在所述多个半导体芯片之间以将所述多个半导体芯片彼此电连接的连接凸块。
17.根据权利要求1所述的半导体封装，还包括将所述多个半导体芯片的至少一部分彼此电连接的导线。
18.一种半导体封装，包括：
衬底；以及
多个半导体芯片，通过接合层堆叠在所述衬底上，其中每个接合层具有选自以下项的不同物理性质：热膨胀系数、固化收缩程度和杨氏模量。
19.一种半导体封装，包括：
衬底；
半导体芯片，堆叠在所述衬底上；
通孔，穿过所述半导体芯片；
凸块，布置在所述半导体芯片之间并连接到所述通孔；
接合层，布置在所述半导体芯片之间，围绕所述凸块，并且具有不同的物理性质；以及
成型部，围绕所述半导体芯片和所述接合层。
20.根据权利要求19所述的半导体封装，其中所述不同的物理性质选自以下项：热膨胀系数、固化收缩程度、杨氏模量和厚度。
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