JP5343261B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5343261B2 JP5343261B2 JP2008294433A JP2008294433A JP5343261B2 JP 5343261 B2 JP5343261 B2 JP 5343261B2 JP 2008294433 A JP2008294433 A JP 2008294433A JP 2008294433 A JP2008294433 A JP 2008294433A JP 5343261 B2 JP5343261 B2 JP 5343261B2
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- 239000004065 semiconductor Substances 0.000 title claims description 162
- 238000004519 manufacturing process Methods 0.000 title claims description 38
- 230000005291 magnetic effect Effects 0.000 claims description 164
- 239000000463 material Substances 0.000 claims description 164
- 238000000034 method Methods 0.000 claims description 46
- 239000002313 adhesive film Substances 0.000 claims description 19
- 229920005992 thermoplastic resin Polymers 0.000 claims description 8
- 238000005520 cutting process Methods 0.000 claims description 5
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- 230000001070 adhesive effect Effects 0.000 description 70
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- 229920005989 resin Polymers 0.000 description 16
- 239000011347 resin Substances 0.000 description 16
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- 238000007789 sealing Methods 0.000 description 10
- 230000006870 function Effects 0.000 description 7
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- 230000005415 magnetization Effects 0.000 description 6
- 229920001187 thermosetting polymer Polymers 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000005294 ferromagnetic effect Effects 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 239000000155 melt Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 101100329534 Haloarcula marismortui (strain ATCC 43049 / DSM 3752 / JCM 8966 / VKM B-1809) csg1 gene Proteins 0.000 description 3
- 101100422777 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) SUR1 gene Proteins 0.000 description 3
- 230000008859 change Effects 0.000 description 3
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- 230000003213 activating effect Effects 0.000 description 2
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- 230000007480 spreading Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
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- 238000003860 storage Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Description
)デバイスが注目されている。MRAMデバイスは、半導体集積回路に形成された複数のメモリセルを用いて不揮発のデータ記録を行ない、かつ、メモリセルの各々に対してランダムアクセスが可能な不揮発性記憶装置である。
磁気シールド体が複数の磁気シールド材に分割される。複数の磁気シールド材が、熱可塑性樹脂を含む接着フィルムに貼り付けられる。複数の磁気シールド材が貼り付けられた接着フィルムを切断することにより、接着フィルムと磁気シールド材との積層構造を有する接着フィルム付き磁気シールド材が複数個形成される。接着フィルム付き磁気シールド材の接着フィルムが、集積された複数の磁気記憶素子を有する半導体チップに接着される。磁気シールド体は表面側からダイシングされることにより複数の磁気シールド材に分割される。複数の磁気シールド材の表面側が接着フィルムに貼り付けられる。
(実施の形態1)
はじめに本実施の形態の半導体装置の構成について説明する。
図5〜図10は、本発明の実施の形態1における半導体装置の製造方法を工程順に示す概略断面図である。図5を参照して、まずリードフレームLFが準備される。
図16は、本発明の実施の形態2における半導体装置の構成を概略的に示す断面図である。図16を参照して、本実施の形態の半導体装置は、半導体チップCHと、接着材ADと、磁気シールド材PMとを有している。接着材ADおよび磁気シールド材PMは、この順序で半導体チップCHの上に積層されている。つまり、半導体チップCHには、接着材ADを介して磁気シールド材PMが接着されている。
図20〜図22は、図16に示す半導体装置の製造方法の第1の例を工程順に示す概略断面図である。図20を参照して、まずMRAMデバイスを有する半導体装置が製造される。図21を参照して、この半導体チップCH上に、たとえばDAFよりなるフィルム状の接着材ADが加熱状態で載置される。図22を参照して、この接着材AD上に磁気シールド材PMが加熱状態で載置されることにより磁気シールド材PMと半導体チップCHとが接着材ADにより接着される。これにより、図16に示すのと同様の半導体装置を製造することができる。
図23〜図25は、図16に示す半導体装置の製造方法の第2の例を工程順に示す概略斜視図である。図23を参照して、まず個片化前の磁気シールド材(磁気シールド体)PMが、半導体チップCHのサイズに合わせて切断されて個片化される(図23(A))。その個片化された複数個の磁気シールド材PMの各々が、たとえばソータなどの装置でダイシングテープDT2上の接着材(たとえばDAF)AD上に移動されて載置される。
図26〜図28は、図16に示す半導体装置の製造方法の第3の例を工程順に示す概略斜視図である。図26を参照して、まずダイシングテープDT5上にフィルム状の接着材(たとえばDAF)ADと個片化前の磁気シールド材(磁気シールド体)PMとが貼り付けられる。この後、ダイサーDCにより接着材ADと磁気シールド材PMとが同時に切断される。これにより、磁気シールド材PMは複数個の磁気シールド材に個片化される。
上記の実施の形態5においては、図26で磁気シールド材PMがダイサーDCで複数個に切断されることにより、切断後の磁気シールド材PMに図29に示すようなバリPMBが生じる。このバリPMBは、たとえばダイサーにより切断された際には、ダイサーを当てる面(上面)の反対側の面(下面)に生じる。
Claims (2)
- 磁気シールド体を複数の磁気シールド材に分割する工程と、
複数の前記磁気シールド材を、熱可塑性樹脂を含む接着フィルムに貼り付ける工程と、
複数の前記磁気シールド材が貼り付けられた前記接着フィルムを切断することにより、前記接着フィルムと前記磁気シールド材との積層構造を有する接着フィルム付き磁気シールド材を複数個形成する工程と、
前記接着フィルム付き磁気シールド材の前記接着フィルムを、集積された複数の磁気記憶素子を有する半導体チップに接着する工程と、を備え、
前記磁気シールド体は表面側からダイシングされることにより複数の前記磁気シールド材に分割され、
複数の前記磁気シールド材の前記表面側が前記接着フィルムに貼り付けられた、半導体装置の製造方法。 - 前記磁気シールド材の外形サイズは、前記半導体チップの外形サイズよりも小さい、請求項1に記載の半導体装置の製造方法。
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JP2010123666A JP2010123666A (ja) | 2010-06-03 |
JP5343261B2 true JP5343261B2 (ja) | 2013-11-13 |
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Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5470602B2 (ja) * | 2009-04-01 | 2014-04-16 | ルネサスエレクトロニクス株式会社 | 磁気記憶装置 |
JP2013149789A (ja) * | 2012-01-19 | 2013-08-01 | Dainippon Printing Co Ltd | 半導体装置、メタルシールド板およびメタルシールド用シート |
JP6122353B2 (ja) * | 2013-06-25 | 2017-04-26 | ルネサスエレクトロニクス株式会社 | 半導体パッケージ |
WO2015033396A1 (ja) * | 2013-09-04 | 2015-03-12 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP6010005B2 (ja) | 2013-09-09 | 2016-10-19 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP6074345B2 (ja) | 2013-09-24 | 2017-02-01 | 株式会社東芝 | 半導体装置及びその製造方法 |
KR102538175B1 (ko) | 2016-06-20 | 2023-06-01 | 삼성전자주식회사 | 반도체 패키지 |
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JP3605651B2 (ja) * | 1998-09-30 | 2004-12-22 | 日立化成工業株式会社 | 半導体装置の製造方法 |
JP2003213224A (ja) * | 2002-01-23 | 2003-07-30 | Sumitomo Bakelite Co Ltd | 半導体用接着フィルム、半導体装置、及び半導体装置の製造方法。 |
JP4471563B2 (ja) * | 2002-10-25 | 2010-06-02 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP4147466B2 (ja) * | 2002-12-10 | 2008-09-10 | ソニー株式会社 | 磁気メモリ装置 |
US8124425B2 (en) * | 2007-02-27 | 2012-02-28 | Renesas Electronics Corporation | Method for manufacturing magnetic memory chip device |
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