WO2015033396A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- WO2015033396A1 WO2015033396A1 PCT/JP2013/073755 JP2013073755W WO2015033396A1 WO 2015033396 A1 WO2015033396 A1 WO 2015033396A1 JP 2013073755 W JP2013073755 W JP 2013073755W WO 2015033396 A1 WO2015033396 A1 WO 2015033396A1
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- shield plate
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- lower shield
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- Embodiments described herein relate to a semiconductor device and a manufacturing method thereof.
- a semiconductor device affected by such a magnetic field can be preferably operated by reducing the influence of an external magnetic field by a magnetic shield.
- a magnetic shield used in a semiconductor device for example, by covering an upper surface and side surfaces of a semiconductor chip with an electromagnetic wave absorbing mold resin in which a resin having a high magnetic permeability is contained as a filler, the influence of an external magnetic field on the semiconductor device is affected. What is reduced is known.
- Embodiments described herein provide a semiconductor device having a higher magnetic shielding effect and a method for manufacturing the same.
- the semiconductor device includes a substrate on which a first contact portion is formed, and a lower shield plate using a magnetic material provided on the substrate so as to avoid the first contact portion.
- the semiconductor device electrically connects a semiconductor chip having a second contact portion provided on the lower shield plate and electrically connected to the first contact portion, and the first contact portion and the second contact portion. Connecting material to be connected.
- the semiconductor device includes an upper shield plate using a magnetic body provided on the semiconductor chip so as to avoid the second contact portion and the connecting material. At least one of the lower shield plate and the upper shield plate has a side wall portion whose end is bent toward the other shield plate and whose tip is connected to the other shield plate.
- FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment.
- 2 is a schematic side view of the semiconductor device.
- FIG. It is a schematic plan view showing the manufacturing method of the same semiconductor device. It is a schematic side view which shows the manufacturing method of the same semiconductor device. It is a schematic plan view showing the manufacturing method of the same semiconductor device. It is a schematic side view which shows the manufacturing method of the same semiconductor device. It is a schematic side view which shows the manufacturing method of the same semiconductor device. It is a schematic side view which shows the manufacturing method of the same semiconductor device. It is a schematic plan view showing the manufacturing method of the same semiconductor device. It is a schematic side view which shows the manufacturing method of the same semiconductor device.
- FIG. 6 is a schematic plan view of a semiconductor device according to a second embodiment. 2 is a schematic side view of the semiconductor device.
- FIG. 1 is a schematic plan view of the semiconductor device according to the first embodiment.
- FIG. 2A is a cross-sectional view taken along the line II ′ of FIG. 1, and FIG. FIG.
- the semiconductor device includes a substrate 1, a lower shield plate 3 attached to the substrate 1 via a first adhesive 2 having an insulating property, The semiconductor chip 5 mounted on the lower shield plate 3 via the insulating second adhesive 4 and the first insulating resin 6 covering the upper surface and part of the side surface of the semiconductor chip 5 And an upper shield plate 7 provided on the upper surface of the first insulating resin 6.
- the lower shield plate 3 is provided with a side wall portion 32 extending in the stacking direction, and the side wall portion 32 is in contact with the lower surface of the upper shield plate 7. Further, these components are embedded with the second insulating resin 9.
- the second insulating resin 9 is omitted for illustration purposes.
- the substrate 1 uses an insulating material such as ceramic, resin, or silicon (Si) whose surface is oxidized.
- a wiring (not shown) and a contact portion 11 (first contact portion) connected to the wiring are formed.
- the wiring and contact portion 11 is formed by printing, vapor deposition, or other methods using a metal such as copper.
- the contact portions 11 are pads for bonding to the semiconductor chip 5, and are arranged at a predetermined pitch in a direction in which the lower shield plate 3 extends along the both side surfaces of the lower shield plate 3 (hereinafter referred to as “first direction”). Has been.
- the lower shield plate 3 is formed as a rectangle having a first direction as a longitudinal direction with the first adhesive 2 attached to the lower surface, and the length in the first direction is the first length of the semiconductor chip 5. It is formed longer than the length in the direction. Further, the width of the lower shield plate 3 in the direction orthogonal to the first direction (hereinafter referred to as “second direction”) is narrower than the distance between the contact portions 11, and the width of the semiconductor chip 5 in the second direction. It is formed in substantially the same way.
- the lower shield plate 3 is made of a material with high magnetic permeability. In this embodiment, a magnetic alloy containing iron such as PC permalloy (Ni—Mo, Cu—Fe) is used. In the present embodiment, the thickness of the lower shield plate 3 is set to about 50 ⁇ m to 150 ⁇ m.
- the lower shield plate 3 has a side wall portion 32.
- the side wall portion 32 is formed by bending a magnetic alloy plate. Therefore, in the present embodiment, the thickness of the lower shield plate 3 and the thickness of the side wall 32 are substantially the same.
- the semiconductor chip 5 includes an integrated circuit, and in this embodiment, a storage device that stores a plurality of data by magnetism is mounted.
- This storage device may be one that writes data by, for example, spin injection, and discriminates the written data by resistance change due to the tunnel magnetoresistance effect.
- the semiconductor chip 5 has a second adhesive 4 attached to the lower surface and has contact portions 12 (second contact portions) on both sides of the upper surface in the second direction.
- the contact portion 12 is electrically connected to the contact portion 11 via bonding wires 51 that are a plurality of connecting materials.
- the upper shield plate 7 has a first insulating resin 6 attached to the lower surface and is formed as a rectangle having the first direction as a longitudinal direction, and the width in the second direction is the second width of the contact portion 12. It is narrower than the width in the direction, and the length in the first direction is substantially the same as that of the lower shield plate 3.
- the upper shield plate 7 is made of a material having a high magnetic permeability like the lower shield plate 3. In this embodiment, a magnetic alloy containing iron such as PC permalloy (Ni—Mo, Cu—Fe) is used.
- the thickness of the upper shield plate 7 is about 50 ⁇ m to 150 ⁇ m in this embodiment.
- the upper shield plate 7 is in contact with the lower shield plate via the side wall portion 32. Accordingly, the upper shield plate 7 together with the lower shield plate 3 forms a magnetic shield that protects the semiconductor device 5 from an external magnetic field.
- the lower surface of the semiconductor chip 5 is covered with the lower shield plate 3, the upper surface is covered with the upper shield plate 7, and the side surfaces are covered with the side wall portions 32.
- the width of the lower shield plate 3 in the second direction is formed to be approximately the same as the width of the semiconductor chip 5, and the width of the upper shield plate 7 in the second direction is slightly smaller than the width of the semiconductor chip 5.
- the main part of the semiconductor chip 5 is preferably protected from an external magnetic field.
- the widths of the lower shield plate 3 and the upper shield plate 7 are set such that the contact between the bonding wires 51 and the contact portions 11 and 12 drawn from the semiconductor chip 5 and the shield plates 3 and 7 can be prevented. Yes.
- the semiconductor device can protect the lower surface of the semiconductor device 5 from the external magnetic field, and can perform a good operation.
- the width of the lower shield plate 3 in the second direction may be substantially the same as the width of the upper shield plate 7 in the second direction as long as the main part of the semiconductor chip 5 is protected.
- FIGS. 4A, 6 ⁇ / b> A, and 9 ⁇ / b> A are used.
- FIG. 4 (b), FIG. 6 (b) and FIG. 9 (b) are II-II 'cut sectional views, respectively.
- FIG. 7 is sectional drawing which shows the manufacturing method.
- a substrate 1 on which wiring and contact portions 11 (not shown) are formed is prepared.
- the substrate 1 is a rectangle having a first direction as a longitudinal direction and a second direction as a width direction.
- Each contact portion 11 is formed along the longitudinal direction with a predetermined space in the width direction.
- the lower shield plate 3 extending in the first direction is disposed in the space for two rows formed in the width direction of the contact portion 11 of the substrate 1, and is adhered by the first adhesive 2.
- the lower shield plate 3 is disposed on the substrate 1 in a state where the first adhesive 2 is adhered or applied to the back surface of the lower shield plate 3.
- the first adhesive 2 may be applied to the substrate 1 side.
- the semiconductor chip 5 is mounted on the lower shield plate 3.
- the semiconductor chip 5 is disposed on the lower shield plate 3 so that the contact portion 12 formed on the upper surface corresponds to the contact portion 11 formed on the substrate 1.
- the second adhesive 4 is adhered or applied to the lower surface of the semiconductor chip 5, and the semiconductor chip 5 is disposed on the lower shield plate 3.
- the second adhesive 4 can be adhered or applied on the lower shield plate 3 and the semiconductor device 5 can be disposed thereon.
- the contact portion 12 of the semiconductor chip 5 and the contact portion 11 of the substrate 1 are electrically connected by the bonding wire 51.
- the width of the semiconductor chip 5 in the second direction is approximately the same as the width of the lower shield plate 3 in the second direction. Accordingly, it is possible to prevent the bonding wire 51 drawn from the semiconductor chip 5 from contacting the lower shield plate 3.
- a first insulating resin 6 having a predetermined thickness and using a thermosetting resin is formed on one surface of the upper shield plate 7.
- a thermosetting acrylic resin is used as the first insulating resin 6, but various plastic materials such as an ultraviolet curable resin can be applied.
- the upper shield plate 7 is pressed against the semiconductor device 5 from the surface on which the first insulating resin 6 is formed so as to avoid the contact portion 12 and the bonding wire 51.
- the lower shield plate 3 and the upper shield plate 7 are brought into contact with each other through a side wall portion 32 extending from the shield plate 3 to the upper shield plate 7.
- the upper shield plate 7 is disposed in a space between the contact portions 12 on the upper surface of the semiconductor chip 5.
- the upper surface of the lower shield plate 3, both side surfaces of the side wall portion 32, and the semiconductor chip 5 are embedded with the first insulating resin 6.
- the first insulating resin 6 is contained in the region directly below the upper shield plate 7, but it is actually pushed out from the side surface of the upper shield plate 7 and is a semiconductor. It is thought that it spreads over the upper surface of the chip 5 and the like. Therefore, the thickness of the first insulating resin 6 may be set to be equal to or lower than the height from the upper surface of the lower shield plate 3 to the upper end of the side wall portion 32. It is also possible to remove a part of the spread first insulating resin 6, and in advance between the portion that contacts the upper surface of the semiconductor chip 5 and the portion that contacts the upper surface of the lower shield plate 3. It may be possible to provide a height difference.
- the first insulating resin 6 is cured by heat or the like. Further, by embedding the entire structure with the second insulating resin 9, as shown in FIGS. 1 and 2, the semiconductor device according to this embodiment is manufactured.
- the width of the upper shield plate 7 in the second direction is smaller than the width of the semiconductor device 5 in the second direction and the width of the lower shield plate 3 in the second direction. Therefore, the contact between the bonding wire 51 and the upper shield plate 7 can be suitably prevented.
- the upper shield plate 7 having a predetermined thickness and having the first insulating resin 6 using a thermosetting resin formed on the back surface is transferred from the back surface to the semiconductor.
- the chip is pressed against the chip 5, and the lower shield plate 3 and the upper shield plate 7 are brought into contact with each other through the side wall 32 extending from the lower shield plate 3 to the upper shield plate 7. Therefore, for example, compared with the case where an adhesive layer is formed on the back surface of the upper shield plate 7 and adhered to the side wall portion 32 of the lower shield plate 3, the upper shield plate 7 and the lower shield plate 3 can be brought into good contact with each other. It is thought that.
- the upper surface of the lower shield plate 3, both side surfaces of the side wall portion 32, and the semiconductor chip 5 are embedded with the first insulating resin 6. Therefore, for example, it is considered that the resin can be easily filled as compared with the case where the upper shield plate 7 is bonded to the side wall portion 32 or the semiconductor chip 5 and then embedded. Furthermore, the number of processes is reduced as compared with such a method.
- the lower shield plate 3 is provided with the side wall portion 32, and the upper shield plate 7 is not provided with the side wall portion. Therefore, the first insulating resin 6 can be easily formed on the lower surface of the upper shield plate 7.
- a side wall portion can be provided on the upper shield plate 7, and a side wall portion can be provided on both the lower shield plate 3 and the upper shield plate 7. Further, for example, it is conceivable to increase the contact area between the lower shield plate 3 and the upper shield plate 7 by bending the upper end of the side wall portion 32.
- FIG. 10 is a schematic plan view of the semiconductor device according to the first embodiment.
- FIG. 11A is a cross-sectional view taken along the line II ′ of FIG. 10, and FIG. FIG.
- the semiconductor device according to the second embodiment is basically configured in the same manner as the semiconductor device according to the first embodiment. However, as shown in FIGS. The difference is that both ends of the direction are bent. In other words, in the present embodiment, two side wall portions 32 are provided on the lower shield plate 3. These side wall portions 32 are in contact with the upper shield plate 7 from the lower surface.
- the lower shield plate 3 and the upper shield plate 7 function as a box-type magnetic shield having no walls on a pair of opposed side surfaces (side surfaces from which the bonding wires 51 are drawn).
- the path for transmitting the magnetic field received by the lower shield plate 3 to the upper shield plate 7 or the magnetic field received by the upper shield plate 7 to the lower shield plate 3 increases. Therefore, it is considered that the shielding property can be improved as compared with the semiconductor device according to the first embodiment.
- two side wall portions 32 are formed on the lower shield plate 3, but two side wall portions may be provided on the upper shield plate 7, for example, one on the lower shield plate 3 and one upper portion. It is also possible to provide one side wall portion on the shield plate 7.
- FIG. 12 14 and 17 are schematic plan views for illustrating the method for manufacturing the semiconductor memory device according to the present embodiment
- FIG. 13 (b), FIG. 15 (b) and FIG. 18 (b) are II-II 'cut sectional views, respectively.
- FIG. 16 is a cross-sectional view showing the same manufacturing method.
- the lower shield plate 3 is arranged on the substrate 1 and the first adhesive 2 is used. Adhere.
- the lower shield plate 3 according to the present embodiment is basically the same as the lower shield plate 3 according to the first embodiment, but in the present embodiment, the lower shield plate 3 is provided with two side wall portions 32. Is different.
- the semiconductor chip 5 is mounted on the lower shield plate 3 as in the first embodiment.
- the contact portion 12 of the semiconductor chip 5 and the contact portion 11 of the substrate 1 are electrically connected by the bonding wire 51. Accordingly, as in the first embodiment, it is possible to prevent the bonding wire 51 drawn from the semiconductor chip 5 from contacting the lower shield plate 3.
- the first insulating resin 6 is formed on one surface of the upper shield plate 7 as in the first embodiment.
- the upper shield plate 7 is pressed against the semiconductor device 5 through a side wall portion 32 extending from the lower shield plate 3 to the upper shield plate 7. The lower shield plate 3 and the upper shield plate 7 are brought into contact with each other.
- the semiconductor device according to the present embodiment is manufactured as shown in FIGS.
- the lower shield plate 3 is provided with two side wall portions 32. Therefore, even if one side wall portion 32 is not in contact with the upper shield plate 7, it is considered that one side wall portion 32 can be brought into contact with the upper shield plate 7. Therefore, it is possible to improve the yield of the magnetic shield.
- FIG. 19 is a schematic plan view of the semiconductor device according to the first embodiment.
- FIG. 20A is a cross-sectional view taken along the line II ′ of FIG. 19, and FIG. FIG.
- the semiconductor device according to the third embodiment is basically configured in the same manner as the semiconductor device according to the first embodiment.
- the first shield substrate 3 has a first shield plate to a first shield plate.
- the contact portion 11 is also formed in the portion exposed in the direction of the semiconductor chip.
- the bonding wire 51 is drawn out from the semiconductor chip 5 in the first direction and connected to the contact portion 11 formed in the exposed portion. It is different in point. According to the semiconductor device according to the present embodiment, even if the number of bonding wires 51 drawn from the semiconductor chip 5 is increased to some extent, it is possible to easily make a contact.
- FIG. 23 and FIG. 26 are schematic plan views for illustrating the manufacturing method of the semiconductor memory device according to the present embodiment
- FIG. 22 (b), FIG. 24 (b) and FIG. 27 (b) are II-II 'cut sectional views, respectively.
- FIG. 25 is a cross-sectional view showing the same manufacturing method.
- a substrate 1 on which wiring and contact portions 11 (not shown) are formed is prepared.
- the substrate 1 is formed in substantially the same manner as the substrate 1 according to the first embodiment, but differs in that a contact portion 11 is also formed in a portion exposed from the lower shield plate 3 in the first direction.
- the lower shield plate 3 is disposed in the space formed in the concave shape of the contact portion 11 of the substrate 1 in the same manner as in the first embodiment, and is adhered by the first adhesive 2.
- the semiconductor chip 5 is mounted on the lower shield plate 3.
- the semiconductor chip 5 is disposed on the lower shield plate 3 so that the contact portion 12 formed on the upper surface corresponds to the contact portion 11 formed on the substrate 1.
- the semiconductor chip 5 according to the present embodiment is manufactured in substantially the same manner as the semiconductor chip 5 according to the first embodiment. However, the contact portion 12 is also formed on the upper surface in the vicinity of the exposed portion. Is different.
- the contact portion 12 of the semiconductor chip 5 and the contact portion 11 of the substrate 1 are electrically connected by a bonding wire 51.
- the first insulating resin 6 is formed on one surface of the upper shield plate 7 as in the first embodiment.
- the upper shield plate 7 is pressed against the semiconductor device 5 as in the first embodiment, and the side shield 32 extends from the lower shield plate 3 to the upper shield plate 7.
- the lower shield plate 3 and the upper shield plate 7 are brought into contact with each other.
- the upper shield plate 7 is disposed in a concave space formed by the contact portion 12 on the upper surface of the semiconductor chip 5.
- the semiconductor device according to this embodiment is manufactured as shown in FIGS.
- the upper end of the side wall portion 32 is formed substantially perpendicular to the upper shield plate 7.
- the upper end of the side wall portion 32 may be formed so as to form a surface substantially parallel to the upper shield plate 7.
- Such a configuration can be easily realized by simply bending a plate made of a magnetic material when the lower shield plate 3 is formed. According to such a configuration, it is considered that the contact area between the lower shield plate 3 and the upper shield plate 7 can be increased, the magnetic resistance at the contact surface can be reduced, and the shielding performance can be further improved.
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Abstract
Description
先ず、図1及び図2を参照して、第1の実施形態に係る半導体装置の構成について説明する。図1は、第1の実施形態に係る半導体装置の概略的な平面図であり、図2(a)は、図1のI-I′切断断面図、図2(b)は、同じくII-II′切断断面図である。
次に、本実施形態に係る半導体装置の製造方法について説明する。図3、図5及び図8は、本実施形態に係る半導体記憶装置の製造方法を示すための概略的な平面図であり、図4(a)、図6(a)及び図9(a)は、それらのI-I′切断断面図、図4(b)、図6(b)及び図9(b)は、同じくII-II′切断断面図である。また、図7は、同製造方法を示す断面図である。
次に、第2の実施形態に係る半導体装置の構成について説明する。図10は、第1の実施形態に係る半導体装置の概略的な平面図であり、図11(a)は、図10のI-I′切断断面図、図11(b)は、同じくII-II′切断断面図である。
次に、第3の実施形態に係る半導体装置の構成について説明する。図19は、第1の実施形態に係る半導体装置の概略的な平面図であり、図20(a)は、図19のI-I′切断断面図、図20(b)は、同じくII-II′切断断面図である。
上記各実施形態においては、側壁部32の上端が上部シールド板7に対して略垂直に形成されていた。しかしながら、例えば図28に示すように、側壁部32の上端を上部シールド板7に対して略平行な面をなすように形成することも可能である。このような構成は、下部シールド板3を形成する際、磁性体からなる板を折り曲げるだけで容易に実現可能である。このような構成によれば、下部シールド板3と上部シールド板7との接触面積を増加させて、接触面における磁気抵抗を低減し、よりシールド性を高めることが可能であると考えられる。
Claims (5)
- 第1のコンタクト部が形成された基板と、
前記基板上に前記第1のコンタクト部を避ける様に設けられた磁性体を用いた下部シールド板と、
前記下部シールド板上に設けられ前記第1のコンタクト部と電気的に接続される第2のコンタクト部を有する半導体チップと、
前記第1のコンタクト部と前記第2のコンタクト部とを電気的に接続する接続材と、
前記半導体チップ上に前記第2のコンタクト部及び前記接続材を避ける様に設けられた磁性体を用いた上部シールド板と
を備え、
前記下部シールド板及び前記上部シールド板の少なくとも一方のシールド板は、端部が他方のシールド板に向けて折り曲げられ、その先端が他方のシールド板に接続される側壁部を有する
ことを特徴とする半導体装置。 - 前記側壁部は、前記半導体チップの前記接続材が配置されていない側に対向している
ことを特徴とする請求項1記載の半導体装置。 - 第1のコンタクト部が形成された基板上に、前記第1のコンタクト部を避けるように磁性体を用いた下部シールド板を設け、
前記下部シールド板上に、前記第1のコンタクト部と電気的に接続される第2のコンタクト部を有する半導体チップを、前記第1のコンタクト部と前記第2のコンタクト部とが対応するように配置し、
前記第1のコンタクト部と前記第2のコンタクト部とを接続材によって電気的に接続し、
前記半導体チップ上に、所定の厚みを有する可塑性の絶縁層が裏面に形成された磁性体を用いた上部シールド板を、前記第2のコンタクト部及び前記接続材を避けるように前記裏面から前記半導体チップに押圧し、前記下部シールド板及び前記上部シールド板の少なくとも一方のシールド板から他方のシールド板に延びる側壁部を介して前記下部シールド板と前記上部シールド板とを接触させる
ことを特徴とする半導体装置の製造方法。 - 前記下部シールド板及び前記上部シールド板は、前記側壁部を2つ有する
ことを特徴とする請求項3記載の半導体装置の製造方法。 - 前記下部シールド板は、前記側壁部を有する
ことを特徴とする請求項3又は4記載の半導体装置の製造方法。
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US14/916,864 US9978690B2 (en) | 2013-09-04 | 2013-09-04 | Semiconductor apparatus and manufacturing method for same |
CN201380079333.1A CN105518850B (zh) | 2013-09-04 | 2013-09-04 | 半导体装置及其制造方法 |
PCT/JP2013/073755 WO2015033396A1 (ja) | 2013-09-04 | 2013-09-04 | 半導体装置及びその製造方法 |
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Cited By (3)
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JP2017092181A (ja) * | 2015-11-06 | 2017-05-25 | 株式会社東芝 | 半導体装置 |
JP2017183398A (ja) * | 2016-03-29 | 2017-10-05 | 東芝メモリ株式会社 | 半導体装置及びその製造方法 |
JP2019103232A (ja) * | 2017-12-01 | 2019-06-24 | 矢崎総業株式会社 | 電子部品ユニット |
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KR102354370B1 (ko) * | 2015-04-29 | 2022-01-21 | 삼성전자주식회사 | 쉴딩 구조물을 포함하는 자기 저항 칩 패키지 |
US10892230B2 (en) | 2018-07-30 | 2021-01-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Magnetic shielding material with insulator-coated ferromagnetic particles |
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JP2009141194A (ja) * | 2007-12-07 | 2009-06-25 | Dainippon Printing Co Ltd | 半導体装置用のメタルシールド板、メタルシールド用シート、半導体装置、メタルシールド用シートの製造方法、およびメタルシールド板の製造方法 |
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JP2019103232A (ja) * | 2017-12-01 | 2019-06-24 | 矢崎総業株式会社 | 電子部品ユニット |
Also Published As
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JPWO2015033396A1 (ja) | 2017-03-02 |
JP6235598B2 (ja) | 2017-11-22 |
CN105518850A (zh) | 2016-04-20 |
US9978690B2 (en) | 2018-05-22 |
US20160197045A1 (en) | 2016-07-07 |
CN105518850B (zh) | 2018-05-11 |
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