JP2006294795A - 半導体装置およびその製造方法 - Google Patents
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Abstract
【解決手段】 本実施形態の半導体装置は、ベッドフレーム1(支持基板)の上面にシリコンスペーサ2を間に挟んで2個のベアチップ3,4を配置し、ベッドフレーム1の下面にもシリコンスペーサ2を間に挟んで2個のベアチップ3,4を配置している。ベッドフレーム1を挟んで水平方向両側にはインナーリード5が配置され、インナーリード5とベアチップ3,4のパッドとはボンディングワイヤ6,7で接続されている。シリコンスペーサ2の一端側のベアチップ3のパッドをインナーリード5に接続するボンディングワイヤ7が、同じシリコンスペーサ2の他端側のベアチップ3に接触しないように、ボンディングワイヤ7の高さを制限している。
【選択図】 図1
Description
上述した第1の実施形態では、ベアチップ3の対向する2辺に沿ってパッドが配置されている例を説明したが、図11に示すように一辺に沿ってのみパッド21が配置されたベアチップ3も存在する。本発明は、このようなベアチップ3に対しても適用可能である。
2 シリコンスペーサ
3,4 ベアチップ
5 インナーリード
6,7 ボンディングワイヤ
8 接着材
Claims (6)
- 支持基板の対向する第1および第2の主面の少なくとも一方の主面上に積層される複数のベアチップと、
前記複数のベアチップのうち、上下に隣接配置される2つの前記ベアチップの間に配置されるスペーサと、
前記支持基板を挟んで水平方向両側に配置され、前記ベアチップのパッドにボンディングワイヤを介して接続されるインナーリードと、を備え、
前記スペーサの一端側の前記ベアチップのパッドを対応する前記インナーリードに接続する前記ボンディングワイヤは、同じスペーサの他端側の前記ベアチップに接触しないように配置されることを特徴とする半導体装置。 - 前記スペーサの一端側の前記ベアチップに該スペーサを接合する接着材の厚みと、該スペーサの厚みとの和は、前記ボンディングワイヤのワイヤ径の2〜4倍であることを特徴とする請求項1に記載の半導体装置。
- 前記第1および第2の主面上にそれぞれ複数個ずつ前記ベアチップが積層され、
前記ボンディングワイヤは、前記インナーリードの対向する2面にそれぞれ接続され、
前記インナーリード上の前記ボンディングワイヤの接続位置は、前記インナーリードの対向する2面において水平方向に互いにずれていることを特徴とする請求項1または2に記載の半導体装置。 - 前記スペーサは、シリコンスペーサであり、
前記ベアチップは、フラッシュメモリチップであることを特徴とする請求項1乃至3のいずれかに記載の半導体装置。 - 第1のインナーリードと、
前記第1のインナーリードに対して水平方向に間隔を隔てて配置され、前記第1のインナーリードよりもリード部が長い第2のインナーリードと、
前記第2のインナーリード上にスペーサを間に挟んで積層され一辺に沿って形成されたパッドをそれぞれ有する複数のベアチップと、
前記第1のインナーリードと前記複数のベアチップのパッドとの間、および前記第2のインナーリードと前記複数のベアチップのベアチップとの間を接続する複数のボンディングワイヤと、を備え、
前記スペーサの一端側の前記ベアチップのパッドを対応する前記第1または第2のインナーリードに接続する前記ボンディングワイヤは、同じスペーサの他端側の前記ベアチップに接触しないように配置されることを特徴とする半導体装置。 - 支持基板の第1の主面に接着材を介して第1のベアチップを実装するステップと、
前記第1のベアチップの表面に接着材を介して第1のスペーサを貼り付けるステップと、
前記第1のベアチップのパッドとインナーリードとをボンディングワイヤで接続し、該ボンディングワイヤの最大高さが前記第1のスペーサの上端よりも低くなるように前記ボンディングワイヤを配置するステップと、
前記第1のスペーサの表面に接着材を介して第2のベアチップを貼り付けるステップと、
前記第2のベアチップのパッドと前記インナーリードとをボンディングワイヤで接続するステップと、
前記ステップのいずれかの処理と並行して、あるいは前記ステップのすべての終了後に、前記支持基板の第2の主面に接着材を介して第3のベアチップを貼り付けるステップと、
前記第3のベアチップの表面に接着材を介して第3のスペーサを貼り付けるステップと、
前記第3のベアチップのパッドとインナーリードとをボンディングワイヤで接続し、該ボンディングワイヤの最大高さが前記第3のスペーサの上端よりも低くなるように前記ボンディングワイヤを配置するステップと、
前記第3のスペーサの表面に接着材を介して第4のベアチップを貼り付けるステップと、
前記第4のベアチップのパッドと前記インナーリードとをボンディングワイヤで接続するステップと、を備えることを特徴とする半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005112142A JP4643341B2 (ja) | 2005-04-08 | 2005-04-08 | 半導体装置 |
US11/398,694 US7569921B2 (en) | 2005-04-08 | 2006-04-06 | Semiconductor device and manufacturing method thereof |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2008251873A (ja) * | 2007-03-30 | 2008-10-16 | Oki Electric Ind Co Ltd | 半導体装置及び半導体装置製造方法 |
JP2008300663A (ja) * | 2007-05-31 | 2008-12-11 | Oki Electric Ind Co Ltd | リードフレーム、このリードフレームを用いる半導体装置及びその製造方法 |
JP2014179514A (ja) * | 2013-03-15 | 2014-09-25 | Toshiba Corp | 半導体装置 |
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JP2007035864A (ja) * | 2005-07-26 | 2007-02-08 | Toshiba Corp | 半導体パッケージ |
JP2007035865A (ja) * | 2005-07-26 | 2007-02-08 | Toshiba Corp | 半導体パッケージとその製造方法 |
JP5604897B2 (ja) * | 2010-02-18 | 2014-10-15 | セイコーエプソン株式会社 | 光デバイスの製造方法、光デバイス及び生体情報検出器 |
DE102010022925B4 (de) * | 2010-06-07 | 2019-03-07 | Tdk Electronics Ag | Piezoelektrisches Vielschichtbauelement und Verfahren zur Ausbildung einer Außenelektrode bei einem piezoelektrischen Vielschichtbauelement |
US11469163B2 (en) * | 2019-08-02 | 2022-10-11 | Semiconductor Components Industries, Llc | Low stress asymmetric dual side module |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04302164A (ja) * | 1991-03-29 | 1992-10-26 | Fujitsu Ltd | 半導体装置 |
JP2000058743A (ja) * | 1998-07-31 | 2000-02-25 | Sanyo Electric Co Ltd | 半導体装置 |
JP2001298150A (ja) * | 2000-04-14 | 2001-10-26 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2002261233A (ja) * | 2001-03-05 | 2002-09-13 | Sony Corp | 半導体装置及びその製造方法 |
JP2003347504A (ja) * | 2003-05-12 | 2003-12-05 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2004282056A (ja) * | 2003-02-27 | 2004-10-07 | Sumitomo Bakelite Co Ltd | 半導体装置、半導体素子の製造方法、および半導体装置の製造方法 |
JP2004303841A (ja) * | 2003-03-28 | 2004-10-28 | Lintec Corp | 半導体装置、半導体装置の製造方法およびスペーサ |
JP2004356529A (ja) * | 2003-05-30 | 2004-12-16 | Renesas Technology Corp | 半導体装置および半導体装置の製造方法 |
JP2005026695A (ja) * | 2003-07-01 | 2005-01-27 | Samsung Electronics Co Ltd | インライン集積回路チップパッケージ製造装置及びそれを利用した集積回路チップパッケージの製造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0951011A (ja) | 1995-08-10 | 1997-02-18 | Tanaka Denshi Kogyo Kk | 半導体チップのワイヤボンディング方法 |
DE10142120A1 (de) * | 2001-08-30 | 2003-03-27 | Infineon Technologies Ag | Elektronisches Bauteil mit wenigstens zwei gestapelten Halbleiterchips sowie Verfahren zu seiner Herstellung |
KR20030075860A (ko) * | 2002-03-21 | 2003-09-26 | 삼성전자주식회사 | 반도체 칩 적층 구조 및 적층 방법 |
JP2004172477A (ja) * | 2002-11-21 | 2004-06-17 | Kaijo Corp | ワイヤループ形状、そのワイヤループ形状を備えた半導体装置、ワイヤボンディング方法及び半導体製造装置 |
JP2004296897A (ja) * | 2003-03-27 | 2004-10-21 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器および半導体装置の製造方法 |
US7030489B2 (en) * | 2003-07-31 | 2006-04-18 | Samsung Electronics Co., Ltd. | Multi-chip module having bonding wires and method of fabricating the same |
-
2005
- 2005-04-08 JP JP2005112142A patent/JP4643341B2/ja not_active Expired - Fee Related
-
2006
- 2006-04-06 US US11/398,694 patent/US7569921B2/en not_active Expired - Fee Related
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04302164A (ja) * | 1991-03-29 | 1992-10-26 | Fujitsu Ltd | 半導体装置 |
JP2000058743A (ja) * | 1998-07-31 | 2000-02-25 | Sanyo Electric Co Ltd | 半導体装置 |
JP2001298150A (ja) * | 2000-04-14 | 2001-10-26 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2002261233A (ja) * | 2001-03-05 | 2002-09-13 | Sony Corp | 半導体装置及びその製造方法 |
JP2004282056A (ja) * | 2003-02-27 | 2004-10-07 | Sumitomo Bakelite Co Ltd | 半導体装置、半導体素子の製造方法、および半導体装置の製造方法 |
JP2004303841A (ja) * | 2003-03-28 | 2004-10-28 | Lintec Corp | 半導体装置、半導体装置の製造方法およびスペーサ |
JP2003347504A (ja) * | 2003-05-12 | 2003-12-05 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2004356529A (ja) * | 2003-05-30 | 2004-12-16 | Renesas Technology Corp | 半導体装置および半導体装置の製造方法 |
JP2005026695A (ja) * | 2003-07-01 | 2005-01-27 | Samsung Electronics Co Ltd | インライン集積回路チップパッケージ製造装置及びそれを利用した集積回路チップパッケージの製造方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008251873A (ja) * | 2007-03-30 | 2008-10-16 | Oki Electric Ind Co Ltd | 半導体装置及び半導体装置製造方法 |
JP4579941B2 (ja) * | 2007-03-30 | 2010-11-10 | Okiセミコンダクタ株式会社 | 半導体装置及び半導体装置製造方法 |
JP2008300663A (ja) * | 2007-05-31 | 2008-12-11 | Oki Electric Ind Co Ltd | リードフレーム、このリードフレームを用いる半導体装置及びその製造方法 |
US7705469B2 (en) | 2007-05-31 | 2010-04-27 | Oki Semiconductor Co., Ltd. | Lead frame, semiconductor device using same and manufacturing method thereof |
JP2014179514A (ja) * | 2013-03-15 | 2014-09-25 | Toshiba Corp | 半導体装置 |
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JP4643341B2 (ja) | 2011-03-02 |
US20060232288A1 (en) | 2006-10-19 |
US7569921B2 (en) | 2009-08-04 |
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