TWI775970B - 包含多晶片堆疊的半導體封裝及其製造方法 - Google Patents

包含多晶片堆疊的半導體封裝及其製造方法 Download PDF

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TWI775970B
TWI775970B TW107137568A TW107137568A TWI775970B TW I775970 B TWI775970 B TW I775970B TW 107137568 A TW107137568 A TW 107137568A TW 107137568 A TW107137568 A TW 107137568A TW I775970 B TWI775970 B TW I775970B
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semiconductor
wafer
semiconductor wafer
die
elevated
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TW107137568A
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TW201933547A (zh
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成基俊
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南韓商愛思開海力士有限公司
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Abstract

提供了半導體封裝。所述半導體封裝包括：第一半導體晶片，其連接有第一高架柱狀凸塊；第二半導體晶片，其堆疊在該第一半導體晶片上以保留該第一高架柱狀凸塊露出，並且被配置為包括設置在該第二半導體晶片的中心區域上的第一晶片襯墊；第三半導體晶片，其偏移並堆疊在該第二半導體晶片上以保留該第一晶片襯墊露出；以及晶片支撐件，其支撐該第三半導體晶片的突出部。

Description

包含多晶片堆疊的半導體封裝及其製造方法
本公開涉及半導體封裝技術，更具體地講，涉及包含多晶片堆疊的半導體封裝及其製造方法。
Figure 107137568-A0202-12-0001-15
本申請主張2018年1月18日提交的韓國申請案第10-2018-0006508號的優先權，其整體通過引用併入本文。
最近，在各種電子系統中需要具有高密度和高性能的半導體封裝。另外，由於移動系統需要緊湊的半導體封裝，所以已開發出具有相對小的形狀因數的半導體封裝。作為用於實現高性能半導體封裝的封裝技術，覆晶堆疊技術可有吸引力。已提出一般覆晶堆疊技術以提供包括在基板上堆疊的一對晶片或一對晶片的雙晶片堆疊結構。因此，可能有必要開發一種封裝技術以用於增加嵌入在封裝中的半導體晶片的數量而不會增加封裝的厚度。
根據實施方式，提供了一種半導體封裝。該半導體封裝包括：第一半導體晶片，其連接有第一高架柱狀凸塊；以及第二半導體晶片，其堆疊 在第一半導體晶片上以保留第一高架柱狀凸塊露出，並且被配置為包括設置在第二半導體晶片的中心區域中的第一晶片襯墊。第二半導體晶片的中心區域與第二半導體晶片的邊緣區域間隔開。第三半導體晶片堆疊在第二半導體晶片上以相對於第二半導體晶片橫向偏移以保留第一晶片襯墊露出。第三半導體晶片包括比第二半導體晶片的側表面進一步橫向突出的突出部(overhang)。提供晶片支撐件以支撐第三半導體晶片的突出部。設置囊封層以囊封第一半導體晶片、第二半導體晶片和第三半導體晶片的堆疊結構。電路互連圖案設置在囊封層上並電連接到第一高架柱狀凸塊和第一晶片襯墊。
根據另一實施方式，提供了一種半導體封裝。該半導體封裝包括：第一半導體晶片，其連接有第一高架柱狀凸塊；第二半導體晶片，其堆疊在第一半導體晶片上以保留第一高架柱狀凸塊露出，並且被配置為包括第一晶片襯墊；囊封層，其囊封第一半導體晶片和第二半導體晶片的堆疊結構；開孔，其基本上穿透囊封層以暴露第一高架柱狀凸塊和第一晶片襯墊；以及電路互連圖案，其被配置為包括通孔部分和延伸部分。通孔部分通過開孔連接到第一高架柱狀凸塊和第一晶片襯墊，並且延伸部分從通孔部分延伸到囊封層上。
根據另一實施方式，提供了一種製造半導體封裝的方法。該方法包括以下步驟：提供連接有第一高架柱狀凸塊的第一半導體晶片並且將第二半導體晶片堆疊在第一半導體晶片上以保留第一高架柱狀凸塊露出。第二半導體晶片具有設置在第二半導體晶片的與第二半導體晶片的邊緣區域間隔開的中心區域中的第一晶片襯墊。將第三半導體晶片堆疊在第二半導體晶片上以相對於第二半導體晶片橫向偏移並保留第一晶片襯墊露出。形成囊封層以囊封第一半導體晶片、第二半導體晶片和第三半導體晶片的堆疊結構。在囊封層上形成電連接到第一高架柱狀凸塊和第一晶片襯墊的電路互連圖案。
10‧‧‧分立半導體封裝
100‧‧‧蓋晶圓
100D‧‧‧蓋晶粒
101‧‧‧第一表面
102‧‧‧第二表面
210‧‧‧第一黏合層
230‧‧‧第二黏合層
240‧‧‧第三黏合層
250‧‧‧第五黏合層
260‧‧‧第四黏合層
301‧‧‧第一半導體晶片
301C‧‧‧中心區域
301E‧‧‧第一邊緣區域
302‧‧‧第二半導體晶片
302E‧‧‧第二邊緣區域
308‧‧‧第四表面
309‧‧‧第三表面
310‧‧‧晶片主體
311‧‧‧第一半導體層
312‧‧‧第一層間絕緣層
313‧‧‧積體電路元件
314‧‧‧第一內部互連結構
330‧‧‧第一晶片襯墊
332‧‧‧第二晶片襯墊
350‧‧‧再分配互連線
351‧‧‧連接部分
370‧‧‧介電層
390‧‧‧第一高架柱狀凸塊
390S‧‧‧頂表面
392‧‧‧第二高架柱狀凸塊
392S‧‧‧頂表面
401‧‧‧第三半導體晶片
401C‧‧‧中心區域
402‧‧‧第四半導體晶片
402C‧‧‧中心區域
402L‧‧‧交疊部分
402P‧‧‧突出部
409‧‧‧第五表面
411‧‧‧第二半導體層
412‧‧‧第二層間絕緣層
413‧‧‧第二積體電路元件
414‧‧‧第二內部互連結構
430‧‧‧第三晶片襯墊
431‧‧‧第四晶片襯墊
453‧‧‧偏移距離
454‧‧‧偏移距離
500‧‧‧晶片支撐件
509‧‧‧頂表面
600‧‧‧光敏材料層
601‧‧‧第一開孔
602‧‧‧第二開孔
603‧‧‧第三開孔
604‧‧‧第四開孔
605‧‧‧開孔
606‧‧‧表面
609‧‧‧曝光區域
700‧‧‧光罩
710‧‧‧光阻擋區域
720‧‧‧光穿透區域
790‧‧‧曝光用光
791‧‧‧剩餘部分
800‧‧‧電路互連圖案
810‧‧‧通孔部分
830‧‧‧延伸部分
900‧‧‧外連接器
910‧‧‧介電層
7800‧‧‧記憶卡
7810‧‧‧記憶體
7820‧‧‧記憶體控制器
7830‧‧‧主機
8710‧‧‧電子系統
8711‧‧‧控制器
8712‧‧‧輸入/輸出裝置
8713‧‧‧記憶體
8714‧‧‧介面
8715‧‧‧匯流排
D‧‧‧曝光臨界深度
H1‧‧‧垂直長度/長度
H2‧‧‧厚度
H3‧‧‧垂直厚度/厚度
H4‧‧‧垂直長度/長度
H5‧‧‧垂直厚度
H6‧‧‧總高度
H7‧‧‧垂直厚度/厚度
圖1至圖9是示出根據實施方式的半導體封裝的製造方法的橫截面圖。
圖10是示出根據實施方式的半導體封裝的橫截面圖。
圖11是示出採用包括根據實施方式的半導體封裝的記憶卡的電子系統的方塊圖。
圖12是示出包括根據實施方式的半導體封裝的另一電子系統的方塊圖。
本文所使用的術語可對應於考慮其在實施方式中的功能而選擇的詞語，術語的含義可被解釋為根據實施方式所屬領域的通常技術人士而不同。如果詳細定義，則可根據定義來解釋術語。除非另外定義，否則本文所使用的術語(包括技術術語和科學術語)具有實施方式所屬領域的通常技術人士通常理解的相同含義。
將理解，儘管本文中可使用術語“第一”、“第二”、“第三”等來描述各種元件，但是這些元件不應受這些術語限制。這些術語僅用於將一個元件與另一元件相區分，而非用於僅限定元件本身或者意指特定順序。
還將理解，當元件或層被稱為在另一元件或層“上”、“上方”、“下面”、“下方”或“外側”時，該元件或層可與另一元件或層直接接觸，或者可存在中間元件或層。用於描述元件或層之間的關係的其它詞語應該以類似的方式解釋(例如，“在...之間”與“直接在...之間”或者“相鄰”與“直接相鄰”之間)。
諸如“在...之下”、“在...下面”、“下”、“上面”、“上”、“頂部”、“底部”等的空間相對術語可用於描述元件和/或特徵與另一元件和/或特徵的關 係(例如，如圖中所示)。將理解，除了附圖中所描繪的取向之外，空間相對術語旨在涵蓋裝置在使用和/或操作中的不同取向。例如，當附圖中的裝置翻轉時，被描述為在其它元件或特徵下面和/或之下的元件將被取向為在其它元件或特徵上面。裝置可按照其它方式取向(旋轉90度或處於其它取向)並且相應地解釋本文中所使用的空間相對描述符。
半導體封裝可包括諸如半導體晶片或半導體晶粒的電子裝置。半導體晶片或半導體晶粒可通過使用晶粒切割製程將諸如晶圓的半導體基板分離成多片來獲得。半導體晶片可對應於記憶體晶片、邏輯晶片(包括特定應用積體電路(ASIC)晶片)或系統晶片(SoC)。記憶體晶片可包括整合在半導體基板上的動態隨機存取記憶體(DRAM)電路、靜態隨機存取記憶體(SRAM)電路、NAND型快閃記憶體電路、NOR型快閃記憶體電路、磁隨機存取記憶體(MRAM)電路、電阻式隨機存取記憶體(ReRAM)電路、鐵電隨機存取記憶體(FeRAM)電路或相變隨機存取記憶體(PcRAM)電路。邏輯晶片可包括整合在半導體基板上的邏輯電路。半導體封裝可用在諸如行動電話的通訊系統、與生物技術或保健關聯的電子系統或可穿戴電子系統中。
貫穿說明書，相同的標號表示相同的元件。即使標號未參照一幅圖提及或描述，該標號也可參照另一幅圖提及或描述。另外，即使標號未在一幅圖中示出，其也可參照另一幅圖提及或描述。
圖1是示出在蓋晶圓100上的第一半導體晶片301以及相對於第一半導體晶片301偏移堆疊的第二半導體晶片302的橫截面圖。圖2是示出第一半導體晶片301的橫截面圖。在本說明書中，術語“第一半導體晶片”、“第二半導體晶片”、“第三半導體晶片”、“第四半導體晶片”等僅用於將一個半導體晶片與另一半導體晶片相區分，而非用於意指特定順序。
參照圖1，蓋晶圓100可以是沒有任何積體電路的虛擬晶圓。用 作蓋晶圓100的虛擬晶圓可以是矽晶圓。用作蓋晶圓100的虛擬晶圓可以是半導體晶圓、金屬晶圓或介電晶圓。蓋晶圓100可充當支撐在蓋晶圓100上堆疊的第一半導體晶片301和第二半導體晶片302的基礎構件。蓋晶圓100的一部分可用作保護半導體封裝中的第一半導體晶片301和第二半導體晶片302的保護構件。
第一半導體晶片301可使用第一黏合層210附接到蓋晶圓100的第一表面101。蓋晶圓100可具有與第一半導體晶片301相反的第二表面102和第一表面101。第一黏合層210可將第一半導體晶片301的第三表面309結合到蓋晶圓100的第一表面101。
第一半導體晶片301可包括提供第三表面309的晶片主體310。晶片主體310還可提供與蓋晶圓100相反的第四表面308。第一晶片襯墊330可在晶片主體310的第四表面308處暴露。參照圖2，晶片主體310可包括第一積體電路元件313。第一積體電路元件313可被整合在第一半導體層311中或第一半導體層311上。第一半導體層311可以是矽層。第一層間絕緣層312可設置在第一半導體層311上以覆蓋第一積體電路元件313，並且第一內部互連結構314可被設置在第一層間絕緣層312中。第一層間絕緣層312可包括垂直堆疊的多個介電層，並且可提供晶片主體310的第四表面308。第一內部互連結構314可將第一晶片襯墊330電連接到設置在晶片主體310中的第一積體電路元件313。
第一晶片襯墊330可對應於位於晶片主體310的中心區域301C的表面上的中心襯墊。中心區域301C可以是與晶片主體310的第一邊緣區域301E間隔開的區域。第一半導體晶片301可包括從位於中心區域301C中的第一晶片襯墊330朝著第一邊緣區域301E延伸的再分配互連線350。第一高架柱狀凸塊390可被設置在多個第一邊緣區域301E中的一個上並與該第一邊緣區域301E連接。各個再分配互連線350可包括連接部分351，並且第一高架柱狀凸塊390可設置在再分配互連線350的連接部分351上。第一高架柱狀凸塊390可電連接到 再分配互連線350的連接部分351。介電層370可形成在晶片主體310的第四表面308上以覆蓋再分配互連線350。介電層370可形成為空出並暴露再分配互連線350的連接部分351。第一高架柱狀凸塊390可連接到通過介電層370暴露的連接部分351。
參照圖1和圖2，第一高架柱狀凸塊390可充當具有垂直長度H1的連接構件。第一高架柱狀凸塊390的長度H1可對應於從晶片主體310向上突出的第一高架柱狀凸塊390的高度。第一高架柱狀凸塊390可被設置為顯著提高再分配互連線350的連接部分351的位置。第一高架柱狀凸塊390可由金屬材料(例如，銅材料)形成。第一高架柱狀凸塊390可形成為具有大約幾十微米至大約一百幾十微米的長度H1。第一高架柱狀凸塊390的長度H1可基本上等於第一半導體晶片301的厚度H2。第一高架柱狀凸塊390的長度H1可大於第一半導體晶片301的厚度H2。第一半導體晶片301的厚度H2可對應於第一半導體晶片301的第三表面309與介電層370的與第一層間絕緣層312相反的表面之間的距離。
再參照圖1，第二半導體晶片302可堆疊在第一半導體晶片301上以通過第一半導體晶片301橫向偏移。第二半導體晶片302可使用第二黏合層230附接到第一半導體晶片301。第二半導體晶片302可以是具有與第一半導體晶片301基本上相同的配置的半導體晶片。例如，第二半導體晶片302可包括與中心襯墊對應的第二晶片襯墊332以及設置在第二半導體晶片302的第二邊緣區域302E上的第二高架柱狀凸塊392。
第二半導體晶片302可相對於第一半導體晶片301橫向偏移以保留第一半導體晶片301的第一邊緣區域301E露出。因此，第一半導體晶片301和第二半導體晶片302可在蓋晶圓100上垂直堆疊以提供臺階結構。第二半導體晶片302可被設置為使得第二邊緣區域302E與第一半導體晶片301的第一邊緣區域 301E相鄰。因此，第二高架柱狀凸塊392可與第一高架柱狀凸塊390相鄰。
第二半導體晶片302的側表面可被設置為在橫向方向上面向第一高架柱狀凸塊390。第一高架柱狀凸塊390可與第二半導體晶片302橫向間隔開特定距離。第一高架柱狀凸塊390的長度H1可大於第二半導體晶片302的垂直厚度H3。因此，第一高架柱狀凸塊390的頂表面390S可位於比第二半導體晶片302的頂表面高的水準處。更具體地講，第一高架柱狀凸塊390的頂表面390S可位於比第二晶片襯墊332高的水準處。第二晶片襯墊332可被設置在第二半導體晶片302的中心區域中。
第二高架柱狀凸塊392可形成為具有與第一高架柱狀凸塊390基本上相同的形狀。例如，第二高架柱狀凸塊392的垂直長度H4可基本上等於第一高架柱狀凸塊390的長度H1。第二高架柱狀凸塊392的長度H4可大於第二半導體晶片302的厚度H3。第二高架柱狀凸塊392的長度H4可大於第一半導體晶片301的厚度H2。
在一些實施方式中，第二高架柱狀凸塊392的長度H4可小於第一高架柱狀凸塊390的長度H1。
圖3是示出堆疊在第二半導體晶片302上並相對於第二半導體晶片302橫向偏移的第三半導體晶片401的橫截面圖。圖4是示出第三半導體晶片401的橫截面圖。
參照圖3，第三半導體晶片401可相對於第二半導體晶片302橫向偏移。第三半導體晶片401可使用第三黏合層240附接到第二半導體晶片302。第三半導體晶片401可相對於第二半導體晶片302橫向偏移以保留第二半導體晶片302的第二邊緣區域302E露出。第二半導體晶片302和第三半導體晶片401可垂直堆疊在第一半導體晶片301上以提供臺階結構。因此，第三半導體晶片401可設置在第二半導體晶片302上，使得第二半導體晶片302的側表面可在橫向方 向上面向第二高架柱狀凸塊392。第二高架柱狀凸塊392的長度H4可大於第三半導體晶片401的垂直厚度H5。因此，第二高架柱狀凸塊392的頂表面392S可位於比第三半導體晶片401的與第二半導體晶片302相反的第五表面409高的水準處。在一些實施方式中，第二高架柱狀凸塊392可從第二半導體晶片302向上突出以具有基本上等於第三半導體晶片401的厚度的垂直長度H4。
參照圖3和圖4，與第一半導體晶片301和第二半導體晶片302不同，第三半導體晶片401可未配置有任何高架柱狀凸塊。第三半導體晶片401可包括在與第三半導體晶片401的頂表面對應的第五表面409上保持暴露的第三晶片襯墊430。第三半導體晶片401可包括第二積體電路元件413。第二積體電路元件413可被整合在第二半導體層411中或第二半導體層411上。第二半導體層411可以是矽層。第二層間絕緣層412可設置在第二半導體層411上以覆蓋第二積體電路元件413，並且第二內部互連結構414可被設置在第二層間絕緣層412中。第二層間絕緣層412可包括垂直堆疊的多個介電層，並且可提供第五表面409。第二內部互連結構414可將第三晶片襯墊430電連接到設置在第三半導體晶片401中的第二積體電路元件413。
第二積體電路元件413可包括構成記憶體裝置的單元電晶體。第一積體電路元件(圖2的313)也可包括構成記憶體裝置的單元電晶體。第三半導體晶片401可以是記憶體晶片，並且第一半導體晶片301和第二半導體晶片302也可以是記憶體晶片。
第三晶片襯墊430可對應於位於第三半導體晶片401的中心區域401C中的中心襯墊。與第一半導體晶片301和第二半導體晶片302不同，第三半導體晶片401可被配置為不包括任何再分配互連線以及覆蓋再分配互連線的任何介電層。
再參照圖3，晶片支撐件500可設置在蓋晶圓100上以與第三半導 體晶片401間隔開。晶片支撐件500可使用第四黏合層260附接到蓋晶圓100的第一表面101。蓋晶圓100可支撐晶片支撐件500。晶片支撐件500可被設置為具有垂直厚度H7，該垂直厚度H7基本上等於第一半導體晶片301、第二半導體晶片302和第三半導體晶片401的總高度H6。例如，晶片支撐件500的厚度H7可對應於從第一半導體晶片301、第二半導體晶片302和第三半導體晶片401的總高度H6減去第四黏合層260的厚度後所餘的值。因此，晶片支撐件500的頂表面509可位於與第五表面409(對應於第三半導體晶片401的頂表面)基本上相同的水準。
圖5是示出堆疊在第三半導體晶片401上以橫向偏移的第四半導體晶片402的橫截面圖。
參照圖5，第四半導體晶片402可通過第三半導體晶片401堆疊以橫向偏移。第二半導體晶片302、第三半導體晶片401和第四半導體晶片402可依次堆疊在第一半導體晶片301上以在基本上相同的偏移方向上相對於第一半導體晶片301偏移。第四半導體晶片402相對於第三半導體晶片401的偏移距離454可大於第三半導體晶片401相對於第二半導體晶片302的偏移距離453。
第三晶片襯墊430所在的中心區域401C可保持未被第四半導體晶片402覆蓋。第三半導體晶片401的中心區域401C可與第三半導體晶片401的邊緣區域間隔開。第四半導體晶片402可偏移，使得第三半導體晶片401的第三晶片襯墊430保持暴露，並且第四半導體晶片402可與第三半導體晶片401部分地交疊。因此，第四半導體晶片402的一部分可橫向突出超過第三半導體晶片401的側表面以提供突出部402P。第四半導體晶片402的突出部402P的寬度可大於第四半導體晶片402的與第三半導體晶片401交疊的交疊部分402L的寬度。
晶片支撐件500可支撐第四半導體晶片402的突出部402P。晶片支撐件500可防止第四半導體晶片402的突出部402P向下翹曲。即，晶片支撐件 500可防止第四半導體晶片402的突出部402P的翹曲或變形，以防止在第四半導體晶片402中形成裂縫。第四半導體晶片402可使用第五黏合層250附接到第三半導體晶片401和晶片支撐件500二者。
晶片支撐件500可以是虛擬晶片。晶片支撐件500可被設置為具有與第四半導體晶片402相同的材料。例如，晶片支撐件500可以是矽晶粒。晶片支撐件500的寬度可為第四半導體晶片402的寬度的一半。另選地，晶片支撐件500的寬度可小於第四半導體晶片402的寬度的一半。
第四半導體晶片402可以是具有與第三半導體晶片401基本上相同的功能和形狀的半導體晶片。第四半導體晶片402可被設置為具有中心區域402C以及設置在中心區域402C上的第四晶片襯墊431。
圖6是示出囊封第一半導體晶片301、第二半導體晶片302、第三半導體晶片401和第四半導體晶片402的光敏材料層600的橫截面圖。
參照圖6，光敏材料層600可形成在蓋晶圓100的第一表面101上以覆蓋第一半導體晶片301、第二半導體晶片302、第三半導體晶片401和第四半導體晶片402。光敏材料層600可通過在蓋晶圓100的第一表面101上層壓光敏介電膜來形成。光敏材料層600可充當覆蓋、囊封並保護第一半導體晶片301、第二半導體晶片302、第三半導體晶片401和第四半導體晶片402的囊封層。
光敏材料層600可包括諸如光敏聚醯亞胺材料或光敏聚苯並噁唑材料的光敏聚合物材料。由於光敏材料層600包括光敏劑，所以光敏材料層600的溶解度可取決於施加於光敏材料層600的曝光製程。例如，曝露於諸如紫外(UV)線的光的光敏材料層600的溶解度可不同於未曝露於諸如紫外(UV)線的光的光敏材料層600的溶解度。
圖7是示出將光敏材料層600部分地曝光的步驟的橫截面圖。
參照圖7，可使用光刻設備將光敏材料層600的一些部分選擇性 地曝露於光。具體地講，光罩700可被設置在光敏材料層600上方，並且曝光用光790可被照射到光罩700上。曝光用光790的一部分可被光罩700的光阻擋區域710阻擋，並且曝光用光790的剩餘部分791可穿過光罩700的光穿透區域720以到達光敏材料層600的預定部分。因此，曝光用光790可改變光敏材料層600的預定部分的化學性質，並且可改變光敏材料層600的預定部分的溶解度。
曝光用光790可滲入到光敏材料層600中以形成光敏材料層600的曝光區域609。曝光區域609可對應於對齊以與第一高架柱狀凸塊390和第二高架柱狀凸塊392以及第三晶片襯墊430和第四晶片襯墊431交疊的區域。曝光用光790能夠有效地傳播到光敏材料層600中的曝光臨界深度D可被限制為特定深度。曝光臨界深度D指示通過曝光用光790正常曝光的光敏材料層600的有效深度。即，足夠強烈以對光敏材料層600正常曝光的曝光用光790可能未達到光敏材料層600的低於曝光臨界深度D的部分。因此，曝光區域609不應形成為比曝光臨界深度D深。
在本公開中，第一高架柱狀凸塊390和第二高架柱狀凸塊392可形成為使得第一高架柱狀凸塊390和第二高架柱狀凸塊392的頂表面位於曝光臨界深度D的範圍內。因此，曝光區域609可形成為接觸第一高架柱狀凸塊390和第二高架柱狀凸塊392的頂表面。
圖8是示出在光敏材料層600中形成開孔605的步驟的橫截面圖。
參照圖8，可通過對光敏材料層600進行顯影來選擇性地去除曝光區域(圖7的609)。結果，可形成基本上穿透光敏材料層600的開孔605。可使用單個曝光步驟和單個顯影步驟來形成開孔605。開孔605可包括第一至第四開孔601、602、603和604。第一開孔601可與第一高架柱狀凸塊390對齊並且可形成為暴露第一高架柱狀凸塊390的頂表面。第二開孔602可與第二高架柱狀凸塊392對齊並且可形成為暴露第二高架柱狀凸塊392的頂表面。第三開孔603可 與第三晶片襯墊430對齊並且可形成為暴露第三晶片襯墊430的頂表面。第四開孔604可與第四晶片襯墊431對齊並且可形成為暴露第四晶片襯墊431的頂表面。即使開孔605形成在不同的位置處並且形成為具有不同的深度，也可使用包括單個曝光步驟和單個顯影步驟的單個光刻步驟來同時形成所有開孔605。
參照圖7和圖8，第一半導體晶片301和第二半導體晶片302可位於曝光臨界深度D的範圍之外。因此，可能難以形成直接延伸到第一半導體晶片301和第二半導體晶片302的表面的曝光區域609。即，可能難以形成直接暴露第一半導體晶片301和第二半導體晶片302的表面的第一開孔601和第二開孔602。由於第一高架柱狀凸塊390和第二高架柱狀凸塊392向上延伸以使得第一高架柱狀凸塊390和第二高架柱狀凸塊392的頂表面位於曝光臨界深度D的範圍內，所以可通過第一開孔601和第二開孔602直接暴露第一高架柱狀凸塊390和第二高架柱狀凸塊392的至少頂表面。因此，第一高架柱狀凸塊390和第二高架柱狀凸塊392可充當將第一半導體晶片301和第二半導體晶片302連接到第一開孔601和第二開孔602的連接器。
第四晶片襯墊431可與第三晶片襯墊430間隔開偏移距離(圖5的454)。因此，第四開孔604也可與第三開孔603間隔開偏移距離(圖5的454)。第三晶片襯墊430可與第二高架柱狀凸塊392間隔開第三半導體晶片401的寬度的至少一半。因此，第三開孔603也可與第二開孔602間隔開第三半導體晶片401的寬度的至少一半。因此，由於第二開孔602、第三開孔603和第四開孔604彼此間隔開相對長的距離，所以可防止第二開孔602、第三開孔603和第四開孔604彼此連接。
圖9是示出形成電路互連圖案800的步驟的橫截面圖。
參照圖9，可在光敏材料層600上形成電路互連圖案800。各個電路互連圖案800可形成為包括填充多個開孔605中的任一個的通孔部分810以及 從通孔部分810延伸到光敏材料層600的表面606上的延伸部分830。電路互連圖案800的通孔部分810可分別直接接觸第一高架柱狀凸塊390和第二高架柱狀凸塊392以及第三晶片襯墊430和第四晶片襯墊431。電路互連圖案800的通孔部分810可分別直接連接到第一高架柱狀凸塊390和第二高架柱狀凸塊392以及第三晶片襯墊430和第四晶片襯墊431。電路互連圖案800的通孔部分810可通過開孔605直接地分別連接到第一高架柱狀凸塊390和第二高架柱狀凸塊392以及第三晶片襯墊430和第四晶片襯墊431。
由於第一開孔601可延伸得比第三半導體晶片401的下部更深，所以填充第一開孔601的通孔部分810的垂直長度可大於第三半導體晶片401的厚度。由於第三開孔603可形成為比第四半導體晶片402的下部更深，所以填充第三開孔603的通孔部分810的垂直長度可大於第四半導體晶片402的厚度。相比之下，由於第四開孔604形成為比第四半導體晶片402的厚度淺，所以填充第四開孔604的通孔部分810的垂直長度可小於第四半導體晶片402的厚度。
可在光敏材料層600的表面606上形成介電層910以保留電路互連圖案800的延伸部分830的部分露出。可在電路互連圖案800的延伸部分830的保持露出的部分上形成外連接器900。外連接器900可由凸塊或焊球形成。在這種情況下，一些延伸部分830可形成為延伸到光敏材料層600的邊緣區域上以不與第一至第四半導體晶片301、302、401和402交疊。因此，一些外連接器900可形成為不與第一至第四半導體晶片301、302、401和402交疊。
可使用分割製程(例如，劃片製程)來切割形成有外連接器900的蓋晶圓100以提供多個分立半導體封裝10，其中之一示出於圖10中。在執行分割製程之前，可對蓋晶圓100的第二表面102應用凹陷製程以減小蓋晶圓100的厚度。
參照圖10，分立半導體封裝10可包括堆疊在通過切割蓋晶圓100 而製造的多個蓋晶粒100D中的任一個上的第一至第四半導體晶片301、302、401和402。蓋晶粒100D可以是矽晶粒。晶片支撐件500可由蓋晶粒100D支撐。第一高架柱狀凸塊390可被設置在第一半導體晶片301的第一邊緣區域301E上，並且第二高架柱狀凸塊392可被設置在第二半導體晶片302的第二邊緣區域302E上。第四半導體晶片402的突出部402P可由晶片支撐件500支撐。
第一至第四半導體晶片301、302、401和402的堆疊堆疊可被光敏材料層600覆蓋和囊封。可使用包括單個曝光步驟和單個顯影步驟的單個光刻步驟來形成開孔605以基本上穿透光敏材料層600。可利用通孔部分810填充開孔605，並且通孔部分810可延伸到光敏材料層600上以提供延伸部分830。通孔部分810和延伸部分830可構成電路互連圖案800。電路互連圖案800可被設置在充當囊封層的光敏材料層600上並且可電連接到第一高架柱狀凸塊390和第二高架柱狀凸塊392以及第三晶片襯墊430和第四晶片襯墊431。可在電路互連圖案800上設置介電層910以保留電路互連圖案800的部分露出，並且外連接器900可附接並連接到電路互連圖案800的露出的部分。
圖11是示出包括採用根據實施方式的半導體封裝的記憶卡7800的電子系統的方塊圖。記憶卡7800包括諸如非揮發性記憶體裝置的記憶體7810以及記憶體控制器7820。記憶體7810和記憶體控制器7820可存儲資料或者讀出所存儲的資料。記憶體7810和記憶體控制器7820中的至少一個可包括根據實施方式的半導體封裝。
記憶體7810可包括應用了本公開的實施方式的技術的非揮發性記憶體裝置。記憶體控制器7820可控制記憶體7810，使得回應於來自主機7830的讀/寫請求，讀出所存儲的資料或者存儲資料。
圖12是示出包括根據實施方式的半導體封裝的電子系統8710的方塊圖。電子系統8710可包括控制器8711、輸入/輸出裝置8712和記憶體8713。 控制器8711、輸入/輸出裝置8712和記憶體8713可通過提供資料移動的路徑的匯流排8715彼此聯接。
在實施方式中，控制器8711可包括一個或更多個微處理器、數位訊號處理器、微控制器和/或能夠執行與這些元件相同的功能的邏輯裝置。控制器8711或記憶體8713可包括根據本公開的實施方式的多個半導體封裝中的一個或更多個。輸入/輸出裝置8712可包括選自鍵區、鍵盤、顯示裝置、觸控式螢幕等中的至少一個。記憶體8713是用於存儲資料的裝置。記憶體8713可存儲要由控制器8711執行的資料和/或命令等。
記憶體8713可包括諸如DRAM的揮發性記憶體裝置和/或諸如快閃記憶體的非揮發性記憶體裝置。例如，快閃記憶體可被安裝到諸如移動終端或臺式電腦的資訊處理系統。快閃記憶體可構成固態磁碟(SSD)。在這種情況下，電子系統8710可在快閃記憶體系統中穩定地存儲大量資料。
電子系統8710還可包括被配置為向通訊網路發送資料以及從通訊網路接收資料的介面8714。介面8714可為有線或無線型。例如，介面8714可包括天線或者有線或無線收發器。
電子系統8710可被實現為移動系統、個人電腦、工業電腦或者執行各種功能的邏輯系統。例如，移動系統可以是個人數位助理(PDA)、可攜式電腦、平板電腦、行動電話、智慧型電話、無線電話、膝上型電腦、記憶卡、數位音樂系統和資訊發送/接收系統中的任一個。
如果電子系統8710是能夠執行無線通訊的設備，則電子系統8710可用在使用諸如碼分多重存取(code division multiple access，CDMA)、全球行動通訊系統(global system for mobile communications，GSM)、北美數位行動電話(north American digital cellular，NADC)、增強時分多重存取(enhanced-time division multiple access，E-TDMA)、寬頻碼分多重存取 (wideband code division multiple access，WCDAM)、CDMA2000、長期演進(long term evolution，LTE)或無線寬頻網際網路(wireless broadband Internet，Wibro)的技術的通訊系統中。
出於例示性目的公開了本公開的實施方式。本領域技術人士將理解，在不脫離本公開和所附申請專利範圍的範疇和精神的情況下，可進行各種修改、添加和替換。
100‧‧‧蓋晶圓
101‧‧‧第一表面
102‧‧‧第二表面
210‧‧‧第一黏合層
230‧‧‧第二黏合層
301‧‧‧第一半導體晶片
301E‧‧‧第一邊緣區域
302‧‧‧第二半導體晶片
302E‧‧‧第二邊緣區域
308‧‧‧第四表面
309‧‧‧第三表面
310‧‧‧晶片主體
330‧‧‧第一晶片襯墊
332‧‧‧第二晶片襯墊
350‧‧‧再分配互連線
351‧‧‧連接部分
370‧‧‧介電層
390‧‧‧第一高架柱狀凸塊
390S‧‧‧頂表面
392‧‧‧第二高架柱狀凸塊
H1‧‧‧垂直長度/長度
H2‧‧‧厚度
H3‧‧‧垂直厚度/厚度
H4‧‧‧垂直長度/長度

Claims (31)

  1. 一種半導體封裝，該半導體封裝包括：第一半導體晶片，第一高架柱狀凸塊連接到該第一半導體晶片；第二半導體晶片，該第二半導體晶片堆疊在所述第一半導體晶片上以保留所述第一高架柱狀凸塊露出，並且被配置為包括設置在所述第二半導體晶片的中心區域中的第一晶片襯墊，其中，所述第二半導體晶片的所述中心區域與所述第二半導體晶片的邊緣區域間隔開；第三半導體晶片，該第三半導體晶片堆疊在所述第二半導體晶片上以相對於所述第二半導體晶片橫向偏移以保留所述第一晶片襯墊露出，並且被配置為包括比所述第二半導體晶片的側表面進一步橫向突出的突出部；晶片支撐件，該晶片支撐件支撐所述第三半導體晶片的所述突出部；囊封層，該囊封層囊封所述第一半導體晶片、所述第二半導體晶片和所述第三半導體晶片的堆疊結構；以及電路互連圖案，所述電路互連圖案被設置在所述囊封層上並且電連接到所述第一高架柱狀凸塊和所述第一晶片襯墊。
  2. 根據請求項1所述的半導體封裝，其中，所述囊封層包括分別暴露所述第一高架柱狀凸塊和所述第一晶片襯墊的開孔，並且其中，各個所述電路互連圖案填充所述開孔中的任一個並且延伸到所述囊封層上。
  3. 根據請求項1所述的半導體封裝，其中，所述囊封層包括光敏材料層。
  4. 根據請求項1所述的半導體封裝，其中，所述第一高架柱狀凸塊連接到所述第一半導體晶片的邊緣區域。
  5. 根據請求項4所述的半導體封裝，其中，所述第一半導體晶片包括：第二晶片襯墊，該第二晶片襯墊被設置在所述第一半導體晶片的中心區域中，其中，所述第一半導體晶片的所述中心區域與所述第一半導體晶片的邊緣區域間隔開；以及再分配互連線，該再分配互連線從所述第二晶片襯墊延伸以接觸所述第一高架柱狀凸塊。
  6. 根據請求項1所述的半導體封裝，其中，所述第一高架柱狀凸塊從所述第一半導體晶片向上突出以具有基本上等於所述第二半導體晶片的厚度的垂直長度。
  7. 根據請求項1所述的半導體封裝，其中，所述第一高架柱狀凸塊從所述第一半導體晶片向上突出以具有大於所述第二半導體晶片的厚度的垂直長度。
  8. 根據請求項1所述的半導體封裝，其中，所述第二半導體晶片堆疊在所述第一半導體晶片上以提供臺階結構。
  9. 根據請求項1所述的半導體封裝，該半導體封裝還包括堆疊在所述第一半導體晶片的與所述第二半導體晶片相反的底表面上的第四半導體晶片，其中，第二高架柱狀凸塊連接到所述第四半導體晶片，並且其中，所述第一半導體晶片偏移堆疊在所述第四半導體晶片上以保留所述第二高架柱狀凸塊露出。
  10. 根據請求項9所述的半導體封裝，該半導體封裝還包括支撐所述第四半導體晶片的蓋晶粒。
  11. 根據請求項10所述的半導體封裝，其中，所述晶片支撐件由所 述蓋晶粒支撐。
  12. 根據請求項11所述的半導體封裝，其中，所述晶片支撐件被設置在所述蓋晶粒上以具有基本上等於所述第四半導體晶片、所述第一半導體晶片和所述第二半導體晶片的總高度的高度。
  13. 根據請求項12所述的半導體封裝，其中，所述晶片支撐件是矽晶粒。
  14. 根據請求項9所述的半導體封裝，其中，所述第三半導體晶片相對於所述第二半導體晶片的偏移距離大於所述第一半導體晶片相對於所述第四半導體晶片的偏移距離。
  15. 根據請求項9所述的半導體封裝，其中，所述第一半導體晶片、所述第二半導體晶片、所述第三半導體晶片和所述第四半導體晶片在基本上相同的偏移方向上偏移堆疊。
  16. 根據請求項9所述的半導體封裝，其中，所述第一半導體晶片和所述第四半導體晶片具有基本上相同的形狀，並且其中，所述第二半導體晶片和所述第三半導體晶片具有基本上相同的形狀。
  17. 一種半導體封裝，該半導體封裝包括：第一半導體晶片，第一高架柱狀凸塊連接到該第一半導體晶片；第二半導體晶片，該第二半導體晶片堆疊在所述第一半導體晶片上以保留所述第一高架柱狀凸塊露出，並且被配置為包括第一晶片襯墊；囊封層，該囊封層囊封所述第一半導體晶片和所述第二半導體晶片的堆疊結構；開孔，所述開孔基本上穿透所述囊封層以暴露所述第一高架柱狀凸塊和所 述第一晶片襯墊；以及電路互連圖案，所述電路互連圖案被配置為包括通過所述開孔連接到所述第一高架柱狀凸塊和所述第一晶片襯墊的通孔部分以及從所述通孔部分延伸到所述囊封層上的延伸部分，其中所述第一高架柱狀凸塊從所述第一半導體晶片向上突出，以具有實質上等於或大於所述第二半導體晶片的厚度之垂直長度。
  18. 根據請求項17所述的半導體封裝，其中，所述通孔部分分別直接接觸所述第一高架柱狀凸塊和所述第一晶片襯墊。
  19. 根據請求項17所述的半導體封裝，其中，所述第一晶片襯墊被設置在所述第二半導體晶片的與所述第二半導體晶片的邊緣區域間隔開的中心區域中。
  20. 根據請求項19所述的半導體封裝，該半導體封裝還包括偏移堆疊在所述第二半導體晶片上以保留所述第一晶片襯墊露出的第三半導體晶片，其中，所述第三半導體晶片具有從所述第二半導體晶片的側表面橫向突出的突出部。
  21. 根據請求項20所述的半導體封裝，其中，連接到所述第一晶片襯墊的所述通孔部分具有大於所述第三半導體晶片的厚度的垂直長度。
  22. 根據請求項17所述的半導體封裝，該半導體封裝還包括堆疊在所述第一半導體晶片的與所述第二半導體晶片相反的底表面上的第四半導體晶片，其中，第二高架柱狀凸塊連接到所述第四半導體晶片，並且其中，所述第一半導體晶片偏移堆疊在所述第四半導體晶片上以保留所述第二高架柱狀凸塊露出。
  23. 根據請求項22所述的半導體封裝， 其中，所述電路互連圖案還包括連接到所述第二高架柱狀凸塊的附加通孔部分，並且其中，所述附加通孔部分具有大於所述第二半導體晶片的厚度的垂直長度。
  24. 一種製造半導體封裝的方法，該方法包括以下步驟：提供連接有第一高架柱狀凸塊的第一半導體晶片；將第二半導體晶片堆疊在所述第一半導體晶片上以保留所述第一高架柱狀凸塊露出，其中，所述第二半導體晶片具有設置在所述第二半導體晶片的與所述第二半導體晶片的邊緣區域間隔開的中心區域中的第一晶片襯墊；將第三半導體晶片堆疊在所述第二半導體晶片上以相對於所述第二半導體晶片橫向偏移並保留所述第一晶片襯墊露出；利用囊封層囊封所述第一半導體晶片、所述第二半導體晶片和所述第三半導體晶片的堆疊結構；以及在所述囊封層上形成電連接到所述第一高架柱狀凸塊和所述第一晶片襯墊的電路互連圖案。
  25. 根據請求項24所述的方法，其中，所述囊封層被形成為包括光敏材料層，其中，形成所述電路互連圖案的步驟包括以下步驟：在所述光敏材料層中形成開孔，其中，所述開孔分別暴露所述第一高架柱狀凸塊和所述第一晶片襯墊；以及形成填充所述開孔並延伸到所述光敏材料層上的所述電路互連圖案，並且其中，通過對所述光敏材料層進行曝光和顯影來同時形成所述開孔。
  26. 根據請求項24所述的方法，該方法還包括以下步驟：設置堆疊在所述第一半導體晶片的與所述第二半導體晶片相反的底表面上的第四半導體 晶片，其中，第二高架柱狀凸塊連接到所述第四半導體晶片，並且其中，所述第一半導體晶片偏移堆疊在所述第四半導體晶片上以保留所述第二高架柱狀凸塊露出。
  27. 根據請求項26所述的方法，其中，所述第四半導體晶片被設置在蓋晶圓上，並且該方法還包括以下步驟：在所述蓋晶圓上設置晶片支撐件以與所述第四半導體晶片、所述第一半導體晶片和所述第二半導體晶片間隔開，其中，所述晶片支撐件支撐所述第三半導體晶片的從所述第二半導體晶片的側表面突出的突出部，並且其中，所述晶片支撐件被設置在所述蓋晶圓上以具有基本上等於所述第四半導體晶片、所述第一半導體晶片和所述第二半導體晶片的總高度的高度。
  28. 根據請求項27所述的方法，其中，通過在所述蓋晶圓上層壓光敏介電層來形成所述囊封層。
  29. 根據請求項25所述的方法，其中，所述電路互連圖案被形成為包括：通過所述開孔連接到所述第一高架柱狀凸塊和所述第一晶片襯墊的通孔部分；以及從所述通孔部分延伸到所述囊封層上的延伸部分。
  30. 根據請求項29所述的方法，其中，所述通孔部分被形成為分別直接接觸所述第一高架柱狀凸塊和所述第一晶片襯墊。
  31. 根據請求項24所述的方法，該方法還包括以下步驟：設置用於支撐所述第三半導體晶片的從所述第二半導體晶片的側表面突出的突出部的晶片支撐件。
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