TW201131705A - Conductor package structure and method of the same - Google Patents

Conductor package structure and method of the same Download PDF

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Publication number
TW201131705A
TW201131705A TW099138891A TW99138891A TW201131705A TW 201131705 A TW201131705 A TW 201131705A TW 099138891 A TW099138891 A TW 099138891A TW 99138891 A TW99138891 A TW 99138891A TW 201131705 A TW201131705 A TW 201131705A
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Taiwan
Prior art keywords
conductor
package structure
substrate
electronic component
layer
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TW099138891A
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Chinese (zh)
Inventor
Diann-Fang Lin
Yu-Shan Hu
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Advanced Chip Eng Tech Inc
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Priority claimed from US12/716,539 external-priority patent/US20110031594A1/en
Application filed by Advanced Chip Eng Tech Inc filed Critical Advanced Chip Eng Tech Inc
Publication of TW201131705A publication Critical patent/TW201131705A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
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    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/92—Specific sequence of method steps
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    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The present invention provides a conductor package structure comprises a conductive base. An adhesive layer is formed on the conductive base. An electronic element is formed on the adhesive layer. Conductors are forming signal connection between the surface of a filling material and the bottom of the filling material, wherein the filling material is filled in the space between the electronic element and the conductors.

Description

201131705 六、發明說明： 【發明所屬之技術領域】 本發明係關於封袭結構，特丨·^曰士 導體封裝結構。 制係一種具有訊號通道之 【先前技術】 丰導體元件的領域中，元件密度持續地提昇以及元件 = 低。也因此對於如此高密度之封裝技術及内 連線技術也提升以適用上述之狀態。傳統之覆晶結構中， #錫球陣列形成於晶粒矣， 莫制 ^ 透“傳統之錫膏藉由錫球罩 傳輸、電源分配、保f =含散熱、訊號 小尺需：勝剛性封裝技術無法滿足高密度 再者，半導體元件需要保護以避免水 裝的技術。在這些技術中，=二 曰曰片別封裝於一彈性或陶究封裴 保護晶粒並且散開由元件產生的熱。因 昇。 的纟其疋對於讀的功率及效能的提 曰位由日㈣裝技術必須先將晶圓上之晶粒分割為個別 分別封裳’因此上述技術之製程十分費時。 為日日粒封裝技術與積體電路之發 ' M i# m ^ 双匁在切關聯，因此封 Ϊ技術對於電子70件之尺寸要求越來越高。基於上述之理 ’現今之封褒技術已逐漸趨向採用球閘陣列封裝 3 201131705 (隐)、覆晶球間陣列封裳、晶片 之技術。射㈣「㈣級料（机:級封裝 裝及交互連接結構，如 各阳0上所有封 晶粒之前進行。χ王步驟，係於切割為個別 程之後，出目士在完成所有配裝製程或封裝襲 裝分=上述晶圓級封裝具有極小之尺封 的圓級封裝技術係為高級封201131705 VI. Description of the Invention: [Technical Field to Be Invented by the Invention] The present invention relates to a sealed structure, a special conductor package structure. A system with a signal path [Prior Art] In the field of abundance of conductor elements, component density continues to increase and component = low. Therefore, such high-density packaging technology and interconnection technology are also upgraded to the above state. In the traditional flip-chip structure, the #tin ball array is formed in the grain 矣, and the traditional solder paste is transferred by the solder ball cover, the power distribution, the f = heat dissipation, and the signal size: wins the rigid package. Technology can't meet high-density, semiconductor components need to be protected from water-filling technology. In these technologies, the two-chip is packaged in an elastic or ceramic package to protect the die and dissipate the heat generated by the component. Because of the increase in power and performance of the reader, the technology of the Japanese (four) loading technology must first divide the die on the wafer into individual seals. Therefore, the process of the above technology is very time consuming. The packaging technology and the integrated circuit 'M i# m ^ double-twisting are related, so the sealing technology has higher and higher requirements for the size of the 70-piece electronic. Based on the above-mentioned theory, the current sealing technology has gradually adopted Ball Gate Array Package 3 201131705 (Hidden), Over-Crystal Array Array, Wafer Technology. Shot (4) "(4) Grade Materials (machine: grade package and interactive connection structure, such as before all the die on each yang 0) χ王Steps, Department Circular scale packaging line after the cutting of individual programs, the completion of all persons head fitting process or partial encapsulation passage means having a wafer level package = feet above seal closure for senior pinpoint

圓上加以製造及測試，且接著夢^、曰曰拉係於晶 目：=。因晶圓級封裝技術利用整個晶圓作為 二，用單一晶片或晶粒’因此於進行 2 二二，m皆已完成。此外，晶圓級封裝 打線接合、晶粒黏著及底部填充之程序；It is made and tested on the circle, and then the dream ^, the pull is tied to the crystal: =. Since the wafer-level packaging technology utilizes the entire wafer as the second, using a single wafer or die, so the implementation of 2 22, m has been completed. In addition, wafer level package bonding, die attach and underfill procedures;

It利用晶圓級封裝技術’可減少成 封裝之最後結構尺寸可相當於晶粒大小，故此技 術可滿足電子裝置之微型化需求。 雖晶圓級封裝技術具有上述優點’然而仍存在一些影 響^級封裝技術之接受度之問題。例如’雖利用晶圓級 …支術可減少積體電路與互連基板間之熱膨脹係數 (CTE)不匹配，然而#元件尺寸縮小，晶圓級封裝結構之 材料間之熱膨脹係數差異變為另一造成結構之機械不穩定 之關鍵因素。再者，形成於半導體晶粒上之數個接合墊係 透過包含重分佈層（RDL)之重分佈製程予以重分佈進入數 個區域陣列形式之金屬墊。一般而言，所有經堆疊之重分 佈層係形成於晶粒上之增層上。增層將增加封裒大小。封 201131705 裝厚度因此增加。其可能與縮小晶片尺寸之需求相牴觸。 是以，本發明提出一種導體封裝結構，降低封裝厚度， 克服上述封裝問題以及提供較佳板級熱循環可靠度測試。 【發明内容】 又“ D ° 本發明提供一種導體封裝結構，包含一基板；一黏著 層，形成於基板之上；至少-電子元件，形成於黏著層之 上；複數個導體，形成於-填充材料之表面與底部之間以 訊號連接，其中填充材料係填入於複數個導體之間的空間 籲及圍繞電子元件；以及-重分佈層，形成於電子元件之Y， 並連接電子元件與複數個導體之間。 其中基板可形成至少一開口於其中，或是將其圖形化 為-可供電性連接之線路結構，其中基板形成於導體之 門f體的底與基板的底部共平面。複數個導體包含至 ^同度。黏著層包含導電材料。填充材料鄰接電子元件 及基板之側並覆蓋電子元件之主動表面，及/或暴露導 體之上表面與底表面。導體封裝結構更包含—導電層形成 於電子7G件與黏著層之間’及/或形成於導體及基板之下； 更包含-介電層形成於重分佈層之τ;更包含一保護層形 成於”電層之上，t包含m層形成於保護層之上。導 體的底部具有凹形部分形成於其中。 在實她例中，本發明之導體封農結構更包含一電磁 :擾遮蔽層形成於導體封裝結構之底邊及/或側邊。在另一 =中’本發明之導體封裝結構更包含一天線結構形成 於導體封裝結構之底邊上。 201131705 此外，本發明提供一種形成導體封裝結構之方法。首 先，此方法包含提供一製具具有對準標記形成於其上。然 後，-薄膜層形成於製具之上。之後，晶粒之焊墊對心 對準標記。晶粒黏附於薄膜層之上。接下來，第—黏著層 形成於晶粒之背面。然後，提供一平板基底具有預製的^ 粒接收穿孔及複數個開口穿過該平板基底，其中晶粒接: 穿孔係用於接收晶粒。平板基底黏附至晶粒的背面。之後， 一封裝材料填入晶粒接收穿孔及複數個開口。移除薄膜 層。接著，平板基底黏附至一載體使得晶粒之主動區域朝 ^ ’其中平板基底包含基板及導體。第二黏著層形成於保 護層之上。最後，利用一雷射標誌製程於第二黏著層之上 以形成一標誌層。 曰 上述方法更包含形成一導電層於電子元件及黏著層之 間之步驟；更包含形成一導電材料於平板基底上以利於訊 號連接，更包含形成一重分佈層於電子元件及導體之上， •以連接電子元件之焊墊與導體之間；更包含形成一介電層 於平板基底、封裝材料及晶粒之上以暴露導體與焊墊；^ 包含形成一保護層以附蓋重分佈層及介電層以保護之；更 包含沿著切割線而切割平板基底以單一化及分離封裝為個 別單元。 【實施方式】 本發明將配合其較佳實施例與隨附之圖示詳述於下。 應可理解者為本發明中所有之較佳實施例僅為例示之用， 並非用以限制。因此除文中之較佳實施例外，本發明亦可It uses wafer-level packaging technology to reduce the final size of the package to the size of the die, so the technology can meet the miniaturization requirements of electronic devices. Although wafer level packaging technology has the above advantages, there are still some problems affecting the acceptance of the package technology. For example, 'the use of wafer level... can reduce the coefficient of thermal expansion (CTE) mismatch between the integrated circuit and the interconnect substrate. However, the size of the component is reduced, and the difference in thermal expansion coefficient between the materials of the wafer-level package structure becomes another. A key factor contributing to the mechanical instability of the structure. Furthermore, the plurality of bond pads formed on the semiconductor die are redistributed into the metal pads in the form of arrays of regions by a redistribution process comprising a redistribution layer (RDL). In general, all of the stacked heavy distribution layers are formed on the buildup layer on the die. Adding layers will increase the size of the package. Seal 201131705 installed thickness is therefore increased. It may be inconsistent with the need to shrink the size of the wafer. Therefore, the present invention proposes a conductor package structure, which reduces the package thickness, overcomes the above package problems, and provides a better board level thermal cycle reliability test. [Digital] The present invention provides a conductor package structure comprising a substrate; an adhesive layer formed on the substrate; at least - an electronic component formed on the adhesive layer; and a plurality of conductors formed in the -fill The surface of the material is connected to the bottom by a signal, wherein the filling material is filled in a space between the plurality of conductors to surround the electronic component; and the redistribution layer is formed in the Y of the electronic component, and the electronic component is connected to the plurality Between the conductors, wherein the substrate can form at least one opening therein, or can be patterned into a power supply connection circuit structure, wherein the bottom of the substrate formed on the gate of the conductor is coplanar with the bottom of the substrate. The conductors comprise the same degree. The adhesive layer comprises a conductive material. The filling material abuts the side of the electronic component and the substrate and covers the active surface of the electronic component, and/or exposes the upper surface and the bottom surface of the conductor. The conductor package structure further comprises - conductive The layer is formed between the electron 7G member and the adhesive layer and/or formed under the conductor and the substrate; further comprises a dielectric layer formed on the redistribution layer τ Further, a protective layer is formed on the "electric layer, and t includes an m layer formed on the protective layer. The bottom of the conductor has a concave portion formed therein. In the example, the conductor sealing structure of the present invention further comprises an electromagnetic shielding layer formed on the bottom edge and/or the side of the conductor packaging structure. In another = the conductor package structure of the present invention further comprises an antenna structure formed on the bottom side of the conductor package structure. In addition, the present invention provides a method of forming a conductor package structure. First, the method includes providing a tool with an alignment mark formed thereon. Then, a film layer is formed on the tool. After that, the pad of the die is aligned with the mark. The die adheres to the film layer. Next, a first adhesive layer is formed on the back side of the crystal grains. Then, a flat substrate is provided having pre-formed receiving perforations and a plurality of openings through the flat substrate, wherein the die attach: the perforations are used to receive the die. The flat substrate is adhered to the back side of the die. Thereafter, a package material fills the die receiving vias and a plurality of openings. Remove the film layer. Next, the flat substrate is adhered to a carrier such that the active area of the die faces the substrate where the substrate and the conductor are included. A second adhesive layer is formed over the protective layer. Finally, a laser marking process is used over the second adhesive layer to form a marking layer. The method further includes the steps of forming a conductive layer between the electronic component and the adhesive layer; further comprising forming a conductive material on the flat substrate to facilitate signal connection, and further comprising forming a redistribution layer on the electronic component and the conductor, The method further comprises: forming a dielectric layer on the flat substrate, the encapsulation material and the die to expose the conductor and the pad; and comprising forming a protective layer to cover the redistribution layer; The dielectric layer is protected; further comprising cutting the flat substrate along the cutting line to singulate and separate the package into individual units. [Embodiment] The present invention will be described in detail with reference to the preferred embodiments thereof and the accompanying drawings. It should be understood that all of the preferred embodiments of the present invention are intended to be illustrative only and not limiting. Therefore, in addition to the preferred embodiment of the text, the present invention may also

C 201131705 廣泛地應用在其他實施例中。且本發明並不受限於任何實 施例’應以隨附之申請專利範圍及其同等領域而定。 本發明揭露一種導體封裝結構，利用一基板具有—預 定的晶粒接收穿孔及複數個開口穿過基板。訊號通道形成 於電子元件與介層導體（via connectors)之上，致使連接 電子件與介層導體。一標誌層形成於訊號通道之上。 第一圖顯示根據本發明第一實施例之基礎導體封裝結 構之截面圖。如第一圖所示，導體封裝結構包含一基底具 籲有預疋的晶粒接收穿孔及複數個開口穿過基板，其中晶粒 接收穿孔係用於接收一晶粒1G2，其具有晶粒焊塾1〇5形 成於其上。在一實施例中，基底包含基板1〇〇及導體， 其中基板100形成於導體104之間’導體1〇4的底部及基 板100的底部共平面。基底的材料包含合金或金屬。合金 包含合金 42(42%Ni-58%Fe)或 K〇var(29%NM7%Co_54 %Fe)。較佳的是，晶粒1〇2是一電子元件。基板}⑻的材 •料包括合金或金屬。複數個開口係形成以從基板1〇〇的上 表面至下表面而穿過基板1〇〇。黏著層（材料）1〇1形成於基 板〇之上以黏著晶粒102。舉例而言，黏著層1 〇 1包含 導電材料以利於導電。導體刚形成於-填充材料103的 表面之間並穿過填充材料1G3，其中導體⑽包含至少一 材料以利於訊號連接(電性溝通)。填充材料103填入電子 兀件102與導體104之間的空間（複數個開口）。填充材料 m鄰接電子元件1()2及基板⑽之側壁，並覆蓋電子元 件⑽之主動表面。舉例而言，填充材_ 103圍繞基板 201131705 100、電子元件1〇2及導體104。 第一圖顯示為根據本發明之一實施例之具有重分佈層 之朝下導體封裝結構之截面圖。如第二圖所示，朝下導體 封裝結構包含一基底，包含基板200及導體204，其中基 板200形成於導體204之間，導體204的底部及基板2〇〇 的底部共平面，複數個導體包含至少一高度。黏著層（材 料）201形成於基板2〇〇之下以黏著晶粒2〇2。較佳的是， 晶粒202是一電子元件，電子元件包含一晶粒、_晶片及 •一晶片大小封裝或一封裝元件。舉例而言，黏著層2〇ι包 含導電材料。導體204形成於一填充材料2〇3的表面之間 並穿過填充材料203，其中導體2〇4包含至少一材料以利 於訊號連接（電性溝通）。填充材料2〇3填入電子元件 與導體204之間的空間。填充材料2〇3鄰接電子元件 及基板200之側壁，並覆蓋電子元件2〇2之主動表面。舉 例而吕’填充材料203圍繞基板2〇〇、電子元件202及導 籲體204。接觸墊（訊號通道）2〇8配置（位）於導體2〇4的下表 面，並連接至導體204。一介電（緩衝）層211形成於電子元 件202及填充材料203之上，以及訊號通道2〇7之下，以 暴露導體204及電子元件202之焊墊205。在一實施例中， 介電層211包含彈性材料、感光材料。訊號通道2〇7，例 如重分佈層，係形成於電子元件202及導體204之上（表 面），以利於連接電子元件202之焊墊205及介層導體2〇4。 一導電層206形成於電子元件202與黏著層2〇1之間以利 於導電。一保護層210形成於填充材料2〇3之下以保護及 201131705 覆蓋填充材料203、基板200、導體204及訊號通道208 以暴露訊號通道208。焊接凸塊/球209形成於訊號通道208 之下以訊號連接。另一保護層212形成於訊號通道207之 上（表面）以保護及覆蓋介電（緩衝）層211及訊號通道207。 在一實施例中’保護層210、212之材料包含矽氧烷聚合物 (SINR)、；ε夕橡膠，保護層21〇可以利用鑄模或膠合法（塗佈 或網印）所形成。 在一實施例中’本發明之具有重分佈層之導體封裝結 ®構更包含一電磁干擾（EMI)遮蔽層形成於該導體封裝結構 之底邊及/或側邊。舉例而言，電磁干擾遮蔽層220、221 可以形成於保護層212之上及/或導體封裝結構之側邊，如 第二圖所示。電磁干擾遮蔽層220、221可以藉由導電材料 所形成’例如金屬。 第四圖顯示為根據本發明之一實施例之具有訊號通道 之另一朝下導體封裝結構之截面圖。如第四圖所示，朝下 φ導體封裝結構省略訊號通道2〇8。保護層21〇形成於填充 材料203之下以保護及覆蓋填充材料2〇3，以暴露導體2〇4 及基板200。焊接凸塊/球2〇9形成於導體2〇4之下以訊號 連接—第一四圖之大部分類似第二圖，省略其詳細說明。 在^實％例中’暴露的基板2〇〇可以提昇散熱的效果。在 實她例中，導體204的底部具有凹形部分204a形成於其 中以利於對準及接收焊接凸塊/球謝，致使焊接凸塊/球 可以準確地附著於導體綱之上。凹形部分204a可以 精由一微影製程及一蝕刻製程而形成。 201131705 在另一實施例中’本發明之具有重分佈層之導體封裝 結構更包含一天線結構形成於導體封裝結構之底邊上。舉 例而言，天線結構230可以形成於保護層212之上，如第 五圖所示。 第/、圖顯示為根據本發明之一實施例之具有訊號通道 之雙邊朝下導體封裝結構之截面圖。如第六圖所示，朝下 導體封裝結構省略訊號通道2〇8。保護層2丨〇形成於填充 材料203之下以保護及覆蓋填充材料2〇3，以暴露導體2〇4 鲁及基板200。保護層212形成於訊號通道207之上（表面） 以保濩及覆蓋介電（緩衝）層211及訊號通道2〇7以暴露訊 號通道207。焊接凸塊/球213形成於訊號通道2〇7之上以 利於訊號連接。第六圖之大部分類似第四圖，省略其詳細 說明。在本實施例中，暴露的基板2〇〇可以提昇散熱的效 果。 ' 第七圖顯示為根據本發明之一實施例之具有訊號通道 籲之堆豐導體封裝結構之戴面圖。如第七圖所示，其顯示一 堆疊導體封裝結構，其可以藉由上面導體封裝結構及下面 雙邊朝下導體封裝結構所構成。上面導體封裝結構之焊接 凸塊/球可以省略。下面雙邊朝下導體封裝結構之焊接凸塊 /球213可以形成於訊號通道207及導體304之間以利於訊 號連接。在本實施例中，上面導體封裝結構之部分類似第 四圖，包括基板300、黏著層301、電子元件302具有焊塾 305、填充材料303、導體304、導電層306、訊號通道3〇7、 保護層310、介電層311、保護層312及標誌層3 13。上面 201131705 導體封裝結構之敘述可以參考第二圖。標誌、層3U形成於 ' 2之上。在一實施例中，導體304之底部具有具 有V P刀304a形成於其中以利於對準及接收焊接凸塊/ ， 致使焊接凸塊/球213可以準確地附著於導體3〇4 之上凹形σ卩分3〇4a可以藉由一微影製程及一蝕刻製程而 形成。 第圖顯示為根據本發明之一實施例之具有訊號通道 之雙側堆疊導體封裝結構之截面圖。如第八圖所示，其顯 ；"、又側堆導體封裝結構，其可以藉由上部主動區域朝 上導體封震結構及下部主動區域朝下導體封裝結構所構 成。上部導體封裝結構及下部導體封裝結構可以為一相同 封裝結構，其中基板200及3〇〇、填充材料203及3〇3與 導^2〇4及304係沿著一連接區域35〇而彼此連接配置了 上部導體封裝結構之焊接凸塊/球可以省略。雙邊堆疊導體 封裝結構之焊接凸塊/球213可以連接至一外部電子元件 馨以利於訊號連接。在本實施例中，上部及下部導體封裝結 構之部分類似第三圖，其中上部導體封裝結構包括基= 300、黏著層3〇1、電子元件3〇2具有焊墊3〇5、填充材料 3〇3、導體304、導電層306、訊號通道307、介電層311 f保護層312,而其中下部導體封裝結構包括基板2〇〇、黏 著層201、電子元件202具有焊墊2〇5、填充材料2〇3、導 體204、導電層206、訊號通道2〇7、介電層2ιι、保護層 及焊接凸塊/球213。上部及下部導體封裝結構之敘^ 可以參考第二圖。 201131705 第九圖顯示為根據本發明之一實施例之具有訊號通道 之一朝上堆疊導體封裝結構之截面圖。如第九圖所示，其 顯示朝下導體封裝結構，其可由電子元件3〇2置於一下部 導體封裝結構之上所構成’例如置於保護層212之上。電 子元件302之晶粒焊電305透過焊線（wjre b〇ncJing)360， 電性連接下部導體封裝結構之訊號通道207。焊線360之 知位於保濩層212之暴露區域3 7 〇之上以連接訊號通道 207，焊線360之另一端位於晶粒焊電3〇5之上以電性連 接。在本實施例中，下部導體封裝結構之部分類似第四圖， 其中下部導體封裝結構包括基板200、黏著層20卜電子元 件。202具有焊墊2〇5、填充材料2〇3、導體2〇4、導電層 號通道207、介電層211及保護層212。下部導體封裝結 構之敘述可以參考第二圖。C 201131705 is widely used in other embodiments. The invention is not limited to any embodiment, which is to be construed as the scope of the appended claims and their equivalents. The present invention discloses a conductor package structure in which a substrate has a predetermined die receiving via and a plurality of openings through the substrate. The signal path is formed on the electronic component and the via connectors, thereby connecting the electronic component to the via conductor. A flag layer is formed over the signal path. The first figure shows a cross-sectional view of a base conductor package structure in accordance with a first embodiment of the present invention. As shown in the first figure, the conductor package structure comprises a substrate with a pre-twisted die receiving via and a plurality of openings through the substrate, wherein the die receiving via is for receiving a die 1G2 having a grain soldering塾1〇5 is formed thereon. In one embodiment, the substrate comprises a substrate 1 and a conductor, wherein the substrate 100 is formed between the conductors 104 at the bottom of the conductors 1 and 4 and at the bottom of the substrate 100. The material of the substrate comprises an alloy or a metal. The alloy contains alloy 42 (42% Ni-58% Fe) or K〇var (29% NM 7% Co_54% Fe). Preferably, the die 1 〇 2 is an electronic component. The material of the substrate} (8) includes an alloy or a metal. A plurality of openings are formed to pass through the substrate 1 from the upper surface to the lower surface of the substrate 1A. An adhesive layer (material) 1〇1 is formed on the substrate 以 to adhere the die 102. For example, the adhesive layer 1 〇 1 contains a conductive material to facilitate conduction. The conductor is formed between the surface of the filling material 103 and through the filling material 1G3, wherein the conductor (10) contains at least one material to facilitate signal connection (electrical communication). The filling material 103 fills the space (plurality of openings) between the electronic component 102 and the conductor 104. The filling material m abuts the side walls of the electronic component 1 () 2 and the substrate (10) and covers the active surface of the electronic component (10). For example, the filler _ 103 surrounds the substrate 201131705 100, the electronic component 1〇2, and the conductor 104. The first figure shows a cross-sectional view of a downward conductor package having a redistribution layer in accordance with an embodiment of the present invention. As shown in the second figure, the downward conductor package structure comprises a substrate comprising a substrate 200 and a conductor 204, wherein the substrate 200 is formed between the conductors 204, the bottom of the conductor 204 and the bottom of the substrate 2 are coplanar, and a plurality of conductors Contains at least one height. An adhesive layer (material) 201 is formed under the substrate 2 to adhere the crystal grains 2〇2. Preferably, the die 202 is an electronic component comprising a die, a wafer, and a chip size package or a package component. For example, the adhesive layer 2〇ι contains a conductive material. The conductor 204 is formed between the surface of a filling material 2〇3 and passes through the filling material 203, wherein the conductor 2〇4 contains at least one material to facilitate signal connection (electrical communication). The filling material 2〇3 fills the space between the electronic component and the conductor 204. The filling material 2〇3 abuts the side walls of the electronic component and the substrate 200 and covers the active surface of the electronic component 2〇2. For example, the filling material 203 surrounds the substrate 2, the electronic component 202, and the conductor 204. The contact pads (signal channels) 2〇8 are placed (positioned) on the lower surface of the conductor 2〇4 and connected to the conductor 204. A dielectric (buffer) layer 211 is formed over the electronic component 202 and the fill material 203, and under the signal path 2A7 to expose the conductor 204 and the pads 205 of the electronic component 202. In an embodiment, the dielectric layer 211 comprises an elastic material, a photosensitive material. Signal channels 2〇7, such as redistribution layers, are formed over electronic component 202 and conductor 204 (surface) to facilitate bonding of bond pads 205 and via conductors 2〇4 of electronic component 202. A conductive layer 206 is formed between the electronic component 202 and the adhesive layer 2〇1 to facilitate conduction. A protective layer 210 is formed under the filling material 2〇3 to protect and cover the filling material 203, the substrate 200, the conductor 204 and the signal channel 208 to expose the signal channel 208. Solder bumps/balls 209 are formed under signal path 208 for signal connection. Another protective layer 212 is formed on the surface (surface) of the signal channel 207 to protect and cover the dielectric (buffer) layer 211 and the signal channel 207. In one embodiment, the material of the protective layers 210, 212 comprises a siloxane polymer (SINR), an ε rubber, and the protective layer 21 〇 can be formed by molding or gelation (coating or screen printing). In one embodiment, the conductor package of the redistribution layer of the present invention further comprises an electromagnetic interference (EMI) shielding layer formed on the bottom and/or sides of the conductor package. For example, the EMI shielding layers 220, 221 can be formed over the protective layer 212 and/or on the sides of the conductor package structure, as shown in the second figure. The electromagnetic interference shielding layers 220, 221 may be formed of a conductive material such as a metal. The fourth figure shows a cross-sectional view of another downward conductor package having a signal path in accordance with an embodiment of the present invention. As shown in the fourth figure, the signal channel 2〇8 is omitted from the downward φ conductor package structure. A protective layer 21 is formed under the filling material 203 to protect and cover the filling material 2〇3 to expose the conductor 2〇4 and the substrate 200. The solder bumps/balls 2〇9 are formed under the conductors 2〇4 to be signal-connected—most of the first four figures are similar to the second one, and a detailed description thereof will be omitted. In the case of %, the exposed substrate 2 can enhance the heat dissipation effect. In the example, the bottom of the conductor 204 has a concave portion 204a formed therein to facilitate alignment and receipt of the solder bump/ball, so that the solder bump/ball can be accurately attached to the conductor. The concave portion 204a can be formed by a lithography process and an etching process. In another embodiment, the conductor package structure having a redistribution layer of the present invention further comprises an antenna structure formed on a bottom edge of the conductor package structure. For example, the antenna structure 230 can be formed over the protective layer 212 as shown in FIG. Figure / is a cross-sectional view of a bilateral downward conductor package having a signal path in accordance with an embodiment of the present invention. As shown in the sixth figure, the signal path 2 〇 8 is omitted for the downward conductor package structure. A protective layer 2 is formed under the filling material 203 to protect and cover the filling material 2〇3 to expose the conductor 2〇4 and the substrate 200. The protective layer 212 is formed on the surface (surface) of the signal channel 207 to protect and cover the dielectric (buffer) layer 211 and the signal channel 2〇7 to expose the signal channel 207. Solder bumps/balls 213 are formed over signal channels 2〇7 to facilitate signal connections. Most of the sixth drawing is similar to the fourth drawing, and a detailed description thereof is omitted. In this embodiment, the exposed substrate 2 〇〇 can enhance the effect of heat dissipation. The seventh figure shows a wear side view of a stacked conductor package structure having a signal path in accordance with an embodiment of the present invention. As shown in the seventh figure, it shows a stacked conductor package structure which can be formed by the upper conductor package structure and the lower bilaterally facing conductor package structure. The solder bump/ball of the upper conductor package structure can be omitted. A solder bump/ball 213 of the lower bilateral conductor package structure may be formed between the signal path 207 and the conductor 304 to facilitate signal connection. In this embodiment, a portion of the upper conductor package structure is similar to the fourth figure, including the substrate 300, the adhesive layer 301, the electronic component 302 having the solder 305, the filling material 303, the conductor 304, the conductive layer 306, the signal channel 3〇7, The protective layer 310, the dielectric layer 311, the protective layer 312, and the mark layer 3 13 . The description of the 201131705 conductor package structure can be referred to the second figure. The mark, layer 3U is formed above '2. In one embodiment, the bottom of the conductor 304 has a VP knife 304a formed therein to facilitate alignment and receipt of the solder bumps/, such that the solder bumps/balls 213 can be accurately attached to the concave σ above the conductors 3〇4. The 〇3〇4a can be formed by a lithography process and an etching process. The figure shows a cross-sectional view of a double-sided stacked conductor package structure having a signal path in accordance with an embodiment of the present invention. As shown in the eighth figure, the ", side-by-side conductor package structure can be constructed by the upper active region facing the upper conductor sealing structure and the lower active region facing the lower conductor package structure. The upper conductor package structure and the lower conductor package structure may be the same package structure, wherein the substrates 200 and 3, the filling materials 203 and 3〇3 and the wires 〇4 and 304 are connected to each other along a connection region 35〇. The solder bumps/balls configured with the upper conductor package structure may be omitted. The solder bumps/balls 213 of the double-sided stacked conductor package structure can be connected to an external electronic component to facilitate signal connection. In this embodiment, portions of the upper and lower conductor package structures are similar to the third diagram, wherein the upper conductor package structure includes a base = 300, an adhesive layer 3 〇 1, an electronic component 3 〇 2 has a pad 3 〇 5, and a filler material 3 〇3, conductor 304, conductive layer 306, signal channel 307, dielectric layer 311 f protective layer 312, and wherein the lower conductor package structure includes substrate 2, adhesive layer 201, electronic component 202 has pads 2 〇 5, padding Material 2〇3, conductor 204, conductive layer 206, signal channel 2〇7, dielectric layer 2 ιι, protective layer and solder bump/ball 213. The upper and lower conductor package structures can be referred to the second figure. 201131705 The ninth diagram shows a cross-sectional view of a stacked conductor package having one of the signal channels facing upwards in accordance with an embodiment of the present invention. As shown in the ninth figure, it shows a downward facing conductor package structure which can be formed by placing the electronic component 3〇2 over the lower conductor package structure, for example, on the protective layer 212. The die pad 305 of the electronic component 302 is electrically connected to the signal path 207 of the lower conductor package structure through a bonding wire (wjre b〇ncJing) 360. The wire 360 is located above the exposed area of the protective layer 212 to connect the signal path 207, and the other end of the wire 360 is placed above the die bond 3〇5 for electrical connection. In the present embodiment, a portion of the lower conductor package structure is similar to the fourth diagram, wherein the lower conductor package structure includes the substrate 200, the adhesive layer 20, and the electronic component. 202 has a pad 2〇5, a filling material 2〇3, a conductor 2〇4, a conductive layer channel 207, a dielectric layer 211, and a protective layer 212. The description of the lower conductor package structure can be referred to the second figure.

第十圖顯示為根據本發明之一實施例之個別的導體封 j結構之截面圖。黏著層4〇5形成於基板4〇&之上。至少 :電子元件404形成於黏著層4〇5之上。複數個導體4〇6d 接成真充材# 407的表面及其底部之間以利於訊號連 =、中填充材料術填入複數個導體條d之間的空間並 =1子元Γ404。黏著層（導電層）4G5之預定的厚度位於 4之背面上。基板4()6e形成於導體概d之 =侧之底部與基板條之底部共平面。介電層4ιι導 :如硬氧炫聚合物（峨)材料，形成於 充）材料407及晶粒404之上，了我（填 墊401。1轳、S、首41 , 以暴路導體406d及晶粒焊 、道12,例如重分佈（導電）層，係形成於電 12 201131705 子元件404及導體406d之上（表面）’從而連接電子元件404 之焊塾401與介層導體406d之間。保護層413形成以覆蓋 訊號通道412及介電層411以利於保護，黏著層414形成 於保護層413之上。導電層（材料）421形成於基板4〇6(；及 導體406d之下表面之上以焊接一外部物件。黏著層414 係藉由雷射標誌製程以形成一標誌層（表面）422。 值得注意的是，保護層（薄膜）的厚度較佳為約〇.丨微 米至0.3微米，反射率接近空氣反射率丨。保護層的材料 可以為Si〇2、Al2〇3或氟聚合物等。 連接導線係經由接觸穿孔而穿透基底，因此晶粒封裝 之厚度明顯地縮小。本發明之封裝比習知者更薄。再者， f底係於封裝之前預製。晶粒穿孔與接觸穿孔亦預先決 疋。因此，產能可以比以前得到提昇。 因此’本發明之優點包含：The tenth diagram shows a cross-sectional view of an individual conductor seal j structure in accordance with an embodiment of the present invention. An adhesive layer 4〇5 is formed on the substrate 4〇& At least: the electronic component 404 is formed over the adhesive layer 4〇5. A plurality of conductors 4〇6d are connected between the surface of the true filling material #407 and the bottom thereof to facilitate signal connection, and the medium filling material fills the space between the plurality of conductor strips d and =1 sub-element 404. The predetermined thickness of the adhesive layer (conductive layer) 4G5 is located on the back surface of 4. The substrate 4 () 6e is formed on the bottom of the side of the conductor d and is coplanar with the bottom of the substrate strip. Dielectric layer 4 ιι: such as hard oxygen polymer (峨) material, formed on the filling material 407 and the grain 404, I (padding 401. 1 轳, S, the first 41, to the cataract conductor 406d And a grain soldering, track 12, such as a redistributed (conductive) layer, is formed between the electric device 12 201131705 sub-element 404 and the conductor 406d (surface) to thereby connect the solder 401 of the electronic component 404 to the via conductor 406d The protective layer 413 is formed to cover the signal channel 412 and the dielectric layer 411 for protection, and the adhesive layer 414 is formed on the protective layer 413. The conductive layer (material) 421 is formed on the substrate 4〇6 (and the lower surface of the conductor 406d). The upper layer is soldered to an external object. The adhesive layer 414 is formed by a laser marking process to form a marking layer (surface) 422. It is noted that the thickness of the protective layer (film) is preferably about 〇. In micrometers, the reflectivity is close to the air reflectance 丨. The material of the protective layer may be Si〇2, Al2〇3 or fluoropolymer, etc. The connecting wires penetrate the substrate via the contact vias, so the thickness of the die package is significantly reduced. The package of the present invention is thinner than the conventional ones. ..., F sill in the package prior to contact with the perforated perforated preform die must also advance Cloth Thus, productivity can be enhanced than before and therefore 'the advantages of the present invention comprises:

j導體基底預設晶粒接收穿孔；而由於晶粒嵌入基底_ P因此得以產生超薄封裝；基板；藉由填人⑦橡勝作》 緩衝區域以吸收石夕晶粒及導體基底間的熱膨脹係數(CT: .3)不匹配所產生熱應力；由於應用簡單的製程使得封 產能得以提升（製作時間縮短）。封裝及板狀可靠度㈣ 會導致熱機械應力施加於球體。成本低廉且製卷 "“可以完全地自動，尤其於模組組裝中。易 夕晶片封襞（雙晶片封裳）。由 、 戒）由於無拉子汙染、製程簡易 凡王自動化，可以得到較高的良率。 對Ub領域技#者，本發明雖以較佳實例闊明如 13 201131705 【圖式簡單說明】 第一圖顯示根據本發明第一 構之截面圖。 上，然其並非用以限定本發明 精神與範圍内所作之修改與類 之申請專利範圍内，此範圍應 構，且應做最寬廣的詮釋。 之精神。在不脫離本發明之 似的配置，均應包含在下述 覆蓋所有類似修改與類似結 實施例之基礎導體封裝結 f ®顯不根據本發明之一實施例之具有重分佈層之 •朝下導體封裴結構之截面圖。 第三圖顯示為根據本發明之另一實施例之具有訊號通 k之朝下導體封裝結構之截面圖。 第四圖顯示為根據本發明之又一實施例之具有訊號通 道之朝下導體封裝結構之截面圖。 第五圖顯示為根據本發明之再一實施例之具有訊號通 道之朝下導體封裝結構之截面圖。 % 第/、圖顯示為根據本發明之一實施例之具有訊號通道 之又邊朝下導體封裝結構之截面圖。 第七圖顯示為根據本發明之一實施例之具有訊號通道 之堆疊導體封裝結構之截面圖。 第八圖顯示為根據本發明之一實施例之具有訊號通道 之雙側堆疊導體封裝結構之截面圖。 第九圖顯示為根據本發明之一實施例之具有訊號通道 之一朝上堆疊導體封裝結構之截面圖。 第十圖顯示為根據本發明之一實施例之個別的導體封 14 201131705 裝結構之截面圖。 【主要元件符號說明】 基板 100、200、300、406c 黏著層（材料）1〇1、201、301、405、414 電子元件 102、202、302、404 填充材料 103、203、303、407 導體 104、204、304、406d 凹形部分204a、304a 籲晶粒焊墊105、205、305、401 導電層 206、306、421 訊號通道 207、208、307、412 焊接凸塊/球209、213 保護層 210、310、312、413 介電（緩衝）層 211、212、311、411 電磁干擾遮蔽層220、221 天線結構230 •標誌層313、422 連接區域350 焊線360 暴露區域370j conductor substrate preset crystal grain receives perforation; and because the crystal grain is embedded in the substrate _P, an ultra-thin package can be produced; the substrate; by filling the 7 rubber to make a buffer region to absorb the thermal expansion between the stone and the conductor substrate The coefficient (CT: .3) does not match the thermal stress generated; the application capacity is improved due to the simple application process (the production time is shortened). Package and plate reliability (4) can cause thermo-mechanical stress to be applied to the sphere. Low cost and roll-making "" can be completely automatic, especially in module assembly. Yi Xi wafer sealing (double wafer sealing). By, ring) due to no-leaf pollution, simple process automation, can be obtained Higher yield. For Ub domain technology, the present invention is illustrated by a preferred example as 13 201131705 [Simplified illustration of the drawings] The first figure shows a cross-sectional view according to the first configuration of the present invention. To the extent that the scope of the invention is to be construed as limiting the scope of the invention, the scope of the invention should be construed as the broadest scope of the invention. A cross-sectional view of a downward conductor sealing structure having a redistribution layer according to an embodiment of the present invention, which covers all of the similar modified and similar junction embodiments, is shown. A cross-sectional view of a lower conductor package structure having a signal pass k according to another embodiment of the invention. The fourth figure shows a downward conductor package junction having a signal path according to still another embodiment of the present invention. Figure 5 is a cross-sectional view showing a downward conductor package having a signal path in accordance with still another embodiment of the present invention. % / / is shown as having a signal path in accordance with an embodiment of the present invention. FIG. 7 is a cross-sectional view showing a stacked conductor package structure having a signal path according to an embodiment of the present invention. A cross-sectional view of a double-sided stacked conductor package structure of a signal path. The ninth diagram shows a cross-sectional view of a stacked conductor package structure with one of the signal channels in accordance with an embodiment of the present invention. A cross-sectional view of a package structure of an individual conductor seal 14 of an embodiment. [Description of main component symbols] Substrate 100, 200, 300, 406c Adhesive layer (material) 1〇1, 201, 301, 405, 414 Electronic component 102, 202, 302, 404 filling material 103, 203, 303, 407 conductors 104, 204, 304, 406d concave portions 204a, 304a call the die pad 105, 205, 305, 401 conductive layer 206, 306, 421 signal channel 207, 208, 307, 412 solder bumps / balls 209, 213 protective layer 210, 310, 312, 413 dielectric (buffer) layer 211, 212, 311, 411 electromagnetic interference shielding layer 220, 221 Antenna Structure 230 • Marker Layer 313, 422 Connection Area 350 Solder Wire 360 Exposure Area 370

S 15S 15

Claims (1)

201131705 七、申請專利範圍： 1. 一種導體封裝結構，包含： 一基板； 一黏耆層，形成於該基板之上； 至少一電子元件，形成於該黏著層之上； 複數個導體，形成於一填充材料之表面與底部之間以气 =連接’其中該填充材料係填人於該複數個導體之間的 空間及圍繞該電子元件；以及201131705 VII. Patent application scope: 1. A conductor package structure comprising: a substrate; an adhesive layer formed on the substrate; at least one electronic component formed on the adhesive layer; and a plurality of conductors formed on a space between the surface of the filler material and the bottom portion, wherein the filling material fills a space between the plurality of conductors and surrounds the electronic component; 件與該複導=電子疋件之上’並連接該電子元 2. t =項第1項之導體封裝結構，其中該基板可形成至 二二：於其申’或形成一圖形化之結構，其中該基板 幵y成於垓導體之間。 該電子_、 1項之導體封裝結構，其中該填充材料鄰接 ^ 兀件及該基板之側壁，並覆蓋該電子元件之主動 ，及/或暴露該導體之上表面與底表面。 於該電^第1項之導體封裝結構，更包含—導電層形成 該基板之元件與該黏著層之間，及7或形成於該導體及 5.如 求項第 1項之導體封裝結構，更包含一介電層形成 16 201131705 之下 於該重分佈層 6.如 二::之導體封裝結構’更包含- 保護層形成 I Si項第6項之導體封裝結構’更包含-第-電子元 ::成於該保護層之上，其中該第二電子元件 透圪-焊線而連接至該該重分佈層。 θ 8· 項第1項之導體封裝結構，更包含—電磁干擾遮 曰/成於戎導體封裝結構之底邊及/或側邊。 9. :::項第i項之導體封裝結構，更包含一天 成於或導體封裝結構之底邊上。 夕 10. 如請求項第1 ㈣目士員+導體兀件封裝結構’其中該導體的 底°卩具有凹形部分形成於其中。 17The conductor package structure of the first item is connected to the electronic component of the electronic component 2. t = item 1, wherein the substrate can be formed into two or two: in the form of a pattern or a patterned structure Wherein the substrate 幵y is formed between the tantalum conductors. The conductor package structure of the electronic article, wherein the filler material abuts the sidewall of the substrate and the substrate, and covers the active of the electronic component and/or exposes the upper surface and the bottom surface of the conductor. The conductor package structure of the first item further comprises: a conductive layer forming an element between the substrate and the adhesive layer, and 7 or formed on the conductor and 5. The conductor package structure according to item 1 of the item, Further comprising a dielectric layer formation 16 201131705 under the redistribution layer 6. The second:: conductor package structure 'more includes - the protective layer forms the Si Si item 6th conductor package structure' more includes - the first - electron Element: is formed on the protective layer, wherein the second electronic component is connected to the redistribution layer through a solder wire. The conductor package structure of item 1 of item θ 8 · further includes - electromagnetic interference shielding / formed on the bottom edge and / or side of the conductor package structure. 9. ::: The conductor package structure of item i, which further includes one day or the bottom edge of the conductor package structure. 10. As claimed in claim 1 (4), the conductor + conductor element package structure 'where the bottom of the conductor has a concave portion formed therein. 17
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