CN111430310A - 芯片内系统集成封装结构及其制作方法、立体堆叠器件 - Google Patents

芯片内系统集成封装结构及其制作方法、立体堆叠器件 Download PDF

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Publication number
CN111430310A
CN111430310A CN202010255403.6A CN202010255403A CN111430310A CN 111430310 A CN111430310 A CN 111430310A CN 202010255403 A CN202010255403 A CN 202010255403A CN 111430310 A CN111430310 A CN 111430310A
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China
Prior art keywords
chip
substrate
connection structure
groove
electric connection
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CN202010255403.6A
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Inventor
马书英
王姣
宋昆树
杨笑冰
肖智轶
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Huatian Technology Kunshan Electronics Co Ltd
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Huatian Technology Kunshan Electronics Co Ltd
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Priority to CN202010255403.6A priority Critical patent/CN111430310A/zh
Priority to PCT/CN2020/093970 priority patent/WO2021196394A1/zh
Publication of CN111430310A publication Critical patent/CN111430310A/zh
Priority to US17/957,060 priority patent/US20230022427A1/en
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Abstract

本发明提供一种芯片内系统集成封装结构及其制作方法、立体堆叠器件，其中，芯片内系统集成封装结构包括：基板、芯片、第一电连接结构以及第二电连接结构；基板具有正面和背面，其正面开设有凹槽和导通孔焊垫，背面开设有延伸至正面导通孔焊垫的导电通孔；芯片埋入基板正面的凹槽中，芯片的另一面具有芯片焊垫；第一电连接结构形成于基板的正面，第二电连接结构形成于基板的背面，第一电连接结构与导通孔焊垫和芯片焊垫电连接，第二电连接结构与导通孔焊垫电连接。通过第一电连接结构和第二电连接结构，不同的芯片之间可以通过第一电连接结构和第二电连接焊接，有利于形成高密度互连、封装小型化和轻薄化的立体堆叠结构。

Description

芯片内系统集成封装结构及其制作方法、立体堆叠器件
技术领域
本发明涉及半导体芯片技术领域，尤其涉及一种芯片内系统集成封装结构及其制作方法、立体堆叠器件。
背景技术
随着市场应用多元化发展，小型化高密度三维集成封装技术需求越来越多。目前，对于现有的硅基扇出型三维封装结构而言，其垂直导电通孔结构的开口是在芯片埋入面，实际工艺实现难度非常大，主要是由于该结构垂直通孔绝缘存在工艺缺陷，对比文件中埋入芯片后，采用聚合物填充芯片和硅基之间的缝隙，同时表面会存在一层聚合物绝缘层，完成通孔刻蚀后，通孔侧壁绝缘只能采用二氧化硅或者聚合物，二氧化硅无法在聚合物上沉积，采用聚合物喷涂方式无法保证侧壁挂胶，业内暂无合适材料均匀覆盖通孔侧壁，尤其针对高深宽比通孔结构。目前，三维堆叠结构普遍采用二氧化硅绝缘，需要在硅面沉积。另外对比专利需要研磨暴露出背面的金属pad，研磨同时涉及到金属，聚合物，硅三种材料同时研磨，需要用到化学机械抛光技术，设备昂贵，成本较高。
发明内容
本发明旨在提供一种芯片内系统集成封装结构及服务器，以克服现有技术中存在的不足。
为解决上述技术问题，本发明的技术方案是：
一种芯片内系统集成封装结构，其包括：基板、芯片、第一电连接结构以及第二电连接结构；
所述基板具有正面和背面，其正面开设有凹槽和导通孔焊垫，背面开设有延伸至所述正面导通孔焊垫的导电通孔；
所述芯片埋入所述基板正面的凹槽中，所述芯片的一面与所述凹槽的底面相粘接，所述芯片的另一面具有芯片焊垫，所述芯片与所述凹槽之间以及基板的正面具有第一绝缘层；
所述第一电连接结构形成于所述基板的正面，所述第二电连接结构形成于所述基板的背面，所述第一电连接结构通过第一金属重布线与所述导通孔焊垫和芯片焊垫电连接，所述第二电连接结构借助延伸至所述导电通孔中的第二金属重布线与所述导通孔焊垫电连接。
作为本发明的芯片内系统集成封装结构的改进，所述基板的材质为绝缘材质或非绝缘材质，所述基板为非绝缘材质时，所述基板的正面、凹槽的侧壁和底壁还沉积有氧化硅层。
作为本发明的芯片内系统集成封装结构的改进，所述凹槽顶部开口的尺寸不小于凹槽底部的尺寸，所述凹槽的深度小于或者等于所述基板的厚度，所述凹槽的截面形状为矩形或者梯形，所述截面为所述基板的正面和背面垂直相交的平面。
作为本发明的芯片内系统集成封装结构的改进，所述芯片内系统集成封装结构还包括第二绝缘层，所述第二绝缘层形成于所述第一绝缘层和第一金属重布线上。
作为本发明的芯片内系统集成封装结构的改进，所述第一电连接机构为形成于所述基板正面的焊球或者金属凸点。
作为本发明的芯片内系统集成封装结构的改进，所述第二电连接结构为形成于所述基板背面的焊球或者金属凸点。
作为本发明的芯片内系统集成封装结构的改进，所述基板的背面以及导电通孔的孔壁上形成有钝化层。
作为本发明的芯片内系统集成封装结构的改进，所述导电通孔由金属完全或部分填充，当部分填充时，所述导电通孔未填满的空间由干膜或者钝化胶所填充。
为解决上述技术问题，本发明的技术方案是：
一种芯片内系统集成封装结构的制作方法，其包括如下步骤：
提供一基板，在所述基板的正面通过刻蚀的方式形成至少一个凹槽；
在所述凹槽中通过粘接的方式固定芯片，并使得所述芯片和凹槽的侧壁之间预留间隙；
在所述基板的正面、芯片的焊垫面以及芯片与凹槽之间的间隙铺设第一绝缘层；
在所述第一绝缘层上制作第一金属重布线，并预留导通孔焊垫位置和芯片焊垫位置；
在所述第一绝缘层和第一重布线上制作第二绝缘层，并预留第一电连接结构的位置；
在预留的位置制作第一电连接结构；
在所述基板的正面涂布一层粘合胶层，并通过临时键合工艺将承载片键合在所述粘合胶层上；
对所述基板的背面进行减薄；
在所述基板的背面制作能够连通至位于所述导通孔焊垫位置的第一重布线的导电通孔，在所述基板的背面以及导电通孔的孔侧壁覆盖第一钝化层；
在所述第一钝化层上制作第二重布线，使其通过所述导电通孔与位于所述导通孔焊垫位置的第一重布线电连接；
在所述重布线的通孔中采用聚合物全部填充或者半填充；
在所述第一钝化层上制作第二钝化层，并预留第二电连接结构的位置；
在预留的位置制作第二电连接结构；
通过拆键合方式，去掉所述承载片，并清洗粘合胶。
为解决上述技术问题，本发明的技术方案是：
一种立体堆叠器件，其包括：至少两个层叠设置的如上所述的芯片内系统集成封装结构；
相邻的芯片内系统集成封装结构中，一个芯片内系统集成封装结构的第二电连接结构与另一个芯片内系统集成封装结构的第一电连接机构电连接。
与现有技术相比，本发明的有益效果是：本发明的芯片内系统集成封装结构具有如下优点：
(1)基板正面具有第一电连接结构，背面具有第二电连接结构，不同的芯片之间可以通过第一电连接结构和第二电连接焊接，有利于形成高密度互连、封装小型化和轻薄化的立体堆叠结构；
(2)凹槽和导电通孔的侧壁可以覆盖绝缘层，如果基板为绝缘材质，凹槽和导电通孔的侧壁可无需再做绝缘层，因此基板可以采用绝缘基板或者非绝缘基板，工艺实现方案灵活；
(3)基板正反两面垂直连接的导电通孔是背面开口式的；
(4)导电通孔通过RDL重布线后，先由聚合物全部填充，可降低后制程光刻过程通孔内残留光刻胶的风险，或通孔的结构可先由聚合物覆盖但不填充，可降低导电通孔内的应力。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明中记载的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1～13为本发明的芯片内系统集成封装结构的制作方法的工艺流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明垂直通孔开口在芯片埋入面背面，直接在硅面铺设绝缘层，优选二氧化硅绝缘，工艺成熟稳定，同时背面研磨减薄只需要减薄硅基板，工艺简单，成本更低，具有实际量产应用价值。
本发明一实施例提供一种芯片内系统集成封装结构。
如图13所示，该实施例的芯片内系统集成封装结构包括：基板1、芯片3、第一电连接结构8以及第二电连接结构11。
其中，基板1具有正面103和背面104。基板1可以采用绝缘材质或者非绝缘材质，绝缘材质可以是无机非金属材料，比如二氧化硅或氮化硅，也可以是有机高分子材料，比如聚亚酰胺、环氧树脂等。
为了实现芯片3的芯片内系统集成封装，基板1的正面103开设有凹槽2和导通孔焊垫，芯片3埋入基板1正面103的凹槽2中。此时，芯片3的一面与凹槽2的底面相粘接，芯片3的另一面具有芯片3焊垫，芯片3与凹槽2之间以及基板1的正面103具有第一绝缘层5，如此芯片3被包覆于凹槽2中。上述芯片3具有芯片3焊垫的一面接近基板1的正面103设置，如此有利于第一绝缘层5的制作，形成一平整的绝缘面。
如上所述，基板1的材质为绝缘材质或非绝缘材质，当基板1为非绝缘材质时，基板1的正面103、凹槽2的侧壁和底壁还沉积有氧化硅层；当基板1为绝缘材质时，可不必沉积氧化硅层。
凹槽2可通过干法刻蚀，湿法刻蚀，激光等技术形成。凹槽2的截面形状为矩形或者梯形，截面为基板1的正面103和背面104垂直相交的平面。凹槽2的俯视可以是矩形、正方形或其他适应多种芯片3排布和各种芯片3埋入的形状，凹槽2的上开口尺寸不小于凹槽2底部尺寸，深度小于或等于基板1的厚度，并且凹槽2尺寸可以满足芯片3放置于其中的要求。
背面104开设有延伸至正面103导通孔焊垫的至少一个导电通孔9。该导电通孔9可以是直孔或斜孔，导电通孔9可以通过干法刻蚀，激光等技术形成，用于信号互联。本实例优选采用直孔结构。
此外，导电通孔9由金属完全或部分填充，当部分填充时，导电通孔9未填满的空间由干膜或者钝化胶所填充。本实施例考虑到成本原因，导电通孔9不填满金属，导电通孔9不填满金属所预留空间可由干膜或钝化胶填充，形成堵孔结构，预留空隙可以全堵孔结构、半堵孔结构或者不堵孔结构。本实例优选全堵孔结构。
第一电连接结构8形成于基板1的正面103，第二电连接结构11形成于基板1的背面104，第一电连接结构8通过第一金属重布线6与导通孔焊垫和芯片3焊垫电连接，第二电连接结构11借助延伸至导电通孔9中的第二金属重布线109与导通孔焊垫电连接。如此，不同的芯片3之间可以通过第一电连接结构8和第二电连接焊接，有利于形成高密度互连、封装小型化和轻薄化的立体堆叠结构。
一个实施方式中，第一电连接机构为形成于基板1正面103的焊球或者金属凸点。相应的，第二电连接结构11也可以为形成于基板1背面104的焊球或者金属凸点。
此外，芯片内系统集成封装结构还包括第二绝缘层7，第二绝缘层7形成于第一绝缘层5和第一金属重布线6上。该第二绝缘层7上预留有制作第一电连接结构8的位置。基板1的背面104以及导电通孔9的孔壁上形成有钝化层10。该钝化层10预留有制作第二电连接结构11的位置。
基于上述实施例介绍的芯片内系统集成封装结构，本发明还提供一种制作方法，其包括如下步骤：
提供一基板，在基板的正面通过刻蚀的方式形成至少一个凹槽；
在凹槽中通过粘接的方式固定芯片，并使得芯片和凹槽的侧壁之间预留间隙；
在基板的正面、芯片的焊垫面以及芯片与凹槽之间的间隙铺设第一绝缘层；
在第一绝缘层上制作第一金属重布线，并预留导通孔焊垫位置和芯片焊垫位置；
在第一绝缘层和第一重布线上制作第二绝缘层，并预留第一电连接结构的位置；
在预留的位置制作第一电连接结构；
在基板的正面涂布一层粘合胶层，并通过临时键合工艺将承载片键合在粘合胶层上；
对基板的背面进行减薄；
在基板的背面制作能够连通至位于导通孔焊垫位置的第一重布线的导电通孔，在基板的背面以及导电通孔的孔侧壁覆盖第一钝化层；
在第一钝化层上制作第二重布线，使其通过导电通孔与位于导通孔焊垫位置的第一重布线电连接；
在导电通孔中至少部分地填充金属；
在第一钝化层上制作第二钝化层，并预留第二电连接结构的位置；
在预留的位置制作第二电连接结构；
通过拆键合方式，去掉承载片，并清洗粘合胶。
下面结合另一实施例对制作方法的技术方案进行举例说明。
本实施例的制作方法包括：
如图1所示，提供一基板1，基板1具有正面103和与其相对的背面104，在基板1的正面刻蚀形成至少一个凹槽2；凹槽2的垂直截面形状可以是梯形，矩形，俯视可以是矩形、正方形或其他适应多种芯片排布和各种芯片埋入的形状，凹槽2的上开口尺寸不小于凹槽2底部尺寸，深度小于或等于基板1的厚度，并且凹槽2尺寸可以满足芯片放置于内，基板1若为硅时，正面需沉积一层氧化硅层105作为绝缘层。基板1若为绝缘材质时，正面无需沉积氧化硅。
如图2所示，在凹槽2内通过粘附层4贴装至少一个芯片3，并使芯片3的焊垫面朝外，芯片3的焊垫面接近基板1的正面，且芯片3与凹槽2的侧壁之间具有间隙，具体实施时，芯片3可通过粘结胶或者干膜贴装到基板1凹槽2内，本实施采用的连接方式是利用粘结胶进行粘结。
如图3所示，在芯片3与凹槽2的侧壁之间的间隙内、芯片3的焊垫面上及基板1的正面上整面铺设一层第一绝缘层5，然后通过光刻预留导电通孔焊垫位置101和使芯片焊垫位置102暴露，具体实施时，第一绝缘层5可以通过涂布光刻胶的方式或压干膜的方式形成，本实施采用压干膜的方式，不仅填充间隙，同时形成第一绝缘层5。
如图4所示，在第一绝缘层5上制作第一金属重布线6，通过第一金属重布线6电连接预留导电通孔焊垫位置101和芯片焊垫位置102。
如图5所示，在第一金属重布线6上制作第二绝缘层7，并通过光刻预留焊球焊盘6；第二绝缘层7与第一绝缘层的材质可以相同，也可以近似。优选的，第二绝缘层的方式是采用旋涂方式制备。
如图6所示，在基板1正面上的焊盘处形成有电性导出结构8。电性导出结构可以为或焊球或者金属凸点等，本实施例中优选金属凸点，参见图6所示。金属凸点的制作方式是电镀与回流工艺，金属材质为铜、镍、钯、金、锡和银或铜、镍、锡和银一种或几种，本实施例中优选铜、镍、锡和银。
如图7所示，在基板1正面涂布一层粘合胶层13，用来保护金属凸点8，并通过临时键合工艺将承载片12键合在粘合胶层13上面，用来支撑基板1做背面加工，承载片材质可以是玻璃、硅、金属或塑料。本实施例中，优选玻璃作为承载片，利用玻璃的透光性能，在玻璃内表面涂布一层感光材料，最终通过激光解键合工艺拆掉玻璃。
如图8所示，对基板1背面进行研磨减薄。基板1减薄的工艺可以是研磨、干法或湿法刻蚀中的一种或者两种相结合，本实施例中，优选研磨与干法，研磨去除多余的硅，干法刻蚀掉因研磨产生的应力应变层。
如图9所示，在基板1背面的凹槽2背面以外区域制作至少一个导电通孔9，至少一个导电通孔可以是直孔或斜孔，直孔通过干法刻蚀、激光等技术形成通孔，用于信号互联。本实例优选直孔，直孔侧壁和基板1背面覆盖背面第一层钝化层108，其可以选择二氧化硅。背面第一钝化层108可以选用钝化胶喷涂、干膜或化学气相沉积的工艺，并通过光刻显影或化学刻蚀的方法，使孔底导电通孔焊垫101暴露出来。本实例优选化学气相沉积工艺，沉积一层氧化硅覆盖在硅基背面104和垂直导电通孔9内，垂直导电通孔9底部的氧化硅通过氧化层刻蚀工艺去除，使导电通孔焊垫101暴露出来。
如图10所示，在导电通孔9和背面第一钝化层108表面制作第二重布线109，并使第二重布线109与导电通孔焊垫位置101电连接。具体实施时，每层金属重布线的金属材质可以是铜、镍、靶、金中的一种或两种，形成金属重布线的方法可以为电镀、化学镀、真空蒸镀法、物理汽相沉积中的一种或两种。导电通孔内的金属填充可以填满孔也可以只填充一部分；本实施例考虑到成本原因，导电通孔不填满金属。由于把整个直孔填充便于制程作业，导电通孔不填满金属所预留空间可由干膜或钝化胶或其它聚合物填充，形成堵孔结构110，预留空隙可以全堵孔结构、半堵孔结构或者不堵孔结构；本实例优选全堵孔结构。优选的，导电通孔内的金属重布线的材质为钛、铜。
如图11所示，在背面第一金属重布线109上制作背面第二钝化层10，背面第二钝化层材质可以和堵孔结构110材料相同或相近，并通过光刻工艺制作焊盘112。
如图12所示，在基板1背面上的焊盘处形成有电性导出结构11。电性导出结构11可以为或焊球或者金属凸点等，本实施例中优选金属凸点。金属凸点的制作方式是电镀，金属材质为铜、镍、钯、金、锡和银或铜、镍、锡和银等，本实施例中优选铜、镍和金。
如图13所示，通过拆键合技术，去掉承载片12，清洗掉粘合胶13。拆键合技术有机械拆键合，热拆键合，激光拆键合和紫外拆键合等，本实例优先激光拆键合。
本发明还提供一种立体堆叠器件，其包括：至少两个层叠设置的如上所述的芯片内系统集成封装结构。具体地，相邻的芯片内系统集成封装结构中，一个芯片内系统集成封装结构的第二电连接结构与另一个芯片内系统集成封装结构的第一电连接机构电连接。如此，可形成高密度互连、封装小型化和轻薄化的立体堆叠结构。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
此外，应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施例中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。

Claims (10)

1.一种芯片内系统集成封装结构，其特征在于，所述芯片内系统集成封装结构包括：基板、芯片、第一电连接结构以及第二电连接结构；
所述基板具有正面和背面，其正面开设有凹槽和导通孔焊垫，背面开设有延伸至所述正面导通孔焊垫的导电通孔；
所述芯片埋入所述基板正面的凹槽中，所述芯片的一面与所述凹槽的底面相粘接，所述芯片的另一面具有芯片焊垫，所述芯片与所述凹槽之间以及基板的正面具有第一绝缘层；
所述第一电连接结构形成于所述基板的正面，所述第二电连接结构形成于所述基板的背面，所述第一电连接结构通过第一金属重布线与所述导通孔焊垫和芯片焊垫电连接，所述第二电连接结构借助延伸至所述导电通孔中的第二金属重布线与所述导通孔焊垫电连接。
2.根据权利要求1所述的芯片内系统集成封装结构，其特征在于，所述基板的材质为绝缘材质或非绝缘材质，所述基板为非绝缘材质时，所述基板的正面、凹槽的侧壁和底壁还沉积有氧化硅层。
3.根据权利要求1所述的芯片内系统集成封装结构，其特征在于，所述凹槽顶部开口的尺寸不小于凹槽底部的尺寸，所述凹槽的深度小于或者等于所述基板的厚度，所述凹槽的截面形状为矩形或者梯形，所述截面为所述基板的正面和背面垂直相交的平面。
4.根据权利要求1所述的芯片内系统集成封装结构，其特征在于，所述芯片内系统集成封装结构还包括第二绝缘层，所述第二绝缘层形成于所述第一绝缘层和第一金属重布线上。
5.根据权利要求1所述的芯片内系统集成封装结构，其特征在于，所述第一电连接机构为形成于所述基板正面的焊球或者金属凸点。
6.根据权利要求1或5所述的芯片内系统集成封装结构，其特征在于，所述第二电连接结构为形成于所述基板背面的焊球或者金属凸点。
7.根据权利要求1所述的芯片内系统集成封装结构，其特征在于，所述基板的背面以及导电通孔的孔壁上形成有钝化层。
8.根据权利要求1所述的芯片内系统集成封装结构，其特征在于，所述导电通孔由金属完全或部分填充，当部分填充时，所述导电通孔未填满的空间由干膜或者钝化胶所填充。
9.一种芯片内系统集成封装结构的制作方法，其特征在于，所述制作方法包括如下步骤：
提供一基板，在所述基板的正面通过刻蚀的方式形成至少一个凹槽；
在所述凹槽中通过粘接的方式固定芯片，并使得所述芯片和凹槽的侧壁之间预留间隙；
在所述基板的正面、芯片的焊垫面以及芯片与凹槽之间的间隙铺设第一绝缘层；
在所述第一绝缘层上制作第一金属重布线，并预留导通孔焊垫位置和芯片焊垫位置；
在所述第一绝缘层和第一重布线上制作第二绝缘层，并预留第一电连接结构的位置；
在预留的位置制作第一电连接结构；
在所述基板的正面涂布一层粘合胶层，并通过临时键合工艺将承载片键合在所述粘合胶层上；
对所述基板的背面进行减薄；
在所述基板的背面制作能够连通至位于所述导通孔焊垫位置的第一重布线的导电通孔，在所述基板的背面以及导电通孔的孔侧壁覆盖第一钝化层；
在所述第一钝化层上制作第二重布线，使其通过所述导电通孔与位于所述导通孔焊垫位置的第一重布线电连接；
在所述重布线的通孔中采用聚合物全部填充或者半填充；
在所述第一钝化层上制作第二钝化层，并预留第二电连接结构的位置；
在预留的位置制作第二电连接结构；
通过拆键合方式，去掉所述承载片，并清洗粘合胶。
10.一种立体堆叠器件，其特征在于，所述立体堆叠器件包括：至少两个层叠设置的如权利要求1至8任一项所述的芯片内系统集成封装结构；
相邻的芯片内系统集成封装结构中，一个芯片内系统集成封装结构的第二电连接结构与另一个芯片内系统集成封装结构的第一电连接机构电连接。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112530874A (zh) * 2020-12-02 2021-03-19 赛莱克斯微系统科技（北京）有限公司 一种三维晶圆集成结构及其制备方法、电子设备
CN113782492A (zh) * 2021-09-10 2021-12-10 京东方科技集团股份有限公司 基板及其制备方法、电学器件、集成电路板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5306670A (en) * 1993-02-09 1994-04-26 Texas Instruments Incorporated Multi-chip integrated circuit module and method for fabrication thereof
CN101232008A (zh) * 2007-01-03 2008-07-30 育霈科技股份有限公司 多晶粒封装及其方法
CN103208428A (zh) * 2012-01-12 2013-07-17 欣兴电子股份有限公司 封装基板及其制法
CN105575913A (zh) * 2016-02-23 2016-05-11 华天科技（昆山）电子有限公司 埋入硅基板扇出型3d封装结构
CN109148431A (zh) * 2018-07-18 2019-01-04 华天科技（昆山）电子有限公司 距离传感器芯片封装结构及其晶圆级封装方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG10201505279RA (en) * 2008-07-18 2015-10-29 Utac Headquarters Pte Ltd Packaging structural member
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US8941222B2 (en) * 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US8669655B2 (en) * 2012-08-02 2014-03-11 Infineon Technologies Ag Chip package and a method for manufacturing a chip package
TWI581376B (zh) * 2014-09-17 2017-05-01 矽品精密工業股份有限公司 封裝結構及其製法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5306670A (en) * 1993-02-09 1994-04-26 Texas Instruments Incorporated Multi-chip integrated circuit module and method for fabrication thereof
CN101232008A (zh) * 2007-01-03 2008-07-30 育霈科技股份有限公司 多晶粒封装及其方法
CN103208428A (zh) * 2012-01-12 2013-07-17 欣兴电子股份有限公司 封装基板及其制法
CN105575913A (zh) * 2016-02-23 2016-05-11 华天科技（昆山）电子有限公司 埋入硅基板扇出型3d封装结构
CN109148431A (zh) * 2018-07-18 2019-01-04 华天科技（昆山）电子有限公司 距离传感器芯片封装结构及其晶圆级封装方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112530874A (zh) * 2020-12-02 2021-03-19 赛莱克斯微系统科技（北京）有限公司 一种三维晶圆集成结构及其制备方法、电子设备
CN113782492A (zh) * 2021-09-10 2021-12-10 京东方科技集团股份有限公司 基板及其制备方法、电学器件、集成电路板
CN113782492B (zh) * 2021-09-10 2024-05-07 京东方科技集团股份有限公司 基板及其制备方法、电学器件、集成电路板

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Application publication date: 20200717

RJ01 Rejection of invention patent application after publication