CN102148206B - 半导体装置封装件及其制造方法 - Google Patents

半导体装置封装件及其制造方法 Download PDF

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CN102148206B
CN102148206B CN2011100216214A CN201110021621A CN102148206B CN 102148206 B CN102148206 B CN 102148206B CN 2011100216214 A CN2011100216214 A CN 2011100216214A CN 201110021621 A CN201110021621 A CN 201110021621A CN 102148206 B CN102148206 B CN 102148206B
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chip
active
substrate
bridging
semiconductor device
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CN102148206A (zh
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张效铨
蔡宗岳
赖逸少
郑明祥
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Semiconductor Integrated Circuits (AREA)

Abstract

一种半导体装置封装件及其制造方法。半导体装置封装件包括基板、缓冲结构、二主动芯片及桥接芯片。基板具有凹部及相对的第一面与第二面。凹部从第一面往第二面延伸，缓冲结构设于凹部。二主动芯片机械性地设置于且电性连接于第一面，二主动芯片环绕凹部，其中，二主动芯片皆具有第一主动面。桥接芯片设于凹部及缓冲结构之上，其中桥接芯片具有第二主动面，第二主动面面向第一主动面且部分地重迭于第一主动面，桥接芯片用以提供二主动芯片之间的相邻通信。

Description

半导体装置封装件及其制造方法
技术领域
本发明是有关于一种装置封装件，且特别是有关于一种半导体装置封装件。
背景技术
目前来讲，半导体技术应用于不胜枚举的产品，例如是存储卡、计算机、移动电话、监视器等。由于半导体组件的尺寸细微及脆弱特性，半导体工艺对精密度要求较高。因此，如果发生错误，每个步骤严格地被监控。然而，即使半导体相关产品的良率及质量有限，客户对产品功能的要求仍逐渐地提高。
在制造上，半导体装置封装件在芯片受到应力时，容易因为封装的芯片的裂缝而损坏。芯片的裂缝大多因为加工细微特征或由于芯片的易脆特性而导致。因此有必要去寻求以上问题的解决方法。
发明内容
本发明有关于一种半导体装置封装件及其制造方法。半导体装置封装件具有缓冲结构，其用以控制芯片与基板之间的间隙，以及吸收对芯片的冲击，可避免芯片的损坏，因此提升相关产品的良率及质量。
根据本发明第一方面，提出一种半导体装置封装件。半导体装置封装件包括一基板、一缓冲结构(buffer structure)、二主动芯片及一桥接芯片(bridge chip)。基板具有一凹部及相对的一第一面与一第二面，其中，凹部从第一面往第二面延伸。缓冲结构设于凹部。二主动芯片机械性地设置于且电性连接于第一面，二主动芯片环绕凹部，其中，二主动芯片皆具有一第一主动面。桥接芯片设于凹部及缓冲结构之上，其中桥接芯片具有一第二主动面，第二主动面面向第一主动面且部分地重迭于第一主动面，桥接芯片用以提供二主动芯片之间的一相邻通信(proximitycommunication)。
根据本发明第二方面，提出一种半导体装置封装件的制造方法。制造方法包括以下步骤。提供一芯片组件，该芯片组件包括二主动芯片及一桥接芯片，其中该桥接芯片具有一主动面，该主动面各别地面向且部分地重迭于二主动芯片的数个主动面，藉以提供二主动芯片之间的一相邻通信；形成一发泡材料于一基板或该桥接芯片的一背面；机械性地且电性地连接二主动芯片至基板，以使发泡材料设于基板与桥接芯片的背面之间；以及，经由加热基板，扩张发泡材料以形成一缓冲结构填满基板与桥接芯片之间的间隙。
为让本发明的上述内容能更明显易懂，下文特举实施例，并配合附图，作详细说明如下：
附图说明
图1绘示依照本发明一实施例的半导体装置封装件的示意图。
图2绘示依照本发明另一实施例的半导体装置封装件的示意图。
图3绘示依照本发明再一实施例的半导体装置封装件的示意图。
图4绘示依照本发明一实施例的半导体装置封装件的制造方法流程图。
图5A至5C绘示图1的半导体装置封装件的制造步骤。
图6A至6C绘示图2的半导体装置封装件的制造步骤。
主要组件符号说明：
100、200、200′：半导体装置封装件
100a、200a：芯片组件
101、201：基板
101a、201a：第一面
101b、201b：第二面
103、203：缓冲结构
103a、203a：发泡材料
105、107、205、207：主动芯片
105a、107a、109a、205a、207a、209a：信号接垫
109、209：桥接芯片
109b：背面
111：凹部
113、115、215、217：黏贴层
117a、119a：焊块
121、123、125、221、223、225：主动面
211、213：柱体组
219：底胶
203a′：缓冲突部
具体实施方式
图1绘示依照本发明一实施例的半导体装置封装件的示意图。半导体装置封装件100包括一基板101、一缓冲结构103、二主动芯片105、107及一桥接芯片109。基板101具有一凹部111及相对的一第一面101a与一第二面101b。凹部111从第一面101a往第二面101b延伸，且缓冲结构103设于凹部111。主动芯片105及107机械性地设于第一面101a且连接于第一面101a，主动芯片105及107环绕凹部111。主动芯片105及107皆具有一主动面。桥接芯片109设于凹部111及缓冲结构103之上。桥接芯片109具有一主动面，其面向主动芯片105及107的主动面且部分地重迭于主动芯片105及107的主动面。因此，桥接芯片109可用以提供主动芯片105与107之间的相邻通信(proximity communication)。
缓冲结构103包括一发泡材料(vesicant material)，其较佳地一热固性材料(thermosetting material)。例如，发泡材料隙一热移除胶(heat release tape)。特别地，热移除胶Revalpha#3195MS热移除胶。其结合强度在约90℃至约150°C之间时降低，Revalpha#3195MS热移除胶来自于日本大阪的Nitto Denko。缓冲结构103可帮助控制主动芯片105与107之间的间隙、避免桥接芯片109在制造过程中直接接触基板101以及支撑桥接芯片109。
如图1所示，半导体装置封装件100包括二黏贴层113及115。黏贴层113设于主动芯片105与桥接芯片109之间，而黏贴层115设于主动芯片107与桥接芯片109之间。黏贴层113及115用以结合主动芯片105、107与桥接芯片109。黏贴层113及115由底胶(underfill)组成。在一实施例，黏贴层113及115可包括阻隔球(spacer ball)以帮助控制主动芯片与桥接芯片之间的间隙。以电容耦接(capacitivecoupling)的传送为例，主动芯片105及107皆具有数个信号接垫，例如是信号接垫105及107a，其至少部分地且各别地对齐设于桥接芯片109上的数个信号接垫109a，如此，因为主动芯片105及107的信号接垫电容或电感耦合于桥接芯片109的信号接垫，而提供主动芯片105、107与桥接芯片109之间的信号通信，主动芯片105及107的一对信号接垫与桥接芯片109之间产生电容效应。电容耦合提供主动芯片105与桥接芯片109之间及主动芯片107与桥接芯片109之间的信号路径。一信号接垫的表面金属的电位能改变导致包括对应的信号接垫的金属的电位能改变。个别芯片的适当的传送电路的驱动器及接受电路的感测电路可透过尽可能小的电容产生通信。
如图1所示，主动芯片105及107分别透过焊块(solder bump)117a及119a机械性地且电性地连接至基板101的第一面101a上的触点或接垫(未绘示)。芯片与基板之间的间隙被底胶117及119密封，藉以强化及稳地芯片与基板之间的连接以及增加芯片与基板之间焊料的接合可靠度。
此外，主动芯片105及107透过金属凸块可机械性地且电性地连接至第一面101a，金属凸块于芯片的接合接垫与及异方性导电胶膜(anisotropic conductiveadhesive film，ACF)的接合过程中预形成。适于形成异方性导电胶膜的一种异方性黏剂一般z轴异方性黏剂(z-axis anisotropic adhesive)。z轴异方性黏剂由导电粒子填充至一低阶层(low level)，以使粒子不沿xy平面接触。因此，材料沿z方向压缩后建立电性路径。
图2绘示依照本发明另一实施例的半导体装置封装件的示意图。半导体装置封装件200包括基板201、缓冲结构203、二主动芯片205及207、桥接芯片209及二柱体组211及213。基板201具有相对的第一面201a与第二面201b。缓冲结构203设于第一面201a。柱体组211及213分别设于缓冲结构203的二侧，且柱体组211与213中每一者具有数个柱体。柱体组211与213的该些柱体可以是由铜、银、金等制成的导电柱。
主动芯片205及207设于柱体组211及213且经由柱体组211及213电性连接于第一面201a。主动芯片205及207皆具有主动面。主动芯片205及207分别具有数个信号接垫，例如是信号接垫205a及207a。桥接芯片209设于缓冲结构203及主动芯片205及207的下。桥接芯片209具有一主动面及数个信号接垫209a。桥接芯片209的主动面面向主动芯片205及207的主动面且信号接垫205a及207a对齐位于桥接芯片209的主动面上的信号接垫209a，以使桥接芯片209可提供主动芯片205与207之间的相邻通信。
如图2所示，半导体装置封装件200包括二黏贴层215及217。黏贴层215设于主动芯片205与桥接芯片209之间，用以结合主动芯片205与桥接芯片209。黏贴层217设于主动芯片207与桥接芯片209之间，用以结合主动芯片207与桥接芯片209。黏贴层215及217由底胶材料所形成。在一实施例，黏贴层215及217可包括阻隔球以帮助控制主动芯片与桥接芯片之间的间隙。
半导体装置封装件200包括底胶219。底胶219设于柱体组211、213与基板201之间且填充于柱体组211及213内的空间。底胶219用以提升柱体组211及213连接至基板201的连接性以及保护柱体组211及213的柱体。
上述所揭露的缓冲结构层结构，然本发明实施例不限于此。图3绘示依照本发明再一实施例的半导体装置封装件的示意图。半导体装置封装件200’与半导体装置封装件200不同之处在于缓冲结构，而相同组件使用相同标号，不重复赘述。缓冲结构203’包括数个缓冲部(knob)203a’。桥接芯片209设于缓冲突部203a’上。
图4绘示依照本发明一实施例的半导体装置封装件的制造方法流程图。制造方法包括步骤S11至S14且描述图1的半导体装置封装件100的制造过程。图5A至5C绘示图1的半导体装置封装件100的制造步骤。
首先，于步骤S11中，如图5A所示，提供芯片组件100a。芯片组件100a包括二主动芯片105及107及桥接芯片109。其中，桥接芯片109具有一主动面125，其面向且部分地重迭于主动芯片105及107的主动面121及123，藉以提供主动芯片105与107之间的相邻通信。主动芯片105及107透过二黏贴层113及115连接至桥接芯片109。
接着，于步骤S12中，如图5A所示，发泡材料103a形成于基板101，或者发泡材料103a形成于桥接芯片109的背面109b。基板101具有凹部111，其用以容纳桥接芯片109。较佳地，发泡材料103a涂布于易定位的凹部111。
接着，于步骤S13中，如图5B所示，主动芯片105及107机械地且电性地连接至基板101，使发泡材料103a设于基板101与桥接芯片109的背面109b之间。本步骤一开始，倒置芯片组件100a(绘示于图5A)，且在连接主动芯片105及107至基板101之前，将桥接芯片109对齐凹部111。在桥接芯片109位于凹部111之后，执行回焊(reflow)工艺以熔化预形成于主动芯片105及107上的焊块117a及119a，以形成一相对应的芯片上的接垫或触点与基板之间的焊接合，藉以机械性地且电性地设置主动芯片105及107至基板101。并且，主动芯片105、107及基板101之间的间隙受到底胶117及119的密封，藉以强化及稳定芯片与基板之间的连接以及增加芯片与基板之间焊料的接合可靠度。
接着，于步骤S14中，经由加热基板101，扩张发泡材料103a，以形成缓冲结构103填满基板101与桥接芯片109之间的间隙，如图5C所示。至此，完成半导体装置封装件100的制造。
图6A至6C绘示图2的半导体装置封装件100的制造步骤。如图6A所示，提供芯片组件200a。芯片组件200a包括二主动芯片205及207及桥接芯片209。其中，桥接芯片209具有一主动面225，其面向且部分地重迭于主动芯片205及207的主动面221及223，藉以提供主动芯片205与207之间的相邻通信。主动芯片205及207透过二黏贴层215及217连接至桥接芯片109。芯片组件200a更包括二柱体组211及213，其分别设于主动经片205及207，且位于桥接芯片209的二侧。
接着，一发泡材料203a形成于基板201的第一面201。
接着，主动芯片205及207机械性地且电性地连接于基板201，使发泡材料203a设于基板201与桥接芯片209之间，且二柱体组211及213位于发泡材料203a及桥接芯片209的二侧。
接着，经由加热基板201，扩张发泡材料203a，以形成缓冲结构203填充基板201与桥接芯片209之间的间隙，如图6B所示。
接着，提供一底胶材料填充柱体组211及219内的空间，以形成底胶219，如图6C所示，藉以提升柱体组211及219连接至基板201的结合性，以及保护柱体组211及219的该些柱体。至此，完成半导体装置封装件200的制造。图3的半导体装置封装件200’的制造相似于半导体装置封装件200的制造，容此不再重复赘述。
本发明上述实施例的半导体装置封装件及其制造方法，半导体装置封装件具有一缓冲结构填充桥接芯片与基板之间的间隙，以提供桥接芯片的支撑，避免桥接芯片直接接触基板，因此消除作用于桥接芯片的作用力导致半导体装置封装件的应力发生的可能性。此外，缓冲结构可形成一层或数个缓冲突部，其可吸收对桥接芯片的机械冲击。如此一来，可提升半导体装置封装件的质量及良率。
综上所述，虽然本发明已以实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视权利要求书所界定者为准。

Claims (9)

1.一种半导体装置封装件，包括：
一基板，具有一凹部及相对的一第一面与一第二面，其中，该凹部从该第一面往该第二面延伸；
一缓冲结构，设于该凹部，其中该缓冲结构包括一发泡材料；
二主动芯片，机械性地设置于且电性连接于该第一面，其中，该二主动芯片皆具有一第一主动面；以及
一桥接芯片，设于该凹部及该缓冲结构之上，其中该桥接芯片具有一第二主动面，该第二主动面面向该第一主动面且部分地重迭于该第一主动面，该桥接芯片用以提供该二主动芯片之间的一相邻通信。
2.如权利要求1所述的半导体装置封装件，其中该发泡材料是一热固型材料。
3.如权利要求1所述的半导体装置封装件，其中该缓冲结构包括数个突部。
4.如权利要求1所述的半导体装置封装件，更包括：
数个焊块，设于该二主动芯片与该第一面之间。
5.如权利要求1所述的半导体装置封装件，其中各该二主动芯片包括一第一信号接垫，该第一信号接垫设于该第一主动面，该桥接芯片包括二第二信号接垫，该二第二信号接垫设于该第二主动面且电容耦合或电感耦合于该些第一信号接垫。
6.一种半导体装置封装件的制造方法，包括：
提供一芯片组件，该芯片组件包括二主动芯片及一桥接芯片，其中该桥接芯片具有一主动面，该主动面面向且部分地重迭于该二主动芯片的数个主动面，藉以提供该二主动芯片之间的一相邻通信；
形成一发泡材料于一基板或该桥接芯片的一背面；
机械性地且电性地连接该二主动芯片至该基板，以使该发泡材料设于该基板与该桥接芯片的该背面之间；以及
经由加热该基板，扩张该发泡材料以形成一缓冲结构填满该基板与该桥接芯片之间的间隙。
7.如权利要求6所述的制造方法，其中该基板更具有一凹部，该发泡材料涂布于该凹部。
8.如权利要求6所述的制造方法，其中该芯片组件更包括：
二柱体组，设于该二主动芯片且位于该桥接芯片的二侧，该发泡材料位于该二柱体组之间。
9.如权利要求8所述的制造方法，其中于连接该二主动芯片至该基板的该步骤之后，该制造方法更包括：
经由一底胶，填充该二柱体组内的空间。
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