CN104733436A - 具有嵌入式桥的集成电路封装 - Google Patents

具有嵌入式桥的集成电路封装 Download PDF

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Publication number
CN104733436A
CN104733436A CN201410657812.3A CN201410657812A CN104733436A CN 104733436 A CN104733436 A CN 104733436A CN 201410657812 A CN201410657812 A CN 201410657812A CN 104733436 A CN104733436 A CN 104733436A
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Prior art keywords
tube core
bridge
insulating material
electrical insulating
interconnection structure
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CN201410657812.3A
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CN104733436B (zh
Inventor
R·V·玛哈简
C·J·尼尔森
O·G·卡哈德
F·艾德
N·A·德斯潘德
S·M·利夫
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Intel Corp
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Intel Corp
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Abstract

本文描述了具有嵌入式桥的集成电路封装。本公开的实施例涉及一种集成电路(IC)封装，集成电路封装具有分别具有第一和第二输入/输出(I/O)互连结构的第一和第二管芯。IC封装可包括具有分别耦合至第一和第二I/O互连结构的一部分的第一和第二电路由特征的桥。在实施例中，第一和第二电路由特征可设置在桥的一侧上；以及第三电路由特征可设置在相对侧上。第一和第二电路由特征可配置成在第一管芯和第二管芯之间路由电信号，以及第三电路由特征可配置成在一侧和相对侧之间路由电信号。第一管芯、第二管芯、和桥可嵌入在电绝缘材料中。可描述和/或要求保护其它的实施例。

Description

具有嵌入式桥的集成电路封装
技术领域
本公开的实施例一般涉及集成电路的领域，并且更具体地，涉及具有嵌入式桥的集成电路封装。
背景技术
管芯(诸如，处理器)的输入/输出密度持续增加。在具有互连密度的封装上集成多个管芯是重要的以实现高计算能力。由于大硅面积，如硅插入器(interposer)一样的高密度互连技术是昂贵的。嵌入在衬底中的互连桥使用比硅插入器更少硅。
附图说明
通过结合附图的以下详细描述将容易理解多个实施例。为了便于该描述，相同的附图标记指示相同结构的元件。在附图的多个图中通过示例而非作为限制地说明多个实施例。
图1示意性地示出了根据本公开的一些实施例的示例集成电路(IC)组件的截面侧视图。
图2为根据本公开的一些实施例的集成电路封装制造过程的示例性流程图。
图3为根据本公开的实施例的示出了图2中描述的集成电路封装制造过程中的阶段的所选择的操作的示例性截面图。
图4为根据本公开的一些实施例的集成电路封装的示例性截面图。
图5为根据本公开的一些实施例的另一集成电路封装制造过程的示例性流程图。
图6为根据本公开的一些实施例的示出了图5中描述的集成电路封装制造过程中的阶段的所选择的操作的示例性截面图。
图7为根据本公开的实施例的利用集成电路封装的组装过程的示例性流程图。
图8示意性地示出了根据本公开的一些实施例的包括集成电路封装的计算设备。
具体实施方式
本公开的实施例描述了用于具有嵌入式桥的集成电路封装的技术和配置。在以下描述中，将使用本领域技术人员所通常使用的术语来描述示例性实现的各个方面，以向其他本领域技术人员传达它们的工作的实质。然而，对本领域技术人员将显而易见的是，仅采用所描述方面中的一些也可实施本公开的实施例。为了说明的目的，陈述具体的数字、材料和配置以提供对示例性实现的全面理解。然而，本领域技术人员将可理解，没有这些特定细节也可实施本公开的实施例。在其他实例中，省略或简化已知特征以不模糊示例性实现。
在以下详细描述中，参照形成本说明书的一部分的附图，其中在全部附图中相同的标记指示相同的部件，并且在附图中以可实施本发明的主题的示例实施例的方式显示。将理解，可利用其它实施例，且可做出结构上或逻辑上的改变，而不偏离本公开的范围。因此，以下详细描述不应按照限制性意义来理解，且多个实施例的范围由所附权利要求及其等价方案来限定。
为了本公开的目的，短语“A和/或B”表示(A)、(B)或(A和B)。为了本公开的目的，短语“A、B和/或C”表示(A)、(B)、(C)、(A和B)、(A和C)、(B和C)或(A、B和C)。
说明书可使用基于视角的描述，诸如顶部/底部、内/外、上/下等等。这种描述仅用于便于讨论并且不旨在将本文所描述的实施例的应用限制在任何特定方向。
说明书可使用短语“在实施例中”或“在多个实施例中”，它们均可表示相同或不同实施例中的一个或多个。此外，有关本公开的多个实施例使用的术语包括摂、包含摂、具有摂等等是同义的。
本文可使用术语“与……耦合”及其派生词。“耦合”可表示以下一个或多个。“耦合”可表示两个或多个元件直接物理或电气接触。然而，“耦合”还可表示两个或多个元件彼此间接接触，但仍彼此协作或交互，以及可表示一个或多个其他元件被耦合或连接在所述将彼此耦合的元件之间。术语直接耦合摂可表示两个或多个元件直接接触。
在各个实施例中，短语在第二特征上形成、沉积或以其他方式设置摂，可表示第一特征被形成、沉积、或设置在第二特征之上，并且第一特征的至少一部分可与第二特征的至少一部分直接接触(例如，直接物理和/或电接触)或间接接触(在第一特征和第二特征之间具有一个或多个其他特征)。
本文所使用的术语模块摂可表示以下部件、作为以下部件的部分、或包括以下部件：专用集成电路(ASIC)、电子电路、片上系统(SoC)、执行一个或多个软件或固件程序的处理器(共享的、专用的、或组)和/或存储器(共享的、专用的、或组)、组合逻辑电路、和/或提供所描述功能的其他合适的部件。
图1示意性地示出了示例集成电路(IC)组件100的截面侧视图。在一些实施例中，IC组件100可包括IC封装108，IC封装108具有管芯102a和102b(在下文中，“管芯102”)、功率管理模块118a和118b(在下文中，“功率管理模块118”)、以及一个或多个桥120。在一些实施例中，桥120可与一个或多个附加管芯126电耦合。在一些实施例中，IC封装108还可包括散热器122。
如所述的，IC封装108可与封装衬底104电且物理地耦合。如所述的，封装衬底104可进一步与电路板116电且物理地耦合。下面参照图2-8进一步详细描述IC封装108。
IC封装108可104根据各种合适的配置附连至封装衬底104，例如，各种合适的配置包括所述的倒装配置，或诸如例如被嵌入在封装衬底104中或以引线接合布置配置的其他配置。在倒装配置中，IC封装108可利用管芯互连结构106(诸如，凸块、柱、或也可将IC封装108与封装衬底104电耦合的其他合适的结构)附连至封装衬底104的表面。
在一些实施例中，IC封装108可表示由半导体材料制造的分立芯片，并且可包括以下部件或作为以下部件的一部分：处理器、存储器、或ASIC。在一些实施例中，诸如例如模制化合物或底部填充材料之类的电绝缘材料124可包封管芯108的一部分、和/或互连结构106。管芯互连结构106可配置成路由IC封装108和封装衬底104之间的电信号。
封装衬底104可包括配置成路由至IC封装108或从IC封装108路由的电路由特征(未描绘)。电路由特征可包括，例如，设置在封装衬底104的一个或多个表面上的迹线和/或例如，诸如沟槽、通孔或用于通过封装衬底104路由电信号的其他内部结构的内部路由特征。
在一些实施例中，例如，封装衬底104为具有芯和/或构建层的基于环氧树脂的层压衬底，诸如Ajinomoto构建膜(ABF)衬底。封装衬底104可包括在其他实施例中的其他合适类型的衬底，包括例如由玻璃、陶瓷、或半导体材料形成的衬底。
电路板116可以为由电绝缘材料(诸如环氧层压板)组成的印刷电路板(PCB)。例如，电路板116可包括由诸如聚四氟乙烯、酚树脂醛棉纸材料(诸如，阻燃剂4(FR-4)、FR-1、棉纸和环氧材料(诸如，CEM-1或CEM-3)、或利用环氧树脂预浸材料层叠一起的编织的玻璃材料组成的电绝缘层。诸如通孔之类的结构(未描绘)可通过电绝缘材料形成以通过电路板116路由管芯102的电信号。在其他实施例中，电路板116可由其他合适的材料组成。在一些实施例中，电路板116可以为母板(例如，图8的母板802)。
例如，封装级互连，诸如焊球12可耦合至封装衬底104上的一个或多个焊盘(land)(在下文中“焊盘110”)和电路板116上的一个或多个焊盘114以形成对应的焊点，该焊点配置成进一步路由在封装衬底104和电路板116之间的电信号。用于将封装衬底104与电路板116物理和/或电耦合的其它合适的技术可用于其他实施例。在一些实施例(未描绘)中，IC封装108可例如，以与IC封装108与封装衬底104耦合相同的方式与电路板116耦合。在这种实施例中，可省略封装衬底104。
图2为根据本公开的一些实施例的集成电路封装制造过程的示例性流程图。图3为根据示例性实施例的示出了在IC封装衬底制造过程200中的阶段的所选择的操作的截面图。因此，图2和图3将彼此结合进行描述。为了有助于该描述，在图2中执行的操作参照从图3中的操作移动到操作的箭头。
过程200可开始于操作201，在操作201处，两个管芯(例如，图3的管芯304和306)可与载体(例如，图3的载体308)耦合。例如，管芯304和306可通过诸如粘合剂、树脂、或焊料之类的粘结材料(未描绘)与载体308耦合。粘合剂可以是任何类型的管芯粘结粘合剂，诸如环氧粘合剂。在一些实施例中，粘合剂可包括悬浮在粘合剂中的金属颗粒以提供导热性和/或导电性。例如，树脂可以为基于聚酰亚胺的树脂或热塑性塑料。焊料可包括，但不限于，铅(Pb)、金(Au)、银(Ag)、锡(Sn)、铟(In)、锑(Sb)、铋(Bi)、或它们的任意组合。在一些实施例中，将管芯粘结至载体的材料可被选择成比其他材料更容易使管芯完成从载体剥离。
在实施例中，载体308可以是配置成用作用于IC的散热器的金属载体。这种金属载体可基于材料的导热性选择并且可包括能够允许充分的热量远离管芯304和306转移的任何材料，以允许管芯304和306在施加电压时维持操作温度。例如，金属载体可至少部分地由铜或铜合金、铝或铝合金、AlSiC(具有碳化硅颗粒的铝基体)、钻石、铜-钨假合金、Dymalloy组成。在其他实施例中，载体308可由其膨胀系数选择，以降低或最小化工艺流程中的膨胀差异。在这种实施例中，载体308可以是，例如，玻璃或陶瓷载体。
在一些实施例中，管芯304或306可在其他管芯与载体308耦合之前与载体308耦合。在这种实施例中，第二管芯(例如，管芯306)可在相对于第一管芯(例如，管芯304)与载体耦合的位置的位置中与载体308耦合。管芯304和306可各表示由半导体材料制成的分立芯片。在一些实施例中，这种管芯304和306可包括以下部件，或作为以下部件的一部分：处理器、存储器、或ASIC。虽然仅描述两个管芯，但这仅为了清楚起见并且在不背离本公开的范围的情况下任何合适数量的管芯可与载体耦合。
在操作203中，桥(例如，图3的桥310)可附连至管芯304和306。在实施例中，桥310可包括配置成附连至管芯304和306并且将信号路由至管芯304和306并且从管芯304和306路由信号的电路由特征。电路由特征可配置成根据包括倒装芯片配置的各种合适的配置附连至管芯304和306。在倒装芯片配置中，桥310可利用管芯互连结构302附连至管芯304或306中的一个或两者，互连结构302在此处也称为输入/输出(I/O)互连结构，诸如凸块、柱、或也可将桥310与管芯304和306电耦合的其他合适的结构。在其中使用两个以上的管芯的实施例中，桥的电路由特征可被配置成除管芯304和306之外还附接至每个附加管芯并且将信号路由至每个附加管芯和从每个附加管芯路由信号。例如，在未描绘的一个示例配置中，桥310可附连至互连结构(诸如设置在四个管芯的转角上的互连结构302)，使得桥将四个管芯物理且电耦合在一起。
在一些实施例中，如参照图5和6进一步讨论的，桥310可具有设置在与如上讨论的路由特征相对的一侧上的附加路由特征。出于参考起见，这将是图3和4中描绘的桥310的正面。这些路由特征可配置成附连至一个或多个附加管芯(未描绘)并且将信号路由至一个或多个附加管芯并且从一个或多个附加管芯路由信号。此外，这些附加路由特征可配置成将信号路由至与这些附加路由特征相对的侧。例如，这些附加路由特征可配置成在一个或多个附加管芯和管芯304和/或306之间路由信号。桥310可由包括硅、玻璃、具有层压构建材料的加强有机物、和/或有机构建材料与玻璃或硅衬底的组合。在其中桥310可包括硅的实施例中，附加路由特征可以是硅通孔(TSV)。在其中桥310可包括玻璃的实施例中，这些附加路由特征可以是玻璃通孔(TSV)。此外，虽然此处描绘成对称的，但桥310不需要精确对称，并且在一些实施例中，桥的厚度可从一个管芯到下一管芯变化。该厚度的变化可以是有利的，例如，在其中管芯304和306具有不同厚度的实例中，不对称的桥仍可提供与管芯304和306相对的水平表面。
在实施例中，桥310可以是有源的或无源的。如本文所使用的有源桥可指的是具有集成在其中的逻辑的桥，以执行一个或多个逻辑功能。在一些实施例中，当信号被传输时，这些逻辑功能可修改、调节、或动态地路由信号。另一方面，无源桥可能不具有集成在其中的逻辑并且仅可提供信号的静态路由。在实施例中，例如，无源桥可包括无源器件，诸如电容器、电感器、电阻器、或它们的组合。在其中桥310为有源的实施例中，桥310可作为存储器控制器或其他类似的控制器进行操作。在一些实施例中，桥310可以是薄顺应桥(thin compliant bridge)，其可足够柔韧以当管芯可能不共面时进行补偿。
在操作205处，管芯304和306可与桥310一起被包封在电绝缘材料312(诸如，模制化合物(molding compound)或底部填充材料)中。在操作207处，可移除过度的电绝缘材料312。在一些实施例中，可移除所有过度的材料，从而展现桥的一侧。在例如其中桥具有与连接至管芯304和306的路由特征相对的附加路由特征的其他实施例中，可残存一些过度的材料，并且可在该材料中形成通孔以允许形成于附加路由特征的连接。
在操作209处，可在电绝缘材料312中形成通孔314以允许形成与附加管芯互连结构(例如，不与桥310耦合的结构)的连接。在所描述的一些实施例中，通孔可与桥310不共面。在一些实施例中，在操作211，载体308可从IC封装解耦，从而展现配置成具有附连至IC封装的散热器的平面侧。在其他实施例中，载体308可留下作为封装的一部分，例如，在其中载体308采取散热器的形式的情况下。
图4为根据本公开的一些实施例的集成电路(IC)封装的示例性截面图。如所描绘的，封装类似于通过图2中描绘的过程形成的图3的封装。在该实施例中，管芯互连结构不是非均匀长度，而是管芯具有桥互连结构404，桥互连结构404在不需要形成于电绝缘材料中的通孔的情况下与暴露在电绝缘材料的表面中的桥310和管芯互连结构402耦合。在此处所描绘的这种实施例中，管芯互连结构402可制造得更长以计及桥的厚度。在其他实施例中，桥互连结构404可以选择性地制造得很短(未描绘)以计及桥310的厚度。在又一实施例中，桥互连结构404可制造得很短并与管芯互连结构402的延长相结合以实现相同的效果。
图5为根据本公开的一些实施例的集成电路封装制造过程的示例性流程图。图6提供根据示例性实施例的示出了在IC封装衬底制造过程500中的阶段的所选择的操作的截面图。因此，图5和图6将彼此结合进行描述。为了有助于该描述，在图5中执行的操作参照从图6中的操作移动到操作的箭头。此外，在图6的每个操作中没有描绘所有附图标记。
过程500可开始于操作501，在操作501处，两个或两个以上管芯(例如，图6的管芯608和610)可与载体(例如，图6的载体612)耦合。例如，管芯608和610可通过诸如粘合剂、树脂、或焊料之类的粘结材料(未描绘)与载体612耦合。粘合剂可以是任何类型的管芯粘结粘合剂，诸如环氧粘合剂。在一些实施例中，粘合剂可包括悬浮在粘合剂中的金属颗粒以提供导热性和/或导电性。例如，树脂可以为基于聚酰亚胺的树脂或热塑性塑料。在使用焊料的实施例中，焊料可包括，例如，铅(Pb)、金(Au)、银(Ag)、锡(Sn)、或它们的任何组合。在一些实施例中，将管芯608、610粘结至载体612的材料可被选择成比其他材料更容易使管芯608、610完成从载体612剥离(debond)。
在实施例中，载体612可以是配置成用作用于IC封装的散热器的金属载体。这种金属载体可基于材料的导热性选择并且可包括能够允许充分的热量远离管芯转移的任何材料，以允许管芯在施加电压时维持操作温度。例如，金属载体可至少部分地由铜或铜合金、铝或铝合金、AlSiC(具有碳化硅颗粒的铝基体)、钻石、铜-钨假合金、Dymalloy组成。在其他实施例中，载体可由其膨胀系数选择，以降低或最小化工艺流程中的膨胀差异。在这种实施例中，载体可以是，例如，玻璃或陶瓷载体。
在一些实施例中，管芯608或610可在其他管芯与载体612耦合之前与载体612耦合。在这种实施例中，第二管芯(例如，管芯610)可在相对于第一管芯(例如，管芯608)与载体612耦合的位置的位置中与载体耦合。管芯608和610可各自表示由半导体材料制成的分立芯片。在一些实施例中，这种管芯608和610可包括以下部件，或作为以下部件的一部分：处理器、存储器、或ASIC。虽然仅描述两个管芯，但这仅为了清楚起见并且在不背离本公开的范围的情况下任何合适数量的管芯可与载体耦合。
如所描绘的，管芯608和610可具有多组输入/输出(I/O)互连结构。每个管芯可具有配置成与桥电且物理附连的桥互连结构606.每个管芯可进一步具有配置成与功率管理模块电且物理地附连的功率管理互连结构604。此外，每个管芯可具有配置成与封装衬底或电路板电耦合的管芯互连结构602。以下将更详细讨论这些组的I/O互连结构中的每一个。
在操作503中，桥(例如，图6的桥614)可附连至管芯608和610。桥614的电路由特征可配置成根据包括倒装芯片配置的各种合适的配置附连至管芯606和608的桥互连结构606。在倒装芯片配置中，桥614可经由多个互连结构(诸如，凸块、柱、或也可将桥614与管芯608和610电耦合的其他合适的结构)附连至管芯608或610中的一个或两者。在其中使用两个以上的管芯的实施例中，桥614的电路由特征可被配置成除路由至管芯608和610以及从管芯608和610路由的信号之外还附接至每个附加管芯并且将信号路由至每个附加管芯和从每个附加管芯路由信号。
在一些实施例中，桥614可具有设置在与以上讨论的路由特征相对的侧上的附加路由特征616。附加路由特征616可配置成附连至一个或多个附加管芯并且将信号路由至一个或多个附加管芯并且从一个或多个附加管芯路由信号。此外，附加路由特征616可配置成将信号路由至与附加路由特征相对的桥的一侧或从该侧路由信号。例如，附加路由特征616可配置成将一个或多个附加管芯之间的信号路由至管芯608和610。在一些实施例中，附加路由特征616可以为硅通孔(through silicon vias：TSV)。
在实施例中，桥614可以是有源的或无源的。如本文所使用的有源桥可指的是具有集成在其中的逻辑的桥，以执行一个或多个逻辑功能。在一些实施例中，这些逻辑功能可修改、调节信号、或当信号被传输时动态地路由信号。另一方面，无源桥可能不具有集成在其中的逻辑并且仅可提供任何信号的静态路由。在其中桥614为有源的实施例中，桥614可作为存储器控制器或其他类似的控制器进行操作。
在操作505处，附加路由特征616可以与一个或多个附加管芯618耦合。附加管芯618可包括有源或无源管芯，或它们的组合。在实施例中，附加管芯618可包括配置为存储器的一个或多个管芯。在这种实施例中，管芯618可形成存储器堆叠或存储器立方体。在如上所讨论的一些实施例中，桥614可包含逻辑以执行存储器控制器的功能。在其他实施例中，桥614可以为无源桥，并且附加管芯618中的一个可以为配置成作为存储器控制器进行操作的有源管芯。在操作507处，功率管理互连结构604可与配置成管理供应至管芯608和610的功率的功率管理模块620和622耦合。在一些实施例中，例如，功率管理模块620和622可包括被包含在模制材料中的一个或多个无源器件，诸如，电容器、电感器、电阻器、和它们的任何组合。
在操作509处，管芯608和610、桥614、附加管芯618和功率管理模块608和610可被包封在电绝缘材料626(诸如，模制化合物或底部填充材料)中。在其他实施例中，可利用构建层诸如通过无凸块构建层工艺实现包封。在这种实施例中，一个或多个金属特征624可嵌入在构建层中以在管芯608和610与表面水平封装互连结构628之间路由电信号。在一些实施例中，在操作511处，载体612可从IC封装解耦，从而展现配置成与散热器耦合的平面侧。在其他实施例中，载体612可留下作为封装的一部分，例如，在其中载体612采取散热器的形式的情况下。
图7为根据本公开的一些实施例的利用IC封装的组装工艺的示例性流程图。这种IC封装可通过以上参照图2或5中任一个描述的示例性方法生产并且可在图3、4或6中描绘。
组装过程700可开始于操作702，在操作702处，可接收在预定衬底连接点处具有暴露的表面精整层(exposed surface finish)的封装衬底。同样，在示例性实施例中，在将IC封装耦合至封装衬底之前，在封装衬底的表面上可能不存在阻焊剂，并且没有焊料位于表面精整层上。
在操作704处，IC封装可容纳有设置在封装连接点上的焊料凸块。在实施例中，IC封装可以是以上图3、4、或6中描绘的IC封装中的任一个。在操作706处，可将IC封装的连接点与衬底的连接点对齐。然后在操作708处，可IC封装焊料可被合铸成合金以将IC封装贴装至衬底连接点，从而可完成封装710。
可在使用任何合适硬件和/或软件按需配置的系统中实现本公开的实施例。图8示意性地示出了根据一些实施例的包括本文中所描述的IC封装(诸如通过图3、4、或6描绘的IC封装)的计算设备。计算设备800可容纳诸如母板802之类的板。母板802可包括多个部件，该多个部件包括，但不限于，处理器804和至少一个通信芯片806。处理器804可物理且电耦合至母板802。在一些实施例中，至少一个通信芯片806还可物理且电耦合至母板802。在进一步实现中，通信芯片806可以是处理器804的一部分。
根据其应用，计算设备800可包括可能或可能不物理且电耦合至母板802的其他部件。这些其它组件可包括但不限于易失性存储器(例如DRAM)、非易失性存储器(例如ROM)、闪存、图形处理器、数字信号处理器、加密处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码解码器、视频编码解码器、功率放大器、全球定位系统(GPS)装置、指南针、盖革计数器(Geiger counter)、加速度计、陀螺仪、扬声器、相机以及大容量存储装置(诸如硬盘驱动器、紧凑盘(CD)、数字多功能盘(DVD)等等)。
通信芯片806可实现无线通信以供将数据转移至计算设备800或转移来自计算设备800的数据。术语“无线”及其派生词可用于描述可通过使用通过非固态的介质的经调制的电磁辐射传播数据的电路、设备、系统、方法、技术、通信信道等等。术语不隐含相关联的设备不包含任何有线，虽然在一些实施例中它们可能不包括。通信芯片806可实现任何数量的无线标准或协议，无线标准或协议包括，但不限于，电子与电气工程师协会(IEEE)标准(包括Wi-Fi(IEEE802.11家族)、IEEE 802.16标准(例如，IEEE 802.16-2005修改))、长期演进(LTE)项目连同任何修改、更新和/或修订版本(例如，先进的LTE项目、超移动宽带(UMB)项目(也被称为“3GPP2)等等)。”可兼容BWA网络的IEEE 802.16一般被称为WiMAX网络，代表全球微波接入互操作性的首字母的缩写是用于通过针对IEEE802.16标准的整合和互操作性测试的产品的认证标志。通信芯片806可根据全球移动通信(GSM)系统、通用分组无线业务(GPRS)、通用移动电信系统(UMTS)、高速链路分组接入(HSPA)、演进的HSPA(E-HSPA)、或LTE网络操作。通信芯片806可根据用于GSM演进的增强型数据(EDGE)、GSM EDGE无线电接入网络(GERAN)、通用陆地无线接入网络(UTRAN)或演进的UTRAN(E-UTRAN)操作。通信芯片806可根据码分多址(CDMA)、时分多址(TDMA)、数字增强型无绳通信(DECT)、演进数据优化(EV-DO)、它们的衍生物、以及指定用于3G、4G、5G及以上的任何其他无线协议操作。在其他实施例中，通信芯片806可根据其他无线协议操作。
计算设备800可包括多个通信芯片806。例如，第一通信芯片806可专用于短距离无线通信(诸如，Wi-Fi和蓝牙)，以及第二通信芯片806可专用于长距离无线通信(诸如，GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等等)。
计算设备800的处理器804可以是包含在IC组件(例如，图1的IC组件100)中的IC封装(例如，IC封装108)。例如，图1的电路板116可以为母板802而处理器804可以为安装在本文中所描述的封装衬底104上的IC封装108。封装衬底104和母板802可利用本文所描述的封装级互连结构耦合在一起。术语“处理器”可表示任何设备或设备的一部分，其处理来自寄存器和/或存储器的电子数据，以将该电子数据转换成可存储于寄存器和/或存储器中的其它电子数据。
通信芯片806可以是包含在IC组件(例如，IC封装108)中的IC封装(例如，IC封装108)，IC组件包括封装衬底104。在进一步的实现中，容纳在计算设备800内的另一部件(例如，存储器设备或其他集成电路设备)可以是包含在IC组件(例如，图1的IC组件100)中的IC封装(例如，IC封装108)。
在多个实现中，计算设备800可以是膝上型计算机、上网本、笔记本电脑、超级本、智能电话、平板电脑、个人数字助理(PDA)、超移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字相机、便携式音乐播放器、或者数字录像机。在进一步实现中，计算设备800可以是处理数据的任何其他电子设备。
实施例
根据各个实施例，本公开描述了多个示例。示例1为集成电路封装，包括：分别具有多个第一和第二输入/输出互连结构的第一管芯和第二管芯；以及桥，其包括：电耦合至第一多个I/O互连结构的一部分的第一电路由特征；电耦合至第二多个I/O互连结构的一部分的第二电路由特征，第一和第二电路由特征设置在桥的第一侧上；以及设置在桥的与第一侧相对的第二侧上的第三电路由特征，其中第一电路由特征和第二电路由特征配置成在第一管芯和第二管芯之间路由电信号，而第三电路由特征在第二侧和第一侧之间路由电信号，并且其中第一管芯、第二管芯、和桥至少部分地嵌入在电绝缘材料中。
示例2可包括示例1的主题，其中桥进一步包括与第三电路由特征耦合并且配置成在第二侧和第一侧之间路由电信号的硅通孔(TSV)。
示例3可包括示例2的主题，进一步包括具有接合至第三电路由特征的第三多个I/O互连特征的第三管芯，其中第三管芯也嵌入在电绝缘材料中。
示例4可包括示例3的主题，其中第三管芯进一步包括配置成与第四管芯的I/O互连结构接合的第四多个I/O互连结构。
示例5可包括示例3的主题，其中桥为具有嵌入在其中的一个或多个逻辑特征的有源桥。
示例6可包括示例2的主题，进一步包括具有多个管芯的存储器管芯堆叠，其中存储器管芯堆叠经由第三电路由特征接合至桥，并且其中桥为配置成执行存储器控制器的一个或多个功能的有源桥，以及其中存储器管芯堆叠也嵌入在电绝缘材料中。
示例7可包括示例1-6中任一个的主题，进一步包括第一功率管理模块和第二功率管理模块，其中第一管芯和第二管芯进一步分别包括第一功率互连结构和第二功率互连结构，并且其中第一功率管理模块经由第一功率互连结构接合至第一管芯，以及第二功率管理模块经由第二功率互连结构接合至第二管芯，并且其中第一和第二功率管理模块也嵌入在电绝缘材料中。
示例8可包括示例1-6的任一个的主题，进一步包括与第一和第二多个输入/输出(I/O)互连结构耦合的多个通孔，其中通孔设置在电绝缘材料中并且与桥共面。
示例9可包括示例1-6中任一个的主题，其中电绝缘材料包括电绝缘材料的多个构建层，该电绝缘材料具有嵌入在其中并且配置成将I/O信号路由通过电绝缘材料的一个或多个金属特征。
示例10可包括示例1-6的任一个的主题，进一步包括分别与第一和第二管芯的第一和第二表面耦合的散热器，其中散热器形成集成电路封装的一侧。
示例11可包括示例1-6的任一个的主题，其中电绝缘材料和第一和第二管芯的第一和第二表面分别形成配置成与散热器集成的集成电路封装的平面表面。
示例12可包括示例1-6的任一个中的主题，其中第一或第二多个I/O互连结构中的一个或多个具有与电绝缘材料的表面共面的至少一个表面水平连接点，以允许集成电路封装物理连接且电连接至衬底或电路板中的一个。
示例13可包括示例12的主题，其中至少一个表面水平连接点为形成于电绝缘材料中的通孔结构。
示例14可包括示例12的主题，其中第一多个I/O互连结构的一部分和第二多个I/O互连结构的一部分比第一或第二多个I/O互连结构中的一个或多个短，使得第一和第二多个I/O互连结构具有与桥的表面和电绝缘材料的表面共面的接合表面。
示例15为组装集成电路封装的方法，包括：通过将设置在第一管芯上的第一多个输入/输出(I/O)互连结构的一部分接合至设置在桥上的第一多个电路由特征来将第一管芯耦合至桥；通过将设置在第二管芯上的第二多个I/O互连结构的一部分接合至设置在桥上的第二多个电路由特征来将第二管芯耦合至桥，其中多个第一和第二电路由特征设置在桥的第一侧上，并且其中桥具有设置在与第一侧相对的第二侧上的第三多个路由特征，第三多个路由特征配置成在第二侧和第一侧之间路由电信号；以及在第一管芯、第二管芯和桥上沉积电绝缘材料以至少部分地将第一管芯、第二管芯、和桥嵌入在电绝缘材料中。
示例16可包括示例15的主题，进一步包括在将第一管芯和第二管芯耦合至桥之前将第一管芯和第二管芯耦合至载体。
示例17可包括示例16的主题，其中载体为散热器。
示例18可包括示例15-17中的任一个的主题，进一步包括通过将管芯堆叠的第三多个I/O互连结构接合至设置在桥上的第三电路由特征来将管芯堆叠与桥耦合。
示例19可包括示例15-17中的任一个的主题，其中沉积电绝缘材料进一步包括执行无凸块构建层工艺以将金属特征嵌入在电绝缘材料中，金属特征被配置成将I/O信号路由通过电绝缘材料。
示例20可包括示例15-17中的任一个的主题，进一步包括在电绝缘材料的表面中激光钻通孔以展现第一多个I/O互连结构中的一个或多个或第二多个I/O互连结构中的一个或多个。
示例21为封装组件，包括：集成电路(IC)封装，包括：第一管芯和第二管芯，该第一管芯和第二管芯分别具有多个第一和第二输入/输出(I/O)互连结构；和桥，该桥包括第一电路由特征、第二电路由特征和第三电路由特征，第一电路由特征电耦合至第一多个I/O互连结构的一部分，第二电路由特征电耦合至第二多个I/O互连结构的一部分，第一和第二电路由特征设置在桥的第一侧上，以及第三电路由特征设置在与第一侧相对的第二侧上，其中第一电路由特征和第二电路由特征配置成在第一管芯和第二管芯之间路由电信号，以及第三电路由特征配置成至少部分地在第二侧和第一侧之间路由电信号，并且其中第一管芯、第二管芯、和桥至少部分地嵌入在电绝缘材料中；以及封装衬底，该封装衬底包括具有设置在其上的一个或多个焊盘的第一侧和与第一侧相对设置的第二侧，第二侧具有设置在其上的一个或多个电路由特征，电路由特征与第一多个I/O互连结构和第二多个I/O互连结构电耦合。
示例22可包括示例21的主题，其中IC封装为处理器。
示例23可包括示例22的主题，进一步包括与电路板耦合的天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)装置、指南针、盖革计数器、加速度计、陀螺仪、扬声器，或相机中的一个或多个，其中封装组件是膝上型计算机、上网本、笔记本电脑、超级本电脑、智能电话、平板电脑、个人数字助理(PDA)、超移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字相机、便携式音乐播放器，或者数字录像机的一部分。
示例24为用于组装集成电路封装的装置，包括：用于通过将设置在第一管芯上的多个第一输入/输出(I/O)互连结构的一部分接合至设置在桥上的第一多个电路由特征来将第一管芯耦合至桥的装置；用于通过将设置在第二管芯上的第二多个I/O互连结构的一部分接合至设置在桥上的第二多个电路由特征来将第二管芯耦合至桥的装置，其中第一和第二多个电路由特征设置在桥的第一侧上，并且其中桥具有设置在与第一侧相对的第二侧上的第三多个路由特征，多个第三路由特征配置成在第二侧和第一侧之间路由电信号；以及用于在第一管芯、第二管芯和桥上沉积电绝缘材料以至少部分地将第一管芯、第二管芯、和桥嵌入在电绝缘材料中的装置。
示例25可包括示例24的主题，进一步包括用于在将第一管芯和第二管芯耦合至桥之前将第一管芯和第二管芯耦合至载体的装置。
示例26可包括示例25的主题，其中载体为散热器。
示例27可包括示例24-26中的任一个的主题，进一步包括用于通过将管芯堆叠的第三多个I/O互连结构接合至设置在桥上的第三电路由特征来将管芯堆叠与桥耦合的装置。
示例28可包括示例24-26中的任一个的主题，其中用于沉积电绝缘材料的装置进一步包括用于执行无凸块构建层工艺以将金属特征嵌入在电绝缘材料中的装置，金属特征被配置成将I/O信号路由通过电绝缘材料。
示例29可包括示例24-26中的任一个的主题，进一步包括用于在电绝缘材料的表面中激光钻通孔以展现第一多个I/O互连结构中的一个或多个或第二多个I/O互连结构中的一个或多个的装置。
各个实施例可包括上述实施例的任何合适的组合，其包括以上以联合形式(和)描述的实施例的替代(或)实施例的(例如“和”可以是“和/或”)。此外，一些实施例可包括具有存储在其上的指令的产品的一个或多个制品(非瞬态计算机可读介质)，这些指令在被执行时产生以上描述的实施例中的任何一个动作。此外，一些实施例可包括具有用于执行以上实施例的各种操作的任何合适装置的装置或系统。
所示的实现的上述描述、包括摘要中的描述的不旨在穷举或将本公开的实施例限制为所公开的精确形式。虽然为了说明目的在本文中描述了特定实现和示例，但如相关领域技术人员将认识到的，在本发明的范围内有许多等效修改是可能的。
鉴于以上详细描述，可对本公开的实施例进行这些修改。下面权利要求中使用的术语不应当解释成将本公开的各个实施例限定于说明书和权利要求书所公开的特定实现。相反，本发明的范围完全由所附权利要求确定，所附权利要求将根据已确立的权利要求解释原则来解读。

Claims (25)

1.一种集成电路封装，包括：
分别具有第一和第二多个输入/输出(I/O)互连结构的第一管芯和第二管芯；以及
桥，其包括：
第一电路由特征，所述第一电路由特征电耦合至第一多个I/O互连结构的一部分；
第二电路由特征，所述第二电路由特征电耦合至第二多个I/O互连结构的一部分，所述第一和第二电路由特征设置在所述桥的第一侧上；以及
第三电路由特征，所述第三电路由特征设置在所述桥的与所述第一侧相对的第二侧上，其中所述第一电路由特征和所述第二电路由特征被配置成在所述第一管芯和第二管芯之间路由电信号，以及所述第三电路由特征被配置成在所述第二侧和第一侧之间路由电信号，并且其中所述第一管芯、所述第二管芯、和所述桥至少部分地嵌入在电绝缘材料中。
2.如权利要求1所述的集成电路封装，其特征在于，所述桥进一步包括与所述第三电路由特征耦合并且被配置成在所述第二侧和第一侧之间路由电信号的硅通孔(TSV)。
3.如权利要求2所述的集成电路封装，其特征在于，进一步包括具有接合至所述第三电路由特征的第三多个I/O互连特征的第三管芯，其中所述第三管芯也嵌入在电绝缘材料中。
4.如权利要求2所述的集成电路封装，其特征在于，所述第三管芯进一步包括配置成与第四管芯的I/O互连结构接合的第四多个I/O互连结构。
5.如权利要求3所述的集成电路封装，其特征在于，所述桥为具有嵌入在其中的一个或多个逻辑特征的有源桥。
6.如权利要求2所述的集成电路封装，其特征在于，进一步包括具有多个管芯的存储器管芯堆叠，其中所述存储器管芯堆叠经由所述第三电路由特征接合至所述桥，并且其中所述桥为配置成执行存储器控制器的一个或多个功能的有源桥，以及其中所述存储器管芯堆叠也嵌入在电绝缘材料中。
7.如权利要求1-6中的任一项所述的集成电路封装，其特征在于，进一步包括第一功率管理模块和第二功率管理模块，其中所述第一管芯和第二管芯进一步分别包括第一功率互连结构和第二功率互连结构，并且其中所述第一功率管理模块经由所述第一功率互连结构接合至所述第一管芯，而所述第二功率管理模块经由所述第二功率互连结构接合至所述第二管芯，并且其中第一和第二功率管理模块也嵌入在电绝缘材料中。
8.如权利要求1-6中的任一项所述的集成电路封装，其特征在于，进一步包括与所述第一和第二多个输入/输出(I/O)互连结构耦合的多个通孔，其中所述通孔设置在电绝缘材料中并且与所述桥共面。
9.如权利要求1-6中的任一项所述的集成电路封装，其特征在于，所述电绝缘材料包括电绝缘材料的多个构建层，所述电绝缘材料具有嵌入在其中并且配置成将I/O信号路由通过所述电绝缘材料的一个或多个金属特征。
10.如权利要求1-6中的任一项所述的集成电路封装，其特征在于，进一步包括分别与第一和第二管芯的第一和第二表面耦合的散热器，其中所述散热器形成集成电路封装的一侧。
11.如权利要求1-6中的任一项所述的集成电路封装，其特征在于，所述电绝缘材料以及第一和第二管芯的第一和第二表面分别形成配置成与散热器集成的集成电路封装的平坦表面。
12.如权利要求1-6中的任一项所述的集成电路封装，其特征在于，所述第一或第二多个I/O互连结构中的一个或多个具有与电绝缘材料的表面共面的至少一个表面水平连接点，以允许所述集成电路封装物理连接且电连接至衬底或电路板中的一个。
13.如权利要求12所述的集成电路封装，其特征在于，所述至少一个表面水平连接点为形成于电绝缘材料中的通孔结构。
14.如权利要求12所述的集成电路封装，其特征在于，所述第一多个I/O互连结构的一部分和所述第二多个I/O互连结构的一部分比所述第一或第二多个I/O互连结构中的一个或多个短，使得所述第一和第二多个I/O互连结构具有与桥的表面和电绝缘材料的表面共面的接合表面。
15.一种组装集成电路封装的方法，包括：
通过将设置在第一管芯上的第一多个输入/输出(I/O)互连结构的一部分接合至设置在桥上的第一多个电路由特征来将第一管芯耦合至所述桥；
通过将设置在第二管芯上的第二多个I/O互连结构的一部分接合至设置在所述桥上的第二多个电路由特征来将第二管芯耦合至桥，其中所述第一和第二多个电路由特征设置在所述桥的第一侧上，并且其中所述桥具有设置在与第一侧相对的第二侧上的第三多个路由特征，所述第三多个路由特征被配置成在所述第二侧和第一侧之间路由电信号；以及
在所述第一管芯、第二管芯和所述桥上沉积电绝缘材料以至少部分地将所述第一管芯、所述第二管芯、和所述桥嵌入在电绝缘材料中。
16.如权利要求15所述的方法，其特征在于，进一步包括在将所述第一管芯和第二管芯耦合至所述桥之前将所述第一管芯和第二管芯耦合至载体。
17.如权利要求16所述的方法，其特征在于，所述载体为散热器。
18.如权利要求15-17中的任一项所述的方法，其特征在于，进一步包括通过将管芯堆叠的第三多个I/O互连结构接合至设置在所述桥上的第三电路由特征来将所述管芯堆叠与所述桥耦合。
19.如权利要求15-17中的任一项所述的方法，其特征在于，沉积电绝缘材料进一步包括执行无凸块构建层工艺以将金属特征嵌入在电绝缘材料中，所述金属特征被配置成将I/O信号路由通过所述电绝缘材料。
20.如权利要求15-17中的任一项所述的方法，其特征在于，进一步包括在所述电绝缘材料的表面中激光钻通孔以展现所述第一多个I/O互连结构中的一个或多个或所述第二多个I/O互连结构中的一个或多个。
21.一种封装组件，包括：
集成电路(IC)封装，包括：
第一管芯和第二管芯，所述第一管芯和第二管芯分别具有第一和第二多个输入/输出(I/O)互连结构；
以及桥，所述桥包括电耦合至所述第一多个I/O互连结构的一部分的第一电路由特征；电耦合至所述第二多个I/O互连结构的一部分的第二电路由特征，第一和第二电路由特征设置在所述桥的第一侧上；以及设置在与所述第一侧相对的第二侧上的第三电路由特征，其中所述第一电路由特征和第二电路由特征配置成在所述第一管芯和第二管芯之间路由电信号，而所述第三电路由特征配置成至少部分地在所述第二侧和第一侧之间路由电信号，并且其中所述第一管芯、所述第二管芯、和所述桥至少部分地嵌入在所述电绝缘材料中；以及
封装衬底，所述封装衬底包括具有设置在其上的一个或多个焊盘的第一侧；以及与第一侧相对设置的第二侧，所述第二侧具有设置在其上的一个或多个电路由特征，所述电路由特征与所述第一多个I/O互连结构和所述第二多个I/O互连结构电耦合。
22.如权利要求21所述的封装组件，其特征在于，所述IC封装为处理器。
23.如权利要求22所述的封装组件，其特征在于，进一步包括与电路板耦合的天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)装置、指南针、盖革计数器、加速度计、陀螺仪、扬声器，或相机中的一个或多个，其中所述封装组件是膝上型计算机、上网本、笔记本电脑、超级本电脑、智能电话、平板电脑、个人数字助理(PDA)、超移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字相机、便携式音乐播放器，或者数字录像机的一部分。
24.一种用于组装集成电路封装的设备，包括：
用于通过将设置在第一管芯上的第一多个输入/输出(I/O)互连结构的一部分接合至设置在桥上的第一多个电路由特征来将第一管芯耦合至所述桥的装置；
用于通过将设置在第二管芯上的第二多个I/O互连结构的一部分接合至设置在桥上的第二多个电路由特征来将第二管芯耦合至所述桥的装置，其中所述第一和第二多个电路由特征设置在桥的第一侧上，并且其中所述桥具有设置在与第一侧相对的第二侧上的第三多个路由特征，所述第三多个路由特征配置成在所述第二侧和第一侧之间路由电信号；以及
用于在所述第一管芯、所述第二管芯和所述桥上沉积电绝缘材料以至少部分地将所述第一管芯、所述第二管芯、和所述桥嵌入在电绝缘材料中的装置。
25.如权利要求24所述的设备，其特征在于，进一步包括用于通过将管芯堆叠的第三多个I/O互连结构接合至设置在所述桥上的第三电路由特征来将所述管芯堆叠与所述桥耦合的装置。
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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108028225A (zh) * 2015-09-17 2018-05-11 德卡技术股份有限公司 热增强型全模制扇出模组
CN108255761A (zh) * 2016-12-28 2018-07-06 英特尔公司 集成电路管芯之间的接口桥
CN109087908A (zh) * 2015-12-31 2018-12-25 华为技术有限公司 封装结构、电子设备及封装方法
CN109983575A (zh) * 2016-12-22 2019-07-05 英特尔公司 高带宽低轮廓多管芯封装
CN110176445A (zh) * 2016-01-27 2019-08-27 艾马克科技公司 电子装置
CN110660683A (zh) * 2018-06-29 2020-01-07 台湾积体电路制造股份有限公司 支撑info封装件以减小翘曲
CN111033731A (zh) * 2017-08-11 2020-04-17 超威半导体公司 模制芯片组合
US10897812B2 (en) 2018-12-25 2021-01-19 AT&S (Chongqing) Company Limited Component carrier having a component shielding and method of manufacturing the same
CN112435981A (zh) * 2020-09-30 2021-03-02 日月光半导体制造股份有限公司 半导体封装装置及其制造方法
US11088080B2 (en) 2019-09-05 2021-08-10 Powertech Technology Inc. Chip package structure using silicon interposer as interconnection bridge
CN113594150A (zh) * 2020-04-30 2021-11-02 台湾积体电路制造股份有限公司 Ic封装件及其形成方法以及在ic封装件中分配电源的方法
CN114094419A (zh) * 2020-07-16 2022-02-25 佳能株式会社 用于将两个电路单元电互连的中间连接构件

Families Citing this family (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9508636B2 (en) 2013-10-16 2016-11-29 Intel Corporation Integrated circuit package substrate
US9713255B2 (en) 2014-02-19 2017-07-18 Intel Corporation Electro-magnetic interference (EMI) shielding techniques and configurations
CN106133905B (zh) * 2014-04-25 2019-10-15 英特尔公司 集成电路封装衬底
US20150364422A1 (en) * 2014-06-13 2015-12-17 Apple Inc. Fan out wafer level package using silicon bridge
US9385110B2 (en) 2014-06-18 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9666559B2 (en) 2014-09-05 2017-05-30 Invensas Corporation Multichip modules and methods of fabrication
US10026672B1 (en) * 2015-10-21 2018-07-17 Hrl Laboratories, Llc Recursive metal embedded chip assembly
US10163856B2 (en) * 2015-10-30 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuit structure and method of forming
WO2017111790A1 (en) 2015-12-23 2017-06-29 Manusharow Mathew J Improving size and efficiency of dies
US10497674B2 (en) 2016-01-27 2019-12-03 Amkor Technology, Inc. Semiconductor package and fabricating method thereof
US9761559B1 (en) * 2016-04-21 2017-09-12 Micron Technology, Inc. Semiconductor package and fabrication method thereof
US9742445B1 (en) * 2016-07-01 2017-08-22 Bae Systems Information And Electronic Systems Integration Inc. High power radio frequency amplifier architecture
WO2018009145A1 (en) * 2016-07-08 2018-01-11 Agency For Science, Technology And Research A semiconductor package and methods of forming the same
US9871020B1 (en) * 2016-07-14 2018-01-16 Globalfoundries Inc. Through silicon via sharing in a 3D integrated circuit
CN109661725B (zh) * 2016-09-26 2023-07-07 英特尔公司 具有嵌入式通信腔体的管芯
US10672744B2 (en) * 2016-10-07 2020-06-02 Xcelsis Corporation 3D compute circuit with high density Z-axis interconnects
US10672745B2 (en) 2016-10-07 2020-06-02 Xcelsis Corporation 3D processor
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
US10672663B2 (en) 2016-10-07 2020-06-02 Xcelsis Corporation 3D chip sharing power circuit
US10600780B2 (en) 2016-10-07 2020-03-24 Xcelsis Corporation 3D chip sharing data bus circuit
US10586786B2 (en) 2016-10-07 2020-03-10 Xcelsis Corporation 3D chip sharing clock interconnect layer
US10580757B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Face-to-face mounted IC dies with orthogonal top interconnect layers
KR102512017B1 (ko) 2016-10-07 2023-03-17 엑셀시스 코포레이션 직접-접합된 네이티브 상호접속부 및 능동 베이스 다이
US10600735B2 (en) 2016-10-07 2020-03-24 Xcelsis Corporation 3D chip sharing data bus
US10600691B2 (en) 2016-10-07 2020-03-24 Xcelsis Corporation 3D chip sharing power interconnect layer
US10607136B2 (en) 2017-08-03 2020-03-31 Xcelsis Corporation Time borrowing between layers of a three dimensional chip stack
US10593667B2 (en) 2016-10-07 2020-03-17 Xcelsis Corporation 3D chip with shielded clock lines
US10672743B2 (en) * 2016-10-07 2020-06-02 Xcelsis Corporation 3D Compute circuit with high density z-axis interconnects
US11276667B2 (en) * 2016-12-31 2022-03-15 Intel Corporation Heat removal between top and bottom die interface
CN110383419B (zh) * 2017-02-27 2023-09-26 诺威有限公司 用于电测试预测的装置和方法
WO2018174869A1 (en) * 2017-03-22 2018-09-27 Intel Corporation Multiple die package using an embedded bridge connecting dies
US11430740B2 (en) 2017-03-29 2022-08-30 Intel Corporation Microelectronic device with embedded die substrate on interposer
WO2018182595A1 (en) 2017-03-29 2018-10-04 Intel Corporation Embedded die microelectronic device with molded component
JP6858642B2 (ja) * 2017-05-25 2021-04-14 三菱電機株式会社 パワーモジュール
US10943869B2 (en) 2017-06-09 2021-03-09 Apple Inc. High density interconnection using fanout interposer chiplet
US10622311B2 (en) * 2017-08-10 2020-04-14 International Business Machines Corporation High-density interconnecting adhesive tape
WO2019054998A1 (en) * 2017-09-13 2019-03-21 Intel Corporation ACTIVE SILICON BRIDGE
US11177201B2 (en) * 2017-11-15 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages including routing dies and methods of forming same
US10651126B2 (en) * 2017-12-08 2020-05-12 Applied Materials, Inc. Methods and apparatus for wafer-level die bridge
US11862619B2 (en) 2017-12-29 2024-01-02 Intel Corporation Patch accommodating embedded dies having different thicknesses
US11508663B2 (en) * 2018-02-02 2022-11-22 Marvell Israel (M.I.S.L) Ltd. PCB module on package
US10580738B2 (en) 2018-03-20 2020-03-03 International Business Machines Corporation Direct bonded heterogeneous integration packaging structures
US10796999B2 (en) * 2018-03-30 2020-10-06 Intel Corporation Floating-bridge interconnects and methods of assembling same
US10431563B1 (en) * 2018-04-09 2019-10-01 International Business Machines Corporation Carrier and integrated memory
US10742217B2 (en) 2018-04-12 2020-08-11 Apple Inc. Systems and methods for implementing a scalable system
US10593628B2 (en) 2018-04-24 2020-03-17 Advanced Micro Devices, Inc. Molded die last chip combination
US11251171B2 (en) * 2018-06-13 2022-02-15 Intel Corporation Removable interposer
US10535608B1 (en) * 2018-07-24 2020-01-14 International Business Machines Corporation Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate
US10672712B2 (en) 2018-07-30 2020-06-02 Advanced Micro Devices, Inc. Multi-RDL structure packages and methods of fabricating the same
KR102509052B1 (ko) * 2018-08-31 2023-03-10 에스케이하이닉스 주식회사 브리지 다이를 포함하는 스택 패키지
KR102163059B1 (ko) 2018-09-07 2020-10-08 삼성전기주식회사 연결구조체 내장기판
US11114308B2 (en) 2018-09-25 2021-09-07 International Business Machines Corporation Controlling of height of high-density interconnection structure on substrate
KR102615197B1 (ko) 2018-11-23 2023-12-18 삼성전자주식회사 반도체 패키지
US11289424B2 (en) * 2018-11-29 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Package and method of manufacturing the same
KR102538704B1 (ko) * 2018-12-04 2023-06-01 에스케이하이닉스 주식회사 플렉시블 브리지 다이를 포함한 스택 패키지
US11676941B2 (en) 2018-12-07 2023-06-13 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor package and fabricating method thereof
TWI815521B (zh) * 2018-12-07 2023-09-11 美商艾馬克科技公司 半導體封裝和其製造方法
US11488906B2 (en) 2019-01-24 2022-11-01 Samsung Electro-Mechanics Co., Ltd. Bridge embedded interposer, and package substrate and semiconductor package comprising the same
US11769735B2 (en) * 2019-02-12 2023-09-26 Intel Corporation Chiplet first architecture for die tiling applications
US11552019B2 (en) * 2019-03-12 2023-01-10 Intel Corporation Substrate patch reconstitution options
CN114144875A (zh) 2019-06-10 2022-03-04 马维尔以色列(M.I.S.L.)有限公司 具有顶侧存储器模块的ic封装
US11735533B2 (en) 2019-06-11 2023-08-22 Intel Corporation Heterogeneous nested interposer package for IC chips
US11133256B2 (en) * 2019-06-20 2021-09-28 Intel Corporation Embedded bridge substrate having an integral device
US10923430B2 (en) 2019-06-30 2021-02-16 Advanced Micro Devices, Inc. High density cross link die with polymer routing layer
US11694959B2 (en) * 2019-07-29 2023-07-04 Intel Corporation Multi-die ultrafine pitch patch architecture and method of making
US11854984B2 (en) * 2019-09-25 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US11393759B2 (en) 2019-10-04 2022-07-19 International Business Machines Corporation Alignment carrier for interconnect bridge assembly
US11164817B2 (en) 2019-11-01 2021-11-02 International Business Machines Corporation Multi-chip package structures with discrete redistribution layers
US11094637B2 (en) 2019-11-06 2021-08-17 International Business Machines Corporation Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers
US11599299B2 (en) 2019-11-19 2023-03-07 Invensas Llc 3D memory circuit
US11239167B2 (en) 2019-12-04 2022-02-01 International Business Machines Corporation Cu—Cu bonding for interconnects on bridge chip attached to chips and packaging substrate
US11171006B2 (en) 2019-12-04 2021-11-09 International Business Machines Corporation Simultaneous plating of varying size features on semiconductor substrate
US11430764B2 (en) * 2019-12-20 2022-08-30 Intel Corporation Overhang bridge interconnect
US11616026B2 (en) * 2020-01-17 2023-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11302643B2 (en) 2020-03-25 2022-04-12 Intel Corporation Microelectronic component having molded regions with through-mold vias
US11233009B2 (en) 2020-03-27 2022-01-25 Intel Corporation Embedded multi-die interconnect bridge having a molded region with through-mold vias
CN115699326A (zh) 2020-04-03 2023-02-03 沃孚半导体公司 具有源极、栅极和/或漏极导电通孔的基于iii族氮化物的射频晶体管放大器
JP2023520029A (ja) 2020-04-03 2023-05-15 ウルフスピード インコーポレイテッド 裏面ソース端子、ゲート端子及び／又はドレイン端子を有するｉｉｉ族窒化物ベースの高周波増幅器
EP4128344A1 (en) * 2020-04-03 2023-02-08 Wolfspeed, Inc. Rf amplifier package
CN111883513A (zh) * 2020-06-19 2020-11-03 北京百度网讯科技有限公司 芯片封装结构及电子设备
US20220189850A1 (en) * 2020-12-15 2022-06-16 Intel Corporation Inter-component material in microelectronic assemblies having direct bonding
US20220199537A1 (en) * 2020-12-18 2022-06-23 Intel Corporation Power-forwarding bridge for inter-chip data signal transfer
US20220199480A1 (en) * 2020-12-21 2022-06-23 Intel Corporation Microelectronic structures including bridges
US20220344250A1 (en) * 2021-04-22 2022-10-27 Qualcomm Incorporated Integrated circuit (ic) packages employing a capacitor-embedded, redistribution layer (rdl) substrate for interfacing an ic chip(s) to a package substrate, and related methods

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1835229A (zh) * 2005-03-16 2006-09-20 索尼株式会社 半导体器件和制造半导体器件的方法
US20090089466A1 (en) * 2007-09-28 2009-04-02 Sun Microsystems, Inc. Proximity communication package for processor, cache and memory
CN101960589A (zh) * 2008-03-31 2011-01-26 英特尔公司 包含用于高密度互连的硅贴片的微电子封装及其制造方法
CN102077344A (zh) * 2008-06-30 2011-05-25 高通股份有限公司 穿硅通孔桥接互连件
CN102148206A (zh) * 2010-03-29 2011-08-10 日月光半导体制造股份有限公司 半导体装置封装件及其制造方法
CN102460690A (zh) * 2009-06-24 2012-05-16 英特尔公司 多芯片封装和在其中提供管芯到管芯互连的方法
CN103187396A (zh) * 2011-12-28 2013-07-03 美国博通公司 具有无半导体通孔的超薄中介片的半导体封装件
CN103187377A (zh) * 2011-12-28 2013-07-03 美国博通公司 具有桥型中介片的半导体封装
CN203103293U (zh) * 2012-05-31 2013-07-31 美国博通公司 半导体封装
US8519543B1 (en) * 2012-07-17 2013-08-27 Futurewei Technologies, Inc. Large sized silicon interposers overcoming the reticle area limitations
CN103378017A (zh) * 2012-04-24 2013-10-30 辉达公司 高密度3d封装

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5847998A (en) * 1996-12-20 1998-12-08 Advanced Micro Devices, Inc. Non-volatile memory array that enables simultaneous read and write operations
JP2003008228A (ja) 2001-06-22 2003-01-10 Ibiden Co Ltd 多層プリント配線板およびその製造方法
US6856009B2 (en) 2003-03-11 2005-02-15 Micron Technology, Inc. Techniques for packaging multiple device components
US6972152B2 (en) 2003-06-27 2005-12-06 Intel Corporation Use of direct gold surface finish on a copper wire-bond substrate, methods of making same, and methods of testing same
JP2005163153A (ja) 2003-12-05 2005-06-23 Japan Pure Chemical Co Ltd 無電解ニッケル置換金めっき処理層、無電解ニッケルめっき液、および無電解ニッケル置換金めっき処理方法
JP4537084B2 (ja) 2004-01-29 2010-09-01 日本特殊陶業株式会社 配線基板の製造方法
US20060220167A1 (en) * 2005-03-31 2006-10-05 Intel Corporation IC package with prefabricated film capacitor
US7671449B2 (en) * 2005-05-04 2010-03-02 Sun Microsystems, Inc. Structures and methods for an application of a flexible bridge
US20070023910A1 (en) 2005-07-29 2007-02-01 Texas Instruments Incorporated Dual BGA alloy structure for improved board-level reliability performance
JP2007123524A (ja) 2005-10-27 2007-05-17 Shinko Electric Ind Co Ltd 電子部品内蔵基板
TW200746964A (en) 2006-01-27 2007-12-16 Ibiden Co Ltd Method of manufacturing printed wiring board
TWI315658B (en) 2007-03-02 2009-10-01 Phoenix Prec Technology Corp Warp-proof circuit board structure
US8892804B2 (en) * 2008-10-03 2014-11-18 Advanced Micro Devices, Inc. Internal BUS bridge architecture and method in multi-processor systems
TW201034269A (en) 2009-03-13 2010-09-16 Nat Univ Tsing Hua Organic thin film transistor which contains azole complex to dielectric insulating layer
TW201041469A (en) 2009-05-12 2010-11-16 Phoenix Prec Technology Corp Coreless packaging substrate, carrier thereof, and method for manufacturing the same
TW201041105A (en) 2009-05-13 2010-11-16 Advanced Semiconductor Eng Substrate having single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package
CN101930956B (zh) 2009-06-22 2013-09-25 日月光半导体制造股份有限公司 芯片封装结构及其制造方法
JP5635247B2 (ja) 2009-08-20 2014-12-03 富士通株式会社 マルチチップモジュール
JP2011044654A (ja) 2009-08-24 2011-03-03 Shinko Electric Ind Co Ltd 半導体装置
US9024431B2 (en) 2009-10-29 2015-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die contact structure and method
US8461036B2 (en) 2009-12-22 2013-06-11 Intel Corporation Multiple surface finishes for microelectronic package substrates
US8127979B1 (en) 2010-09-25 2012-03-06 Intel Corporation Electrolytic depositon and via filling in coreless substrate processing
US8703534B2 (en) 2011-01-30 2014-04-22 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
US8878354B1 (en) * 2011-05-31 2014-11-04 Marvell World Trade Ltd. Method and apparatus for supplying power to a system on a chip (SOC)
ITMI20111213A1 (it) * 2011-06-30 2012-12-31 St Microelectronics Srl Dispositivo elettronico a semi-ponte con dissipatore di calore ausiliario comune
JP2013105908A (ja) 2011-11-14 2013-05-30 Ngk Spark Plug Co Ltd 配線基板
WO2013095405A1 (en) 2011-12-20 2013-06-27 Intel Corporation Enabling package-on-package (pop) pad surface finishes on bumpless build-up layer (bbul) package
JP2013138115A (ja) 2011-12-28 2013-07-11 Kinko Denshi Kofun Yugenkoshi 支持体を有するパッケージ基板及びその製造方法、並びに支持体を有するパッケージ構造及びその製造方法
KR20130112084A (ko) 2012-04-03 2013-10-14 아페리오(주) 패키지기판 제조방법
US9136236B2 (en) 2012-09-28 2015-09-15 Intel Corporation Localized high density substrate routing
KR20140067727A (ko) 2012-11-27 2014-06-05 삼성전자주식회사 멀티칩 패키지 및 이의 제조 방법
US9250406B2 (en) * 2012-12-20 2016-02-02 Intel Corporation Electro-optical assembly including a glass bridge
US20140189227A1 (en) 2012-12-28 2014-07-03 Samsung Electronics Co., Ltd. Memory device and a memory module having the same
US9633872B2 (en) 2013-01-29 2017-04-25 Altera Corporation Integrated circuit package with active interposer
US9832883B2 (en) 2013-04-25 2017-11-28 Intel Corporation Integrated circuit package substrate
US9508636B2 (en) 2013-10-16 2016-11-29 Intel Corporation Integrated circuit package substrate
US9642259B2 (en) * 2013-10-30 2017-05-02 Qualcomm Incorporated Embedded bridge structure in a substrate

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1835229A (zh) * 2005-03-16 2006-09-20 索尼株式会社 半导体器件和制造半导体器件的方法
US20090089466A1 (en) * 2007-09-28 2009-04-02 Sun Microsystems, Inc. Proximity communication package for processor, cache and memory
CN101960589A (zh) * 2008-03-31 2011-01-26 英特尔公司 包含用于高密度互连的硅贴片的微电子封装及其制造方法
CN102077344A (zh) * 2008-06-30 2011-05-25 高通股份有限公司 穿硅通孔桥接互连件
CN102460690A (zh) * 2009-06-24 2012-05-16 英特尔公司 多芯片封装和在其中提供管芯到管芯互连的方法
CN102148206A (zh) * 2010-03-29 2011-08-10 日月光半导体制造股份有限公司 半导体装置封装件及其制造方法
CN103187396A (zh) * 2011-12-28 2013-07-03 美国博通公司 具有无半导体通孔的超薄中介片的半导体封装件
CN103187377A (zh) * 2011-12-28 2013-07-03 美国博通公司 具有桥型中介片的半导体封装
CN103378017A (zh) * 2012-04-24 2013-10-30 辉达公司 高密度3d封装
CN203103293U (zh) * 2012-05-31 2013-07-31 美国博通公司 半导体封装
US8519543B1 (en) * 2012-07-17 2013-08-27 Futurewei Technologies, Inc. Large sized silicon interposers overcoming the reticle area limitations

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108028225B (zh) * 2015-09-17 2022-06-07 美国德卡科技公司 热增强型全模制扇出模组
CN108028225A (zh) * 2015-09-17 2018-05-11 德卡技术股份有限公司 热增强型全模制扇出模组
CN109087908B (zh) * 2015-12-31 2020-10-27 华为技术有限公司 封装结构、电子设备及封装方法
CN109087908A (zh) * 2015-12-31 2018-12-25 华为技术有限公司 封装结构、电子设备及封装方法
CN110176445B (zh) * 2016-01-27 2023-09-01 艾马克科技公司 电子装置
CN110176445A (zh) * 2016-01-27 2019-08-27 艾马克科技公司 电子装置
CN109983575B (zh) * 2016-12-22 2024-02-27 英特尔公司 高带宽低轮廓多管芯封装
CN109983575A (zh) * 2016-12-22 2019-07-05 英特尔公司 高带宽低轮廓多管芯封装
CN108255761B (zh) * 2016-12-28 2023-09-26 英特尔公司 集成电路管芯之间的接口桥
US11693810B2 (en) 2016-12-28 2023-07-04 Intel Corporation Interface bridge between integrated circuit die
CN108255761A (zh) * 2016-12-28 2018-07-06 英特尔公司 集成电路管芯之间的接口桥
CN111033731A (zh) * 2017-08-11 2020-04-17 超威半导体公司 模制芯片组合
CN111033731B (zh) * 2017-08-11 2021-09-28 超威半导体公司 模制芯片组合
CN110660683B (zh) * 2018-06-29 2021-10-29 台湾积体电路制造股份有限公司 支撑info封装件以减小翘曲
CN110660683A (zh) * 2018-06-29 2020-01-07 台湾积体电路制造股份有限公司 支撑info封装件以减小翘曲
US10886238B2 (en) 2018-06-29 2021-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Supporting InFO packages to reduce warpage
US11764165B2 (en) 2018-06-29 2023-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Supporting InFO packages to reduce warpage
US10897812B2 (en) 2018-12-25 2021-01-19 AT&S (Chongqing) Company Limited Component carrier having a component shielding and method of manufacturing the same
US11088080B2 (en) 2019-09-05 2021-08-10 Powertech Technology Inc. Chip package structure using silicon interposer as interconnection bridge
CN113594150A (zh) * 2020-04-30 2021-11-02 台湾积体电路制造股份有限公司 Ic封装件及其形成方法以及在ic封装件中分配电源的方法
CN114094419A (zh) * 2020-07-16 2022-02-25 佳能株式会社 用于将两个电路单元电互连的中间连接构件
CN112435981A (zh) * 2020-09-30 2021-03-02 日月光半导体制造股份有限公司 半导体封装装置及其制造方法

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