CN101960589A - 包含用于高密度互连的硅贴片的微电子封装及其制造方法 - Google Patents

包含用于高密度互连的硅贴片的微电子封装及其制造方法 Download PDF

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CN101960589A
CN101960589A CN2009801071711A CN200980107171A CN101960589A CN 101960589 A CN101960589 A CN 101960589A CN 2009801071711 A CN2009801071711 A CN 2009801071711A CN 200980107171 A CN200980107171 A CN 200980107171A CN 101960589 A CN101960589 A CN 101960589A
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interconnection structure
tube core
silicon
paster
microelectronics packaging
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CN101960589B (zh
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R·马哈詹
S·萨内
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Intel Corp
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Abstract

一种微电子封装，包括：衬底(110)；嵌入在所述衬底中的硅贴片(120)；位于所述硅贴片的第一位置处的第一互连结构(131)和位于所述硅贴片的第二位置处的第二互连结构(132)；以及所述硅贴片中将所述第一互连结构和所述第二互连结构彼此连接的导电线(150)。

Description

包含用于高密度互连的硅贴片的微电子封装及其制造方法
技术领域
本发明所公开的实施例总体上涉及微电子封装，更具体而言，涉及微电子封装内的电连接。
背景技术
为了提高性能，中央处理单元(CPU)产品越来越多地在CPU封装内以并排或者其它的多芯片模块(MCU)的方式集成多个管芯。这种发展连同诸如长期以来的越来越朝着小型化发展的趋势的其它因素导致微电子工业的如下情况：在可用的空间中可能无法容纳足够数量的管芯连接(通过每层上管芯边缘的每毫米(mm)的输入/输出(I/O)来测量)。管芯连接的数量不足将限制受影响的管芯接口的带宽能力，并且从而使逻辑-逻辑和/或逻辑-存储器的通信受到影响。当前改进的方法通过缩放可控坍塌芯片连接(C4)互连来增大I/O密度，将来至少对于一些应用来说衬底的行/间隔将会相当不充足。
附图说明
通过结合附图来阅读下面的具体描述，将更好地理解所公开的实施例，在附图中：
图1是根据本发明的实施例的微电子封装的平面视图；
图2是根据本发明的实施例的图1的微电子封装的截面图；
图3-5是根据本发明的各个实施例的图1和图2的微电子封装的一部分的截面图；以及
图6是示出了制造根据本发明的实施例的微电子封装的方法的流程图。
为了例示的简单性和清楚性，附图示出了结构的概括方式，并且可以省略对公知特征和技术的描述和具体细节，以避免不必要地使对本发明所描述实施例的讨论难以理解。此外，附图中的元件不一定是按比例绘制的。例如，可以相对于其他元件放大附图中的一些元件的尺寸，从而有助于改善对本发明的实施例的理解。不同附图中的相同附图标记表示相同的元件，然而类似的附图标记不一定表示类似的元件。
如果存在的话，说明书和权利要求中的术语“第一”、“第二”、“第三”、“第四”，等等用于在类似元件之间进行区分，而不一定用于描述特定的连续顺序或者时间顺序。应理解这样使用的术语在适当的情况下是可互换的，使得这里所描述的本发明的实施例能够例如以除了这里例示或者以其它方式描述的那些顺序之外的顺序进行操作。类似地，如果方法在这里被描述为包括一系列步骤，这里所描述的这些步骤的顺序不一定是可以执行这些步骤的唯一顺序，并且某些所提到的步骤可能可以被省略和/或可能可以将这里未描述的某些其它步骤添加到该方法中。此外，术语“包括”、“包含”、“具有”及其任意的变型旨在覆盖非排它性的包括，使得包括一系列组成部分的工艺、方法、物品或装置不必限于这些组成部分，而是可以包括没有明确列出的或者这些工艺、方法、物品或装置固有的其他组成部分。
如果存在的话，说明书和权利要求中的术语“左”、“右”、“前”、“后”、“顶部”、“底部”、“上方”、“下方”，等等均用于说明性的目的，而不一定用于描述固定不变的相对位置。应理解这样使用的术语在适当的情况下是可互换的，使得这里所描述的本发明的实施例能够例如以这里例示或者以其它方式描述的那些取向之外的其它取向进行操作。这里所使用的术语“耦合”被定义为直接地或者间接地以电气或者非电气方式进行连接。在这里被描述为彼此“相邻”的对象可以彼此物理接触、彼此非常接近、或者彼此总体上位于相同的区域或者范围中，应该视使用该短语的语境而定。在这里，短语“在一个实施例中”的出现不一定都是指相同的实施例。
具体实施方式
在本发明的一个实施例中，微电子封装包括：衬底；嵌入所述衬底中的硅贴片(patch)；位于所述硅贴片的第一位置处的第一互连结构和位于所述硅贴片的第二位置处的第二互连结构；以及所述硅贴片中将所述第一互连结构和所述第二互连结构彼此连接的导电线。
本发明的实施例可以提供明显增加的I/O密度，并且因此为在微电子封装中的管芯之间进行通信提供了明显增大的带宽。一般来说，本发明的实施例利用高密度的焊料凸块和细线嵌入硅片，其中使用传统的硅工艺来制造所述细线。具有逻辑或者存储器管芯的组件可以使用本领域公知的传统组装工艺。
例如，具有10微米(在下文中，称为“微米”或者“μm”)的行/间隔的150μm的最小互连间距产生大约28 I/O每毫米每层的I/O密度。如果这些值缩减到例如80μm的间距和2μm的行/间隔，所述I/O密度将增加到大约100 I/O每毫米每层。除了这种I/O密度将提供的极大提高的通信带宽之外，(至少部分)由于硅工艺技术的成熟，本发明的实施例还可以实现改进的组装工艺。因此，本发明的实施例提供了一种在逻辑-逻辑管芯和/或逻辑-存储器管芯之间制造高密度互连的新方法，从而实现了满足未来的需求所需的高带宽的互连。
此外，因为在位于距离中性点(DNP)最大距离处和别处的凸块的CTE失配减小，所以本发明的实施例可以导致整体机械可靠性(例如，凸块裂缝、ILD故障，等等)的改进。例如并且如下面将进一步讨论的，根据所嵌入的硅的几何形状，在封装衬底中嵌入硅可以将衬底的有效热膨胀系数(CTE)减小到与相关联的管芯的CTE更匹配的值。除了上面提到的之外，有效衬底CTE的减小具有几个潜在的机械上益处，包括减小到硅后端(backend)互连层中的脆性低k层间电介质(ILD)层的应力传递、减小后端(post)组装的翘曲、以及减小可靠性测试期间的热介面材料(TIM)应力。
现在参考附图，图1是根据本发明的实施例的微电子封装的平面视图。如图1所示，微电子封装100包括衬底110和嵌入衬底110中的硅贴片120。微电子封装100还包括位于硅贴片120中的位置141处的互连结构131、位于硅贴片120中的位置142处的互连结构132、以及硅贴片120中将互连结构131和互连结构132彼此连接的导电线150。在所示的实施例中，互连结构131是位于位置141处的多个互连结构中的一个，互连结构132是位于位置142处的多个互连结构中的一个。例如，可以将这些多个互连结构设计成使其实现的互连的数量最大化。
例如，衬底110可以是本领域公知的传统的有机衬底。又例如，互连结构131和/或互连结构132可以包括铜柱等。在一个实施例中，铜柱包括互锁特征件(interlocking feature)，这将在随后的附图中示出并且在下面进行进一步的讨论。
又例如，导电线150的宽度(以及在这里描述的所有类似的导电线的宽度)可以不大于大约0.2微米(在下文中称为“微米”)，尽管至少一对相邻的互连结构之间的间隔(即，间距)不大于80微米。对于本领域技术人员显而易见的是，这些间距和线宽比利用当前可用的技术所能够得到的聚合物层中的铜线的间距和线宽明显小很多。根据本发明的实施例在衬底中嵌入硅的优点在于，硅工艺已经发展到这种小间距和线宽处于当前技术的可实现范围内的程度。
微电子封装100还包括衬底110上方的管芯161和管芯162。在图1中，用虚线示出了管芯161和管芯162的轮廓，以表示其位于硅贴片120和衬底110上方。换句话说，图1将管芯161和管芯162描绘成好像是透明的(除了它们的轮廓)，从而可以观察到下面的细节。概括地说，位置141是硅贴片120的位于管芯161下的区域，而位置142是硅贴片120的位于管芯162下的区域。
图1还示出了对未标示的一对互连结构(一个处于位置141以及一个处于位置142)进行连接的导电线155，并且还示出了附加的硅贴片170、附加的互连结构180以及附加的管芯190。应注意在图1中仅附加的互连结构180中的一些标示有附图标记；基于与被标示的那些互连结构180的外观的类似性，应该能容易地识别图中未标示的互连结构180。例如，硅贴片170中的每一个可以与硅贴片120类似。在一个实施例中，硅贴片170彼此不覆盖或者接触，以避免否则可能发生的潜在的灵活性问题。又例如，互连结构180中的每一个可以与互连结构131和/或互连结构132类似。再例如，管芯190中的每一个可以与管芯161和/或管芯162类似。
实际上，在嵌入的硅贴片内将密集地填装大量的诸如导电线150和155的导电线，从而实现非常低的间距以及非常高密度的互连。可以使用传统的硅制造工艺来管理这些互连的RC特性。
图2是沿着图1的II-II线截取的微电子封装100的截面图。图2中示出了衬底110、硅贴片120、处于相应位置141和142处的互连结构131和132、导电线150和155、管芯161和162、附加的硅贴片170中的一个、以及附加的管芯190中的一个。为了图2清楚起见，利用剖面线标记示出了硅贴片120和170。应注意，并未如图1中所绘示的那样在那些硅贴片中示出剖面线标记。
如图2所示，导电线150和155延伸至硅贴片120中相同的深度。另一方面，硅贴片170包含一对在硅贴片170中延伸至不同深度的导电线(未标示)。根据本发明的各个实施例，可以将这些结构中的任一个或者两者，或者某另一结构用作硅贴片中的导电线。在一个实施例中，硅贴片自身在衬底110内的深度可以在大约70到100微米之间。
如图2进一步所示，衬底110包含其中具有缓冲材料210的孔口(well)(或者多个孔口)。将硅贴片120(以及硅贴片170)以与缓冲材料210相邻的方式嵌入孔口中。例如，缓冲材料210可以是提供(具有连接性的)柔顺垫的基于硅酮的材料等，以便在硅贴片120和170的硅和衬底110的有机材料之间提供应力缓冲。无论其成分如何，缓冲材料210用于减轻由于两种材料之间的CTE失配引起的硅贴片和衬底两者所承受的CTE应力的水平。
继续讨论CTE失配的问题，值得一提的是在衬底110中硅贴片120和170的存在将使衬底110的有效CTE从大约百万分之17每度开尔文(ppm/°K)的值(没有硅贴片)减小到具有硅贴片的大约10-12ppm/°K的值。(具有嵌入的硅贴片的衬底的实际CTE值取决于所嵌入的硅的几何形状)。上面已经提到了有效衬底CTE的这种减小的几种益处。
在所示出的实施例中，微电子封装100还包括衬底110中的导电线220。(为简单起见，将这些示出为在衬底110中终结而没有连接到任何地方，但是实际上它们当然是连续的并且完成它们期望的电连接。)导电线220可以位于所示出的位置和/或位于根据微电子封装100的设计要求所需要的其它位置。例如，导电线220可以是电源线，并且因此可以数量更少和/或因为它们必须承载更大的电流所以具有比导电线150和155更大的尺寸(如上所述，其设计用于封装管芯之间的高带宽、高密度的总线互连)。应该理解也可以将导电线中的一些或者全部用作其它目的，并且还应理解导电线220可以如图所示位于硅贴片的外侧或者位于硅贴片以内。
图2中的特征件275包括互连结构131并且还包括导电结构231以及(在一些情况下)各种其它附加的结构和/或将结合图3-5描述的细节，图3-5是根据本发明的各个实施例的微电子封装100的示出部分的截面图。这些细节不包括在图2中，因为图2较小的比例使得它们不容易包括在内并且还因为图2旨在概括地足够包括特征件275的许多可能的结构。类似地，在图2中示出的某些细节可能在图3-5中予以省略。例如，导电结构231可以与导电互连结构131类似。
图3示出了其中焊料凸块310位于导电互连结构131和导电结构231之间的实施例。除了其他可能的优点，铜柱(或者其它互连结构)之间的焊料凸块可以使用公知的工艺来形成，制造起来相对容易，并且有助于进行自对准。
图4示出了其中互连结构131和导电结构231被按压在一起以便有助于扩散接合的实施例。例如，该工艺可以降低粘结温度并且改变接头和整个结构中最终的应力状态。
图5示出了其中互连结构131和导电结构231设置有诸如形成所示出的燕尾状接头的那些互锁特征件的互锁特征件的实施例，其中互连结构131上的突出部分510被设计成配合到导电结构231中的开口520中，从而将两个互连结构互锁在一起。例如，该技术可以改进被连接的两个硅实体的对准。本领域技术人员应该意识到，很多其它类型的互锁特征件也是可以的。
图6是示出了制造根据本发明的实施例的微电子封装的方法600的流程图。方法600的步骤610提供其中嵌入有硅贴片的衬底。例如，衬底可以与衬底110类似，并且硅贴片可以与硅贴片120类似，衬底110和硅贴片120在图1中首次示出。
方法600的步骤620在硅贴片的第一位置处形成第一互连结构并且在硅贴片的第二位置处形成第二互连结构。例如，第一互连结构可以与互连结构131类似，第二互连结构可以与互连结构132类似，互连结构131和互连结构132在图1中首次示出。
方法600的步骤630将第一互连结构和第二互连结构彼此电连接。
方法600的步骤640在所述第一位置上方设置第一管芯，并且在所述第二位置上方设置第二管芯。例如，所述第一管芯可以与管芯161类似，所述第二管芯可以与管芯162类似，管芯161和管芯162在图1中首次示出。
方法600的步骤650将所述第一管芯和所述第一互连结构彼此电连接。在一个实施例中，步骤650包括在所述第一管芯处设置第一导电结构并且在所述第一导电结构和所述第一互连结构之间设置第一焊接点。例如，第一导电结构可以与在图2中首次示出的导电结构231类似。又例如，第一焊接点可以与在图3中首次示出的焊料凸块310类似。在另一实施例中，步骤650包括将所述第一导电结构和所述第一互连结构按压到一起，以便在其间形成扩散接合。
在不同的实施例中，第一互连结构具有第一互锁特征件，第一导电结构具有第三互锁特征件。例如，第一互锁特征件可以与突出部分510类似，第三互锁特征件可以与开口520类似，在图5中示出了突出部分510和开口520。在该实施例中，步骤650可以包括对第一互连特征件和第三互锁特征件进行互锁。
方法600的步骤660将所述第二管芯和所述第二互连结构彼此电连接。在一个实施例中，步骤660和步骤650可以作为同一步骤的一部分来执行，并且在同一或者另一实施例中，步骤660和步骤650可以被同时执行。在同一或者另一实施例中，步骤660包括在第二管芯处设置第二导电结构，并且在第二导电结构和第二互连结构之间设置第二焊接点。例如，第二导电结构可以与在图2中首次示出的导电结构231类似。又例如，第二焊接点可以与在图3中首次示出的焊料凸块310类似。在另一实施例中，步骤660包括将第二导电结构和第二互连结构按压在一起，以便在其间形成扩散接合。
在不同的实施例中，第二互连结构具有第二互锁特征件，并且第二导电结构具有第四互锁特征件。例如，第二互锁特征件可以与突出部分510类似，并且第四互锁特征件可以与开口520类似，在图5中示出了突出部分510和开口520。在该实施例中，步骤660可以包括对第二互锁特征件和第四互锁特征件进行互锁。
应该理解如上所述，上述步骤例示了本发明的一个实施例，并且可以以各种方式进行修改而不超出本发明的范围。仅作为一个示例，可以在执行步骤630之前执行步骤650和/或步骤660。换句话说，在将第一和第二互连结构彼此电连接之前，可以将第一管芯和第一互连结构和/或第二管芯和第二互连结构彼此电互连。
尽管已经参考特定的实施例描述了本发明，但是本领域技术人员将会理解，在不偏离本发明的精神或范围的情况下，可以进行各种改变。因此，本发明的实施例的公开旨在例示本发明的范围，而非旨在对其进行限制。本发明的范围将仅由所附权利要求书所要求的范围来限制。例如，对于本领域技术人员而言显而易见的是，可以以各种实施例来实施这里所讨论的微电子封装和相关方法，并且对这些实施例中的某一些的上述讨论不一定代表对所有可能的实施例的完整描述。
此外，已经就特定实施例描述了益处、其它优点以及问题的解决方案。然而，这些益处、优点、问题的解决方案、以及可以促使任何益处、优点、或者方案产生或变得更显著的任意一个要素或多个要素不应被理解为任何或所有权利要求的决定性的、必需的、或者必要的特征或要素。
此外，即使这里所公开的实施例和/或限制(1)并未明确限定在权利要求书中；以及(2)根据等同原则是权利要求书中的明确表述的要素和/或限制的等同物或者是可能的等同物，所述实施例和限制也不根据贡献原则贡献给公众。

Claims (20)

1.一种微电子封装，包括：
衬底；
嵌入所述衬底中的硅贴片；
位于所述硅贴片的第一位置处的第一互连结构和位于所述硅贴片的第二位置处的第二互连结构；以及
所述硅贴片中将所述第一互连结构和所述第二互连结构彼此连接的导电线。
2.根据权利要求1所述的微电子封装，其中：
所述衬底包含其中具有缓冲材料的孔口；并且
所述硅贴片以与所述缓冲材料相邻的方式嵌入所述孔口中。
3.根据权利要求1所述的微电子封装，其中：
所述第一和第二互连结构中的至少一个包括铜柱。
4.根据权利要求3所述的微电子封装，其中：
所述铜柱包括互锁特征件。
5.根据权利要求1所述的微电子封装，其中：
所述导电线的宽度不大于大约0.2微米。
6.根据权利要求1所述的微电子封装，还包括：
所述衬底中的电源线。
7.根据权利要求1所述的微电子封装，其中：
所述衬底的有效热膨胀系数在大约10ppm/°K和大约12ppm/°K之间。
8.一种微电子封装，包括：
衬底；
位于所述衬底上方的第一管芯和第二管芯；
嵌入在所述衬底中的硅贴片；
所述硅贴片中位于所述第一管芯下方的第一多个互连结构和所述硅贴片中位于所述第二管芯下方的第二多个互连结构；以及
导电线，所述导电线将所述第一多个互连结构中的第一个和所述第二多个互连结构中的第一个彼此连接。
9.根据权利要求8所述的微电子封装，其中：
所述衬底包含其中具有缓冲材料的孔口；并且
所述硅贴片以与所述缓冲材料相邻的方式嵌入所述孔口中。
10.根据权利要求9所述的微电子封装，其中：
所述第一和第二多个互连结构中的至少一个中的至少一对相邻互连结构之间的间隔不大于80微米。
11.根据权利要求9所述的微电子封装，其中：
所述衬底的有效热膨胀系数在大约10ppm/°K和大约12ppm/°K之间。
12.根据权利要求9所述的微电子封装，其中：
所述第一和第二多个互连结构中的每一个包括铜柱。
13.根据权利要求12所述的微电子封装，其中：
所述铜柱中的至少一个包括互锁特征件。
14.根据权利要求12所述的微电子封装，其中：
所述导电线的宽度不大于大约0.2微米。
15.根据权利要求14所述的微电子封装，还包括：
所述衬底中的电源线。
16.一种制造微电子封装的方法，所述方法包括：
提供其中嵌入有硅贴片的衬底；
在所述硅贴片的第一位置处形成第一互连结构并且在所述硅贴片的第二位置处形成第二互连结构；以及
将所述第一互连结构和所述第二互连结构彼此电连接。
17.根据权利要求16所述的方法，还包括：
在所述第一位置上方设置第一管芯并且在所述第二位置上方设置第二管芯；
将所述第一管芯和所述第一互连结构彼此电连接；以及
将所述第二管芯和所述第二互连结构彼此电连接。
18.根据权利要求17所述的方法，其中：
将所述第一管芯和所述第一互连结构彼此电连接包括：
在所述第一管芯处设置第一导电结构；以及
在所述第一导电结构和所述第一互连结构之间设置第一焊接点；并且
将所述第二管芯和所述第二互连结构彼此电连接包括：
在所述第二管芯处设置第二导电结构；以及
在所述第二导电结构和所述第二互连结构之间设置第二焊接点。
19.根据权利要求17所述的方法，其中：
将所述第一管芯和所述第一互连结构彼此电连接包括：
在所述第一管芯处设置第一导电结构；以及
将所述第一导电结构和所述第一互连结构按压在一起；并且
将所述第二管芯和所述第二互连结构彼此电连接包括：
在所述第二管芯处设置第二导电结构；以及
将所述第二导电结构和所述第二互连结构按压在一起。
20.根据权利要求17所述的方法，其中：
所述第一互连结构具有第一互锁特征件；
所述第二互连结构具有第二互锁特征件；
将所述第一管芯和所述第一互连结构彼此电连接包括：
在所述第一管芯处设置第一导电结构，所述第一导电结构具有第三互锁特征件；以及
对所述第一互锁特征件和所述第三互锁特征件进行互锁；并且
将所述第二管芯和所述第二互连结构彼此电连接包括：
在所述第二管芯处设置第二导电结构，所述第二导电结构具有第四互锁特征件；以及
对所述第二互锁特征件和所述第四互锁特征件进行互锁。
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CN101960589B (zh) 2012-10-10
KR101182010B1 (ko) 2012-09-11
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US8441809B2 (en) 2013-05-14
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GB2470866A (en) 2010-12-08
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GB201015981D0 (en) 2010-11-03
US8064224B2 (en) 2011-11-22
DE112009005519A5 (de) 2014-12-31
DE112009000351B4 (de) 2014-07-17
TW200950034A (en) 2009-12-01
DE112009000351T5 (de) 2011-05-05
WO2009146007A2 (en) 2009-12-03
JP2011515842A (ja) 2011-05-19
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DE112009005519B4 (de) 2021-08-19

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