CN105633049B - 封装结构的制法 - Google Patents
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Abstract
一种封装结构及其制法,该封装结构包括框体、半导体晶片、介电层与线路层,该框体具有贯穿的开口,该半导体晶片设于该框体的开口中,且具有外露于该开口的相对的作用面与非作用面,该介电层形成于该开口中,以接触并固定该半导体晶片,且该介电层与该作用面侧的框体表面齐平,该线路层形成于该作用面侧的介电层上,以电性连接该作用面。本发明能有效节省成本与减少厚度。
Description
技术领域
本发明有关于一种封装结构的制法,尤指一种具有线路层的封装结构的制法。
背景技术
现行的覆晶技术因具有缩小晶片封装面积及缩短讯号传输路径等优点,目前已经广泛应用于晶片封装领域,例如:晶片尺寸构装(Chip Scale Package,CSP)、晶片直接贴附封装(Direct Chip Attached,DCA)以及多晶片模组封装(Multi-Chip Module,MCM)等型态的封装模组,其均可利用覆晶技术而达到封装的目的。
于覆晶封装制程中,因晶片与封装基板的热膨胀系数的差异甚大,所以晶片外围的凸块无法与封装基板上对应的接点形成良好的接合,使得凸块容易自封装基板上剥离。另一方面,随着积体电路的积集度的增加,因晶片与封装基板之间的热膨胀系数不匹配(mismatch),其所产生的热应力(thermal stress)与翘曲(warpage)的现象也日渐严重,其结果将导致晶片与封装基板之间的电性连接的可靠度(reliability)下降,并造成信赖性测试的失败。
为了解决上述问题,遂发展出以半导体基材作为中介结构的制程,其通过于一封装基板与一半导体晶片之间增设一硅中介板(silicon interposer),因为该硅中介板与该半导体晶片的材质接近,所以可有效避免热膨胀系数不匹配所产生的问题。
请参阅图1,其为现有具硅中介板的堆迭封装结构的剖视图。如图所示,现有的封装结构除了能避免前述问题外,相较于直接将半导体晶片接置于封装基板的情况,现有的封装结构也可使封装结构的版面面积更加缩小。
举例来说,一般封装基板最小的线宽/线距只可做到12/12微米,而当半导体晶片的输入输出(I/O)数增加时,由于线宽/线距已无法再缩小,所以须加大封装基板的面积以提高布线数量,以便于接置高输入输出(I/O)数的半导体晶片;相对地,由于图1的封装结构将半导体晶片11接置于一具有硅贯孔(through silicon via,TSV)121的硅中介板12上,以该硅中介板12做为一转接板,进而将半导体晶片11电性连接至封装基板13上,而硅中介板12可利用半导体制程做出3/3微米或以下的线宽/线距,所以当半导体晶片11的输入输出(I/O)数增加时,该硅中介板12的面积已足够连接高输入输出(I/O)数的半导体晶片11。此外,因为该硅中介板12具有细线宽/线距的特性,其电性传输距离较短,所以连接于该硅中介板12的半导体晶片11的电性传输速度(效率)也较将半导体晶片直接接置封装基板的速度(效率)来得快。
然而,由于现有为使用硅中介板12的硅贯孔121来电性连接上下两侧的半导体晶片11与封装基板13,但制作硅贯孔121会使得整体封装成本提高;此外,最终封装结构也会因为多了硅中介板12而增加不少厚度。
因此,如何避免上述现有技术中的种种问题,实为目前业界所急需解决的课题。
发明内容
有鉴于上述现有技术的缺失,本发明提供一种封装结构及其制法,能有效节省成本与减少厚度。
本发明的封装结构,包括:具有贯穿的开口的框体;设于该框体的开口中的半导体晶片,其具有外露于该开口的相对的作用面与非作用面;形成于该开口中的介电层,以接触并固定该半导体晶片,且该介电层与该作用面侧的框体表面齐平;以及形成于该作用面侧的介电层上的线路层,以电性连接该作用面。
本发明还提供一种封装结构,其包括:框体,其具有贯穿的开口;半导体晶片,其设于该框体的开口中,且具有外露于该开口的相对的作用面与非作用面;介电层,其形成于该开口中,以接触并固定该半导体晶片;线路层,其形成于该作用面侧的介电层上,以电性连接该作用面;以及承载板,其设于该框体、介电层和半导体晶片的非作用面上,且该框体和承载板为非一体成形。
本发明还提供一种封装结构的制法,其包括:提供一具有相对的第一表面与第二表面的承载板,该承载板的第一表面上形成有具有外露该第一表面的开口的框体,该框体和承载板为非一体成形,该开口中的第一表面上设置有具相对的作用面与非作用面的半导体晶片,该半导体晶片以该非作用面接合该第一表面,且该开口中填有介电层,以接触并固定该半导体晶片;于该介电层上形成线路层,以电性连接该作用面;以及移除该承载板,以外露该半导体晶片的非作用面。
于一具体实施例中,提供该承载板与框体及设置该半导体晶片的步骤包括:于该承载板上设置该半导体晶片;于该承载板上接置一具有凹部的盖板,该凹部面对该承载板,令该半导体晶片对应容置于该凹部中;移除该盖板的部分厚度,以外露该半导体晶片及该盖板所留下的该框体;以及于该框体的开口中形成具有外露至少部分的该作用面的介电层。
于另一具体实施例中,形成该框体及该介电层的步骤包括:提供一其上设有该半导体晶片及一具有凹部的盖板的该承载板,该凹部面对该承载板,使该半导体晶片对应容置于该凹部底面,并令该盖板悬空在该承载板上;于该凹部中及盖板和承载板之间形成介电层,以接触并固定该半导体晶片;以及移除该盖板的部分厚度,以外露该半导体晶片及该盖板所留下的该框体。
由上可知,本发明以较便宜的线路层取代现有的中介板,且亦省去现有半导体晶片与中介板之间的焊球,因此能有效减少封装结构的成本与厚度。
附图说明
图1为现有具硅中介板的堆迭封装结构的剖视图;
图2A至图2L’所示者为本发明的封装结构的制法的剖视图,其中,图2C’为图2C的另一实施例,图2D’与图2D”为图2D的不同实施例,图2L’为接续图2D”得到的封装结构,图2L”为具有承载板的封装结构的剖视图;
图3A及图3B为接续图2D’后的二种封装结构的剖视图,图3A’及图3B’为具有承载板的封装结构的剖视图;以及
图4A至图4E’为本发明封装结构的另一制法的剖视图,其中,图4D’及图4E’为图4D及图4E的不同实施例。
符号说明
11、22 半导体晶片
12 硅中介板
121 硅贯孔
13 封装基板
20 承载板
20a 第一表面
20b 第二表面
21 盖板
210 凹部
22a 作用面
22b 非作用面
21’ 框体
210’ 开口
23 介电层
23’ 介电增层
230 开孔
24 导电体
25 线路层
26 绝缘保护层
260 绝缘保护层开孔
27 导电元件
28 基板。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用于配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用于限定本发明可实施的限定条件,所以不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的用语也仅为便于叙述的明了,而非用于限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当亦视为本发明可实施的范畴。
图2A至图2L所示者,其为本发明的封装结构的制法的剖视图,其中,图2C’为图2C的另一实施例,图2D’与图2D”为图2D的不同实施例,图2D’为接续图2C’的实施例。
如图2A所示,提供一具有相对的第一表面20a与第二表面20b的承载板20与一具有凹部210的盖板21,其二者并非一体成形。
该承载板20与盖板21可为有机或无机材质,该有机材质为例如苯环丁烯(Benzocyclo-buthene,BCB)或聚酰亚胺(polyimide),该无机材质为例如碳化硅(SiC)或二氧化硅(SiO2),形成该承载板20与盖板21的材质可为金属、玻璃、陶瓷或半导体,该半导体为例如硅(Si)或砷化镓(gallium arsenide,GaAs)。
如图2B所示,于该承载板20的第一表面20a上设置至少一具有相对的作用面22a与非作用面22b的半导体晶片22,多个该半导体晶片22的大小或厚度(或称为高度)可彼此不同,令该非作用面22b接合该第一表面20a,该半导体晶片22可藉由粘着层或粘晶膜(dieattach film)(未图示)以接置于该第一表面20a上,或者,该半导体晶片22可藉由促进剂(promoter)层(未图示)与感光材料层(未图示)依序形成于该第一表面20a上,而得以接置于该第一表面20a上,促进剂层的作用,是使得感光材料层如PBO藉由促进剂较粘着该承载板20而较不粘着该半导体晶片22。
而该感光材料层可为感光型旋涂式介电质(photosensitive spin-ondielectrics,PSOD,例如聚对二唑苯先驱物(Photo definable Polybenzobisoxazole(PBO)precursor))、或可光定义材料(photodefinable material,例如聚亚酰胺先驱物(polyimide precursor))、或感光可图案化材料(photosensitive patternablematerial,例如聚倍半硅氧烷合成物(polysilsesquiazane composition))。
接着,于该承载板20上接置该盖板21,该凹部210面对该承载板20,令该半导体晶片22对应容置于该凹部210中,该盖板21可藉由熔合结合(fusion bond)或粘着结合方式接置于该承载板20上。
如图2C所示,藉由例如研磨方式移除该盖板21的部分厚度,以外露该半导体晶片22,剩余的该盖体21定义为具有外露该第一表面20a的开口210’的框体21’。此外,本实施例中,该框体21’的高度高于该半导体晶片22的高度。
或者,于另一实施例中,该框体21’等于或齐平于该半导体晶片22,如图2C’所示。
如图2D所示,于该框体21’与该半导体晶片22的作用面22a上形成介电层23,该介电层23还可填入至该开口210’中,使该介电层23覆盖该框体21’和半导体晶片22。该介电层23可为感光型的干膜(dry film),该介电层23可为有机材质或无机材质,其中,该有机材质为聚酰亚胺、聚对二唑苯或苯环丁烯;该无机材质为氧化硅或氮化硅。
或者,于另一实施例中,可透过研磨的方式移除图2D中部分框体21’和介电层23,使该介电层23与该作用面22a侧的框体21’表面齐平,如图2D’所示。
或者,于又一实施例中,该框体21’的高度高于该半导体晶片22的高度,而形成的该介电层23仅覆盖该半导体晶片22,且该介电层23与该作用面22a侧的框体21’表面齐平。当然,也可透过研磨的方式移除图2D中部分框介电层23,使该介电层23与该作用面22a侧的框体21’表面齐平,如图2D”所示。
接续图2D,如图2E所示,于该介电层23中形成外露该作用面22a的多个开孔230。
如图2F所示,于该开孔230中形成电性连接该作用面22a的导电体24。
如图2G所示,于该介电层23上形成电性连接该导电体24与作用面22a的线路层25,例如线路重布层(RDL)。此外,该线路重布层可为单一层线路或如图2G所示包括例如三层线路的多层线路。而该导电体24及该导电体24接触并电线连接的第一层线路可如图2F及图2G所示分段形成,也可于一步骤中同时形成该第一层线路和导电体24。
如图2H所示,于该线路层25上形成具有多个绝缘保护层开孔260的绝缘保护层26。
如图2I所示,于该等绝缘保护层开孔260中设置多个导电元件27,该导电元件27可为焊球。
如图2J所示,进行切单步骤,即可得本发明的封装结构。
如图2K所示,藉由该等导电元件27于该线路层25上接置并电性连接一基板28,该基板28可为封装基板。
如图2L所示,移除该承载板20,以外露该半导体晶片22的非作用面22b,以得到无承载板20的封装结构。此外,若于图2B的步骤中形成有该粘晶膜、促进剂层或聚对二唑苯层,则移除该承载板20还包括移除该粘晶膜、促进剂层或聚对二唑苯层。
于另一实施例中,如接续图2D”,则得到如图2L’的封装结构,在此结构中,该介电层23与该作用面22a侧的框体21’表面齐平,且该介电层23覆盖该作用面22a,且该封装结构还包括多个形成于该介电层23中并电性连接该作用面22a的导电体24,该线路层25接触该介电层23并电性连接该多个导电体24。当然,如图2L”所示,该封装结构也可具有承载板20,设于该框体21’、介电层23和半导体晶片22的非作用面22b上,且该框体21’和承载板20为非一体成形。
请参阅图3A的另一实施例,其为接续图2D’的步骤,在形成介电层23之后,于该作用面22a及框体21’上形成介电增层23’,并于介电增层23’中形成多个导电体24,之后如图2G至图2L的步骤形成电性连接该导电体24的线路层25、绝缘保护层26及导电元件27,并接置基板28。
如图3B所示,其为图3A的另一实施例,其二者的差异仅在于图3B的实施例中,省略了形成介电增层23’和导电体24的步骤,直接形成线路层25以电性连接该作用面22a。因此,本实施例中,相对于框体21’,该整作用面22a及整非作用面22b皆外露于该介电层23,该线路层25接触并电性连接该作用面22a。
此外,如图3A’及图3B’所示,该封装结构具有承载板20。
请参阅图4A至图4E’,其为本发明封装结构的另一制法。
如图4A所示,提供一其上设有该半导体晶片22及一具有凹部210的盖板21的该承载板20,该凹部210面对该承载板20,使该半导体晶片22对应容置于该凹部210底面,并令该盖板21悬空在该承载板20上。
如图4B所示,于该凹部210中及盖板21和承载板20之间形成介电层23,以接触并固定该半导体晶片22。
如图4C所示,移除该盖板21的部分厚度,以外露该半导体晶片22及该盖板21所留下的该框体21’。
接着,于该介电层23上依序形成线路层25、绝缘保护层26及导电元件27,以电性连接该作用面22a,如图4D所示。
或者,如图4D’所示,于该介电层23上先形成介电增层23’,再依序形成线路层25、绝缘保护层26及导电元件27。
如图4E及图4E’所示,藉由该等导电元件27接置并电性连接一基板28,再移除该承载板20,以外露该半导体晶片22的非作用面22b,得到本发明的封装结构。
本发明提供一种封装结构,包括:框体21’,其具有贯穿的开口210’;半导体晶片22,设于该框体21’的开口210’中,且具有外露于该开口210’的相对的作用面22a与非作用面22b;介电层23,其形成于该开口210’中,以接触并固定该半导体晶片22,且该介电层23与该作用面22a侧的框体21’表面齐平;以及线路层25,其形成于该作用面22a侧的介电层23上,以电性连接该作用面22a。
于另一实施例中,如图2J及图2K所示,该封装结构还具有承载板20,其设于该框体21’、介电层23和半导体晶片22的非作用面22b上,且该框体21’和承载板20为非一体成形。
于一实施例中,如图2L’所示,该介电层23覆盖该作用面22a,且该封装结构还包括多个形成于该介电层23中并电性连接该作用面22a的导电体24,该线路层25接触该介电层23并电性连接该多个导电体24。
如图2L”所示,该介电层23覆盖该作用面22a,并与该作用面22a侧的框体21’齐平,且该封装结构还包括承载板20、及多个形成于该介电层23中并电性连接该作用面22a的导电体24,该线路层25接触该介电层23并电性连接该多个导电体24。
于另一实施例中,该半导体晶片22的整作用面22a及整非作用面22b皆外露于该介电层23,且该封装结构还包括形成于该作用面22a侧的介电层23上的介电增层23’、以及形成于该介电增层23’中的多个导电体24,且该线路层25位于该介电增层23’上,并透过多个该导电体24电性连接该作用面22a。在此例中,如图3A所示,该框体21’的厚度与半导体晶片22和介电层23的厚度相同。或如图4E’所示,该框体21’的厚度小于该半导体晶片22,且该介电层23还形成于该非作用面22b侧的框体21’表面。
于另一实施例中,该整作用面22a及整非作用面22b皆外露于该介电层23,该线路层25接触并电性连接该作用面22a,其中,如图3B所示,该框体21’的厚度与半导体晶片22和介电层23的厚度相同。或如图4E所示,该框体21’的厚度小于该半导体晶片22,且该介电层23还形成于该非作用面22b侧的框体21’表面。
如图3A’所示,该封装结构具有承载板20。又,该整作用面22a及整非作用面22b皆外露于该介电层23,且该封装结构还包括形成于该作用面22a侧的介电层23上的介电增层23’、以及形成于该介电增层23’中的多个导电体24,且该线路层25位于该介电增层23’上,并透过多个该导电体24电性连接该作用面22a。
如图3B’所示,该封装结构具有承载板20。又,该整作用面22a及整非作用面22b皆外露于该介电层23,该线路层25接触并电性连接该作用面22a。
于前述的封装结构中,还可包括多个导电元件27,其接置于该线路层25上并电性连接该线路层25。
本实施例的封装结构还可包括一基板28,其藉由该等导电元件27接置于该线路层25上。
综上所述,相较于现有技术,由于本发明是以较便宜的线路层取代现有的中介板,且还省去现有半导体晶片与中介板之间的焊球,因此能有效减少封装结构的成本与厚度;而且,本发明于形成线路层时或于连接基板时仍存在有承载板,该承载板可提供刚性支撑以避免翘曲现象;此外,最终半导体晶片的非作用面为外露,所以能有效促进散热;此外,本发明的框体可有效固定半导体晶片,以避免半导体晶片于制程中位移。
上述实施例仅用于例示性说明本发明的原理及其功效,而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。
Claims (17)
1.一种封装结构的制法,包括:
提供一具有相对的第一表面与第二表面的承载板,于该承载板上设置具有相对的作用面与非作用面的半导体芯片,该半导体芯片以该非作用面接合该第一表面;
于该承载板上接置一具有凹部的盖板,该凹部面对该承载板,令该半导体芯片对应容置于该凹部中;
移除该盖板的部分厚度,以令该盖板形成外露该半导体芯片的框体,该框体具有外露该第一表面的开口;
于该框体的开口中形成具有外露至少部分的该作用面的介电层,以接触并固定该半导体晶片;
于该介电层上形成线路层,以电性连接该作用面;以及
移除该承载板,以外露该半导体晶片的非作用面。
2.如权利要求1所述的封装结构的制法,其特征为,于移除该承载板之前,还包括于该线路层上接置并电性连接多个导电元件。
3.如权利要求2所述的封装结构的制法,其特征为,于移除该承载板之前,还包括将一基板接置并电性连接于该多个导电元件上。
4.如权利要求1所述的封装结构的制法,其特征为,该盖板通过熔合结合或粘着结合方式接置于该承载板上。
5.如权利要求1所述的封装结构的制法,其特征为,该开口中具有多个该半导体晶片,且各该半导体晶片的高度为相同或不同。
6.如权利要求1所述的封装结构的制法,其特征为,该半导体晶片通过粘晶膜以接置于该第一表面上,且移除该承载板还包括移除该粘晶膜。
7.如权利要求1所述的封装结构的制法,其特征为,该半导体晶片还通过促进剂层与感光材料层依序形成于该第一表面上,得以接置于该第一表面上,且移除该承载板还包括移除该促进剂层与感光材料层。
8.如权利要求7所述的封装结构的制法,其特征为,该感光材料层的材质为感光型旋涂式介电质(photosensitive spin-on dielectrics,PSOD)、可光定义材料(photodefinablematerial)或感光可图案化材料(photosensitive patternable material)。
9.如权利要求1所述的封装结构的制法,其特征为,该框体的高度高于该半导体晶片的高度,且该介电层覆盖该框体和半导体晶片;或该框体的高度高于该半导体晶片的高度,而该介电层仅覆盖该半导体晶片,且该介电层与该作用面侧的框体表面齐平。
10.如权利要求1所述的封装结构的制法,其特征为,该框体的高度等于该半导体晶片的高度,且该介电层与该作用面侧的框体表面齐平。
11.如权利要求1所述的封装结构的制法,其特征为,该线路层接触该作用面或透过多个导电体电性连接该作用面。
12.如权利要求11所述的封装结构的制法,其特征为,该线路层透过多个导电体电性连接该作用面,且该线路层包括至少一层线路,其与该导电体同时或分别形成。
13.如权利要求1所述的封装结构的制法,其特征为,该介电层为有机材质或无机材质。
14.如权利要求13所述的封装结构的制法,其特征为,该有机材质为聚酰亚胺、聚对二唑苯或苯环丁烯;该无机材质为氧化硅或氮化硅。
15.如权利要求1所述的封装结构的制法,其特征为,形成该框体及该介电层的步骤包括:
令该盖板悬空在该承载板上;以及
移除该盖板的部分厚度,以外露该半导体晶片及该盖板所留下的该框体,该框体的厚度小于该半导体晶片。
16.如权利要求15所述的封装结构的制法,其特征为,该线路层接触该作用面或透过多个导电体电性连接该作用面。
17.如权利要求1所述的封装结构的制法,其特征为,于形成该线路层之后,还包括进行切单步骤。
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TWI618206B (zh) * | 2017-06-09 | 2018-03-11 | 恆勁科技股份有限公司 | 半導體封裝結構及其製作方法 |
CN107527880A (zh) * | 2017-08-02 | 2017-12-29 | 中芯长电半导体(江阴)有限公司 | 扇出型封装结构及其制备方法 |
US10504858B2 (en) * | 2018-04-27 | 2019-12-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method of fabricating the same |
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1797726A (zh) * | 2004-12-20 | 2006-07-05 | 全懋精密科技股份有限公司 | 半导体构装的芯片埋入基板结构及制法 |
CN103904044A (zh) * | 2014-04-02 | 2014-07-02 | 华进半导体封装先导技术研发中心有限公司 | 一种扇出型晶圆级封装结构及制造工艺 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI245350B (en) * | 2004-03-25 | 2005-12-11 | Siliconware Precision Industries Co Ltd | Wafer level semiconductor package with build-up layer |
US20080217761A1 (en) * | 2007-03-08 | 2008-09-11 | Advanced Chip Engineering Technology Inc. | Structure of semiconductor device package and method of the same |
WO2010041630A1 (ja) * | 2008-10-10 | 2010-04-15 | 日本電気株式会社 | 半導体装置及びその製造方法 |
TW201041469A (en) * | 2009-05-12 | 2010-11-16 | Phoenix Prec Technology Corp | Coreless packaging substrate, carrier thereof, and method for manufacturing the same |
TWI417970B (zh) * | 2009-09-04 | 2013-12-01 | Unimicron Technology Corp | 封裝結構及其製法 |
US20110215450A1 (en) * | 2010-03-05 | 2011-09-08 | Chi Heejo | Integrated circuit packaging system with encapsulation and method of manufacture thereof |
US8349658B2 (en) * | 2010-05-26 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframe |
KR101145041B1 (ko) * | 2010-10-19 | 2012-05-11 | 주식회사 네패스 | 반도체칩 패키지, 반도체 모듈 및 그 제조 방법 |
JP5636265B2 (ja) * | 2010-11-15 | 2014-12-03 | 新光電気工業株式会社 | 半導体パッケージ及びその製造方法 |
US8535983B2 (en) * | 2011-06-02 | 2013-09-17 | Infineon Technologies Ag | Method of manufacturing a semiconductor device |
US8610286B2 (en) * | 2011-12-08 | 2013-12-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming thick encapsulant for stiffness with recesses for stress relief in Fo-WLCSP |
TWI447872B (zh) * | 2011-12-16 | 2014-08-01 | 矽品精密工業股份有限公司 | 封裝結構、基板結構及其製法 |
US9391041B2 (en) * | 2012-10-19 | 2016-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out wafer level package structure |
US9373527B2 (en) * | 2013-10-30 | 2016-06-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip on package structure and method |
US20150115420A1 (en) * | 2013-10-31 | 2015-04-30 | Navas Khan Oratti Kalandar | Sensor die grid array package |
US9768038B2 (en) * | 2013-12-23 | 2017-09-19 | STATS ChipPAC, Pte. Ltd. | Semiconductor device and method of making embedded wafer level chip scale packages |
US9978700B2 (en) * | 2014-06-16 | 2018-05-22 | STATS ChipPAC Pte. Ltd. | Method for building up a fan-out RDL structure with fine pitch line-width and line-spacing |
US9543170B2 (en) * | 2014-08-22 | 2017-01-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages and methods of forming the same |
-
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1797726A (zh) * | 2004-12-20 | 2006-07-05 | 全懋精密科技股份有限公司 | 半导体构装的芯片埋入基板结构及制法 |
CN103904044A (zh) * | 2014-04-02 | 2014-07-02 | 华进半导体封装先导技术研发中心有限公司 | 一种扇出型晶圆级封装结构及制造工艺 |
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