TWI425602B - 包含矽補釘之用於高密度互連體之微電子封裝體及其製造方法 - Google Patents

包含矽補釘之用於高密度互連體之微電子封裝體及其製造方法 Download PDF

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TWI425602B
TWI425602B TW098110418A TW98110418A TWI425602B TW I425602 B TWI425602 B TW I425602B TW 098110418 A TW098110418 A TW 098110418A TW 98110418 A TW98110418 A TW 98110418A TW I425602 B TWI425602 B TW I425602B
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die
interconnect structure
microelectronic package
interconnect
substrate
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TW200950034A (en
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Ravi Mahajan
Sandeep Sane
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Intel Corp
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Description

包含矽補釘之用於高密度互連體之微電子封裝體及其製造方法 發明領域
本發明之所揭露實施例大體關於微電子封裝體，且尤其關於微電子封裝體中之電氣連接。
 發明背景
為了提高性能，中央處理單元(CPU)產品以一並列的或其他多晶片模組(MCM)的形式在CPU封裝體中逐漸整合多個晶粒。此種發展，隨同諸如長期存在的日益小型化的趨勢之其他因素，正導致微電子產業向這一情形發展：足夠數量的晶粒連接體(透過每層晶粒邊緣每毫米(mm)之輸入/輸出(I/O)來量測)適於納入可得空間可能不再可能。數量不足的晶粒連接體將限制受影響晶粒介面的頻寬性能，且從而損害邏輯元件與邏輯元件及/或邏輯元件與記憶體的通訊。目前演進的方法是透過調節受控崩潰晶片連接(controlled collapse chip connect,C4)互連體與基體之線寬(Line)/線間距(Space)來增加I/O的密度，這一方法很可能在將來至少是在一些應用中是不適用的。
依據本發明之一實施例，係特地提出一種微電子封裝體，其包含：一基體；嵌入於該基體中之一矽補釘；在該矽補釘之一第一位置處的一第一互連結構及在該矽補釘之一第二位置處的一第二互連結構；及在該矽補釘中互相連接該第一互連結構與該第二互連結構之一電氣導線。
圖式簡單說明
從下面詳細描述的閱讀中，結合在諸圖式中的附圖，可更好地理解所揭露之實施例，其中：第1圖是根據本發明之一實施例之一微電子封裝體的一平面視圖；第2圖是根據本發明之一實施例第1圖所示之該微電子封裝體的一截面視圖；第3-5圖是根據本發明之各種實施例第1及2圖所示之該微電子封裝體之一部分的截面視圖；及第6圖是根據本發明之一實施例說明製造一微電子封裝體之方法的一流程圖。
為了說明的簡易性及清晰性，諸圖式說明了建構的大致方法，且習知的特徵及技術的描述及細節可省略以避免不必要地模糊所描述的本發明之實施例的討論。此外，圖式中的元件不一定有按照比例繪製。例如，圖式中一些元件的尺寸可能相對於其他元件遭誇大以幫助促進對本發明之實施例的理解。不同圖式中相同的參照數字表示相同的元件，同時相似的參照數字可以(但是不必需)表示相似的元件。
在此等描述及申請專利範圍中，“第一”、“第二”、“第三”、“第四”等術語，如果有的話，可用於區別相似元件且不必用來描述一特定的連續的或有時間順序的次序。需要理解的是如此使用的該等術語在適當的環境下是可以互換的，以便例如本文所描述的本發明之實施例可按除本文所說明或所描述之順序以外的順序操作。類似地，如果一方法在本文描述為包含一系列的步驟，本文中所呈現的這些步驟的次序不必是這些步驟遭執行的僅有的次序，且某些所述的步驟可以省略及/或某些在本文中未描述的其他步驟可加入到該方法中。而且，“包含”、“包括”、“具有”等術語、及其任何變化，是打算涵蓋一未排除的包括，以便包含一元件列表的一程序、方法、物品、或裝置不必受限於這些元件，而可包括未明確列出的其他元件或對於該程序、方法、物品、或裝置來說固有的元件。
在此等描述或申請專利範圍中的“左”、“右”、“前”、“後”、“頂部”、“底部”、“之上”、“之下”等術語，如果有的話，是以描述之目的來使用且不必用於描述永久的相對位置。需要理解的是如此使用的該等術語在適當的環境下是可以互換的，以便例如本文所描述的本發明之諸實施例可按本文所說明或所描述之方位以外的方位操作。本文使用的術語“耦接”，遭定義為以電氣的或非電氣的方式直接或間接連接。本文中所描述的諸如互相“相鄰”的物件可是互相實體接觸、互相緊鄰、或互相在相同的大致的區或區域中，按該措辭所用之脈絡而適當取義。本文中措辭“在一實施例中”的出現不一定是指同一實施例。
 較佳實施例之詳細說明
在本發明之一實施例中，一微電子封裝體包含一基體、嵌入於該基體的一矽補釘、在該矽補釘之一第一位置的一第一互連結構及在該矽補釘之一第二位置的一第二互連結構、及該矽補釘中互相連接該第一互連結構與該第二互連結構之一電氣導線。
本發明之實施例可提供I/O密度的顯著增加且從而在一微電子封裝體中晶粒之間通訊頻寬的顯著增加。大體而言，本發明之實施例嵌入具有高密度的焊點凸塊和細線之矽片，其中，該等矽片使用傳統的矽製程來製造。與邏輯元件或記憶晶粒之組配可使用在該技藝中所習知的傳統的組配製程。
作為一範例，一節距(pitch)為150微米(又記作“microns”或“μm”)線寬/線間距為10μm的最小互連體產生大約為每層每毫米28個I/O的一I/O密度。如果這些值縮小至例如節距為80μm及線寬/線間距為2μm，該I/O密度將增加至大約每層每毫米100個I/O。這一I/O密度除了將提供通訊頻寬的明顯增加外，(至少部分地)由於矽製程技術的成熟，本發明之實施例還使組配製程能夠改善。因此，本發明之實施例提供了一新方法用以在邏輯元件與邏輯元件晶粒及/或邏輯元件與記憶體晶粒間製造高密度的互連體，從而使所需的高頻寬的互連能夠滿足未來的需要。
此外，由於位於一最大距中性點距離(DNP)處與別處之凸塊的減小的熱膨脹係數(CTE)失配，本發明之實施例可使得總的機械可靠性改善(例如，凸塊破裂、層間介電材料ILD失效等的降低)。作為一範例，且如下文進一步討論的，將矽嵌入一封裝基體中，依所嵌入矽的幾何而定，可降低基體的有效熱膨脹係數(CTE)至與關聯的晶粒之CTE更匹配的一值。除了上面所提到的那些優勢以外，有效基體CTE的降低還具有多個潛在的機械優勢，包括轉移至矽後端互連層中之易損壞的低介電值(low-k)層間介電材料上之應力的降低、組配後翹曲的降低，及在可靠性測試中熱介電材料(TIM)應力的降低。
現在參照圖式，第1圖是根據本發明之一實施例之一微電子封裝體100的一平面圖。如第1圖中所說明，微電子封裝體100包含一基體110及遭嵌入於基體110中的一矽補釘120。微電子封裝體100進一步包含矽補釘120中之一位置141處的一互連結構131、矽補釘120中之位置142處的一互連結構132，及矽補釘120中互相連接互連結構131及互連結構132的一電氣導線150。在所說明的實施例中，互連結構131是位於位置141處的多個互連結構之一及互連結構132是位於位置142處的多個互連結構之一。作為一範例，此等多個互連結構可設計成使互連體的數量最大化成為可能。
作為一範例，基體110可是在該技藝中所習知之傳統的有機基體。作為另一範例，互連結構131及/或互連結構132可包含一銅柱等。在一實施例中，該銅柱包含一互鎖形貌部，在接下來的圖式中將描繪且在下面將進一步討論。
作為另一範例，電氣導線150的寬度(及在本文中所描述之所有相似的電氣導線的寬度)可不大於大約0.2微米(又記作“microns”)，同時至少一對相鄰互連結構之間的間距(即節距)不大於80微米。對於本技藝中具有通常知識者顯而易見的是，這樣的節距及線寬明顯小於透過用於聚合層中銅線的目前可得之技術所可能得到的值。根據本發明之實施例在基體中嵌入矽的一優點在於矽製程已經獲提高到一程度使得如此小的節距及線寬在目前技術範圍之內。
微電子封裝體100還進一步包含基體110上的一晶粒161及一晶粒162。第1圖中，晶粒161及晶粒162的輪廓用虛線顯示，表明他們位於矽補釘120及基體110之上。換句話說，第1圖描繪晶粒161及晶粒162好像它們是透明的(除了它們的輪廓)以使下面的細節可以被看清。大體而言，位置141是矽補釘120之在晶粒161之下的區域且位置142是矽補釘120之在晶粒162之下的區域。
第1圖還描繪了連接一未標示的互連結構對(一個來自位置141及一個來自位置142)之一電氣導線155，且進一步描繪了附加的矽補釘170、附加的互連結構180及附加的晶粒190。要注意的是在第1圖中僅有一些附加的互連結構180用參考數字表明；圖式中未標示的互連結構180基於與那些已標示的互連結構180之外觀的類似性應該可以輕易識別。作為一範例，矽補釘170中之每一個可類似於矽補釘120。在一實施例中，為了避免其他原因可能導致之潛在可撓性問題，矽補釘170不會互相重疊或接觸。作為另一範例，互連結構180中之每一個可類似於互連結構131及/或互連結構132。作為又一範例，晶粒190之每一個可類似於晶粒161及/或晶粒162。
實際上，諸如電氣導線150及155的大量的電氣導線將遭緊密地封裝於所嵌入的矽補釘中，致能非常低的節距及非常高密度的互連體。這些互連體的RC行為可使用傳統的矽製造製程來管理。
第2圖是沿著第1圖中的線II-II得到的微電子封裝體100的截面視圖。第2圖中可見的是基體110、矽補釘120、各自的位置141及142處的互連結構131及132、電氣導線150及155、晶粒161及162、附加的矽補釘170之一，及附加的晶粒190之一。為了第2圖的清晰性，矽補釘120及170用交叉底線標記顯示。需要注意的是該等交叉底線標記在那些矽補釘於第1圖中描繪時並未予以顯示。
如第2圖中所說明，電氣導線150及155延伸進入矽補釘120至相同的深度。另一方面，矽補釘170包含一對在矽補釘170中延伸至不同深度的電氣導線(未標示)。這些安排之一或兩者，或一些其他安排，根據本發明之各種實施例，可用於矽補釘中的電氣導線中。在一實施例中，該等矽補釘其自身在基體中的深度可在大約70至100微米之間。
如第2圖中進一步說明，基體110包含其中具有一緩衝材料210的一井(或多個井)。矽補釘120(及矽補釘170)遭嵌入於該井中與緩衝材料210相鄰。作為一範例，緩衝材料可以是提供一適應的緩衝墊層(具有連接性)以便在矽補釘120及170的矽與基體110的有機材料間提供一應力緩衝之一基於聚矽氧(silicone-based)之材料或類似材料。無論它的成分如何，緩衝材料210都用於減輕由於該兩種材料間的CTE失配所產生的，該等矽補釘及該基體兩者所經歷之CTE應力的程度。
繼續CTE失配的主題，在此提及基體110中矽補釘120及170的存在可將基體110的有效CTE的值從大約每凱氏度百萬分之17(ppm/°K)(不含該等矽補釘)降低至包含該等矽補釘情況下的大約10-12ppm/°K可能是有幫助的。(具有遭嵌入的矽補釘之基體的實際CTE值視所嵌入的矽的幾何而定)。有效基體CTE之降低的多個優勢在上面已提出。
在所說明之實施例中，微電子封裝體100進一步包含基體110中的電氣導線220。(為了簡易之目的，這些在基體110中描繪為終止，未與任何事物相連接，但是在實際中，當然，會繼續且實現它們預期的電氣連接。)根據微電子封裝體100的設計要求，電氣導線220可以在所描繪的位置及/或按需要在其他的位置。作為一範例，電氣導線220可以是電力線且，照這樣，可以在數量上小於及/或由於要運載較高的電流，在尺寸上大於電氣導線150及155(如上面所提及的，電氣導線150及155遭設計用於封裝體晶粒間的高頻寬、高密度的匯流排的連接。)應理解的是，一些或所有的電氣導線220都可遭替代用於其他目的，且進一步應理解的是，電氣導線220可置位於矽補釘之外(如所描繪的)，或在矽補釘之內。
第2圖中的一形貌部275包含互連結構131且進一步包含一電氣傳導結構231及(在一些情況下)各種其他附加結構及/或細節，正如現在將結合第3-5圖(此等圖式是根據本發明之各種實施例，微電子封裝體100之所指出部分的截面視圖)來描述的。這些細節未包括於第2圖中，因為此圖式的較小比例不易允許將它們包含於其中，且也因為第2圖是打算充分概括地包含形貌部275的多個可能組態。類似地，第2圖中所描繪的某些細節可從第3-5圖中省略。作為一範例，電氣傳導結構231可類似於電氣傳導互連結構131。
第3圖說明了一焊料凸塊310位於電氣傳導互連結構131及電氣傳導結構231之間的一實施例。銅柱(或其他互連結構)間的一焊料凸塊可使用習知的製程來形成，其製造相對簡單，且適於自行對齊，及其它可能的優點。
第4圖說明了一實施例，在此實施例中，互連結構131及電氣傳導結構231使用藉以促進擴散接合的方法遭壓合在一起。作為一範例，本製程可降低附接的溫度且改變接點及整體結構中應力的產生狀態。
第5圖說明了一實施例，在此實施例中，互連結構131及電氣傳導結構231具有諸如顯示的那些形成鳩尾型接點之互鎖形貌部，其中互連結構131上的一突起510遭設計以適於進入電氣傳導結構231中的一開口520，從而使兩個互連結構互鎖在一起。作為一範例，本技術可改善所接合的兩矽實體的對齊。許多其他類型的互鎖形貌部也是可能的，如本技藝中具有通常知識者將認識到的。
第6圖是根據本發明之一實施例說明製造一微電子封裝體之一方法600的一流程圖。方法600中步驟610是提供具有一矽補釘遭嵌入於其中的一基體。作為一範例，此基體可類似於基體110且此矽補釘可類似於矽補釘120，其兩者第一次顯示是於第1圖中。
方法600中步驟620是在矽補釘的一第一位置處形成一第一互連結構，及在矽補釘的一第二位置處形成一第二互連結構。作為一範例，第一互連結構可類似於互連結構131，且第二互連結構可類似於互連結構132，其兩者第一次顯示是於第1圖中。
方法600中步驟630是互相電氣連接第一互連結構與第二互連結構。
方法600中步驟640是在第一位置之上提供一第一晶粒，及在第二位置之上提供一第二晶粒。作為一範例，第一晶粒可類似於晶粒161，且第二晶粒可類似於晶粒162，其兩者第一次顯示是於第1圖中。
方法600中步驟650是互相電氣連接第一晶粒與第一互連結構。在一實施例中，步驟650包含，在第一晶粒處提供一第一電氣傳導結構，及在第一電氣傳導結構與第一互連結構間提供一第一焊料接點。作為一範例，第一電氣傳導結構可類似於電氣傳導結構231，其第一次顯示是於第2圖中。作為另一範例，第一焊料接點可類似於焊料凸塊310，其第一次顯示是於第3圖中。在另一實施例中，步驟650包含將第一電氣傳導結構與第一互連結構壓合在一起以在其間形成一擴散接合。
在一不同的實施例中，第一互連結構具有一第一互鎖形貌部，且第一電氣傳導結構具有一第三互鎖形貌部。作為一範例，第一互鎖形貌部可類似於突起510，且第三互鎖形貌部可類似於開口520，其兩者第一次顯示是於第5圖中。在此實施例中，步驟650可包含互鎖第一互鎖形貌部及第三互鎖形貌部。
方法600中步驟660是互相電氣連接第二晶粒與第二互連結構。在一實施例中，步驟660及步驟650可作為同一步驟之部分而遭執行，且可在同一實施例或另一實施例中同時遭執行。在同一實施例或另一實施例中，步驟660包含在第二晶粒處提供一第二電氣傳導結構，且在第二電氣傳導結構與第二互連結構間提供一第二焊料接點。作為一範例，第二電氣傳導結構可類似於電氣傳導結構231，其第一次顯示是於第2圖中。作為另一範例，第二焊料接點可類似於焊料凸塊310，其第一次顯示是於第3圖中。在另一實施例中，步驟660包含將第二電氣傳導結構與第二互連結構壓合在一起以在其間形成一擴散接合。
在一不同的實施例中，第二互連結構具有一第二互鎖形貌部，且第二電氣傳導結構具有一第四互鎖形貌部。作為一範例，第二互鎖形貌部可類似於突起510，且第四互鎖形貌部可類似於開口520，其兩者第一次顯示是於第5圖中。在此實施例中，步驟660可包含互鎖第二互鎖形貌部及第四互鎖形貌部。
應該理解的是前述的步驟是對本發明之一實施例的說明，如所提及的一樣，且在不超出本發明之範圍的情況下可用各種方式進行改變。僅作為一範例，步驟650及/或步驟660可先於步驟630的執行而遭執行。換句話說，第一晶粒與第一互連結構及/或第二晶粒與第二互連結構，可在第一與第二互連結構互相電氣連接之前互相電氣連接。
雖然本發明已經參照特定的實施例描述，但是本技藝中具有通常知識者將理解的是，可做出各種改變而不背離本發明之精神或範圍。因此，本發明之實施例之揭露內容打算是說明本發明之範圍且不打算是限制性的。其意圖在於應該將本發明之範圍僅限於後附申請專利範圍所要求的範圍中。例如，對於在本技藝中具有通常知識者顯而易見的是，該等微電子封裝體及本文中討論的相關的方法可使用各種實施例來實現，且前面對某些實施例之討論未必表現所有可能的實施例之全部描述。
另外，利益、其他優點、及問題的解決方法已經針對特定的實施例描述。然而，該等利益、優點、問題的解決方法、及可能使得任何利益、優點、或問題的解決方法產生或變得越加明顯的任何元件或多個元件，不能理解為是任一或所有申請專利範圍之關鍵的、必須的、或實質的特徵或元件。
此外，依據奉獻原則，本文所揭露之實施例及限制條件不奉獻給公眾，如果該等實施例及/或限制條件：(1)在申請專利範圍中未明確主張；及(2)依據均等論，是或可能是申請專利範圍中明確的元件及/或限制條件之等效物。
100．．．微電子封裝體
110．．．基體
120．．．矽補釘
131、132．．．互連結構
141、142．．．位置
150、155、220．．．電氣導線
161、162．．．晶粒
170．．．附加矽補釘
180．．．附加互連結構
第1圖是根據本發明之一實施例之一微電子封裝體的一平面視圖；
第2圖是根據本發明之一實施例第1圖所示之該微電子封裝體的一截面視圖；
第3-5圖是根據本發明之各種實施例第1及2圖所示之該微電子封裝體之一部分的截面視圖；及
第6圖是根據本發明之一實施例說明製造一微電子封裝體之方法的一流程圖。
100．．．微電子封裝體
110．．．基體
120．．．矽補釘
131、132．．．互連結構
141、142．．．位置
150、155．．．電氣導線
161、162．．．晶粒
170．．．附加矽補釘
180．．．附加互連結構
190．．．附加晶粒

Claims (20)

  1. 一種微電子封裝體，其包含：一基體；嵌入於該基體中之一矽補釘；在該矽補釘之一第一位置處的一第一互連結構及在該矽補釘之一第二位置處的一第二互連結構；及在該矽補釘中互相連接該第一互連結構與該第二互連結構之一電氣導線。
  2. 如申請專利範圍第1項所述之微電子封裝體，其中：該基體包含內有一緩衝材料的一井；及該矽補釘係嵌入於該井中與該緩衝材料相鄰。
  3. 如申請專利範圍第1項所述之微電子封裝體，其中：該等第一及第二互連結構中的至少一個包含一銅柱。
  4. 如申請專利範圍第3項所述之微電子封裝體，其中：該銅柱包含一互鎖形貌部。
  5. 如申請專利範圍第1項所述之微電子封裝體，其中：該電氣導線之一寬度不大於0.2微米。
  6. 如申請專利範圍第1項所述之微電子封裝體，其進一步包含：在該基體中之一電力線。
  7. 如申請專利範圍第1項所述之微電子封裝體，其中：該基體具有在10ppm/°K到12ppm/°K之間的一有效熱膨脹係數。
  8. 一種微電子封裝體，其包含： 一基體；該基體之上的一第一晶粒及一第二晶粒；嵌入於該基體中之一矽補釘；于該矽補釘中位於該第一晶粒下之第一多個互連結構及于該矽補釘中位於該第二晶粒下之第二多個互連結構；及把該等第一多個互連結構中之一第一互連結構及該等第二多個互連結構中之一第一互連結構加以互相連接的一電氣導線。
  9. 如申請專利範圍第8項所述之微電子封裝體，其中：該基體包含內有一緩衝材料的一井；及該矽補釘係嵌入於該井中與該緩衝材料相鄰。
  10. 如申請專利範圍第9項所述之微電子封裝體，其中：該等第一及第二多個互連結構之至少其中之一中的至少一對相鄰互連結構間的一間距不大於80微米。
  11. 如申請專利範圍第9項所述之微電子封裝體，其中：該基體具有在10ppm/°K到12ppm/°K之間的一有效熱膨脹係數。
  12. 如申請專利範圍第9項所述之微電子封裝體，其中：該等第一及第二多個互連結構中每一互連結構包含一銅柱。
  13. 如申請專利範圍第12項所述之微電子封裝體，其中：該等銅柱中的至少一個包含一互鎖形貌部。
  14. 如申請專利範圍第12項所述之微電子封裝體，其中： 該電氣導線之一寬度不大於0.2微米。
  15. 如申請專利範圍第14項所述之微電子封裝體，其進一步包含：在該基體中之一電力線。
  16. 一種製造微電子封裝體之方法，該方法包含以下步驟：設置具有一矽補釘嵌入於其中之一基體；在該矽補釘之一第一位置處形成一第一互連結構及在該矽補釘之一第二位置處形成一第二互連結構；及互相電氣連接該第一互連結構與該第二互連結構。
  17. 如申請專利範圍第16項所述之方法，其進一步包含：在該第一位置之上設置一第一晶粒及在該第二位置之上設置一第二晶粒；互相電氣連接該第一晶粒與該第一互連結構；及互相電氣連接該第二晶粒與該第二互連結構。
  18. 如申請專利範圍第17項所述之方法，其中：互相電氣連接該第一晶粒與該第一互連結構之步驟包含：在該第一晶粒處設置一第一電氣傳導結構；及在該第一電氣傳導結構與該第一互連結構之間設置一第一焊料接合點；及互相電氣連接該第二晶粒與該第二互連結構之步驟包含：在該第二晶粒處設置一第二電氣傳導結構；及在該第二電氣傳導結構與該第二互連結構之間設置一第二焊料接合點。
  19. 如申請專利範圍第17項所述之方法，其中：互相電氣連接該第一晶粒與該第一互連結構之步驟包含：在該第一晶粒處設置一第一電氣傳導結構；及將該第一電氣傳導結構與該第一互連結構壓合在一起；及互相電氣連接該第二晶粒與該第二互連結構之步驟包含：在該第二晶粒處設置一第二電氣傳導結構；及將該第二電氣傳導結構與該第二互連結構壓合在一起。
  20. 如申請專利範圍第17項所述之方法，其中：該第一互連結構具有一第一互鎖形貌部；該第二互連結構具有一第二互鎖形貌部；互相電氣連接該第一晶粒與該第一互連結構之步驟包含：在該第一晶粒處設置一第一電氣傳導結構，該第一電氣傳導結構具有一第三互鎖形貌部；及把該第一互鎖形貌部及該第三互鎖形貌部加以互鎖；及互相電氣連接該第二晶粒與該第二互連結構之步驟包含：在該第二晶粒處設置一第二電氣傳導結構，該第二電氣傳導結構具有一第四互鎖形貌部；及把該第二互鎖形貌部及該第四互鎖形貌部予以互鎖。
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GB201015981D0 (en) 2010-11-03
JP2011515842A (ja) 2011-05-19
TW200950034A (en) 2009-12-01
KR20100116689A (ko) 2010-11-01
KR101182010B1 (ko) 2012-09-11
US8064224B2 (en) 2011-11-22
DE112009000351B4 (de) 2014-07-17
WO2009146007A2 (en) 2009-12-03
CN101960589B (zh) 2012-10-10
WO2009146007A3 (en) 2010-01-21
CN101960589A (zh) 2011-01-26
US20090244874A1 (en) 2009-10-01
DE112009000351T5 (de) 2011-05-05
GB2470866A (en) 2010-12-08
US20110241208A1 (en) 2011-10-06
US8441809B2 (en) 2013-05-14
GB2470866B (en) 2012-10-03
DE112009005519A5 (de) 2014-12-31

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