CN104241258B - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN104241258B
CN104241258B CN201410249835.0A CN201410249835A CN104241258B CN 104241258 B CN104241258 B CN 104241258B CN 201410249835 A CN201410249835 A CN 201410249835A CN 104241258 B CN104241258 B CN 104241258B
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CN
China
Prior art keywords
semiconductor chip
silicon hole
circuit
wiring plate
semiconductor
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Expired - Fee Related
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CN201410249835.0A
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CN104241258A (zh
Inventor
山道新太郎
小川健太
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of CN104241258A publication Critical patent/CN104241258A/zh
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Expired - Fee Related legal-status Critical Current
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Abstract

本发明涉及半导体器件。本发明能够减少在第一半导体芯片中产生并通过硅通孔传递到第二半导体芯片的热量。第一半导体芯片具有第一硅通孔。每个第一硅通孔被布置于成m行和n列(m>n)排布的网格点中的任意一个上。第一半导体芯片还具有第一电路形成区。第一电路被形成于第一电路形成区内。第一电路在与第二半导体芯片通信的同时执行信号处理。在平面图中，第一电路形成区不与通过耦接成m行和n列排布的最外侧网格点来界定的硅通孔区重叠。在平面图中，一些连接端子位于第一电路形成区与硅通孔区之间。

Description

半导体器件
相关申请的交叉引用
在2013年6月6日提交的日本专利申请No.2013-119998的公开内容，包括说明书、附图和摘要，全文通过引用并入本文。
技术领域
本发明涉及半导体器件，并且例如是可应用于其中第一半导体芯片和第二半导体芯片堆叠于布线板之上的半导体器件的技术。
背景技术
一种用于将多个半导体芯片封装于布线板之上的方法采用将第二半导体芯片堆叠于第一半导体芯片之上。日本未经审核的专利公开No.2005-183934公开了通过凸点将第二半导体芯片耦接至第一半导体芯片的技术。
另一方面，通过使用硅通孔(silicon-through via)将半导体芯片耦接至另一个半导体芯片的方法正在研究中。硅通孔被设置，以便沿着基板的厚度穿过半导体芯片的基板。例如，日本未经审核的专利公开No.2011-243724所公开的方法包括：堆叠各自具有形成于其内的硅通孔的存储器芯片，并且使用硅通孔来耦接这些存储器芯片。
在日本未经审核的专利公开No.2011-243724中，最下层的存储器芯片通过焊料凸点耦接至布线板。在最下层的存储器芯片周围，设置了框架状的金属部件，以便包封存储器芯片。另外，金属基板还被安装于最上层的存储器芯片之上，粘接部件位于它们之间。在该专利公开中提供了框架状的部件，以便增加布线板的刚度。
发明内容
如果第二半导体芯片被安装于第一半导体芯片之上，则第二半导体芯片的散热性能会下降。因此，本发明的发明人已意识到需要尽可能地防止热量传递到第二半导体芯片。尤其是在第一半导体芯片和第二半导体芯片通过设置于第一半导体芯片内的硅通孔相互耦接的情况下，本发明人已意识到需要防止在第一半导体芯片中产生的热量通过硅通孔传递到第二半导体芯片。根据下面在本说明书及附图中的描述，本发明的其他问题及新特征将变得显而易见。
根据一种实施例，第一半导体芯片被安装于布线板的第一表面之上并且在平面图中是矩形的。第一半导体芯片具有面朝布线板的第一表面的元件形成表面。第一半导体芯片通过连接端子耦接至布线板。第一半导体芯片具有多个第一硅通孔。每个第一硅通孔被布置于成m行和n列(m>n)排布的网格点中的任意一个上。第二半导体芯片被布置于第一半导体芯片之上并且与第一半导体芯片的第一硅通孔电耦接。第一半导体芯片还具有第一电路形成区。第一电路被形成于第一电路形成区内。第一电路在与第二半导体芯片通信的同时执行信号处理。在平面图中，第一电路形成区不与硅通孔区重叠，其中硅通孔区通过耦接排布成m行和n列排布的最外侧网格点来界定。在平面图中，一些连接端子被定位于第一电路形成区与硅通孔区之间。
本实施例能够减少在第一半导体芯片中产生的热量通过硅通孔至第二半导体芯片的传递。
附图说明
图1是示出根据一种实施例的半导体器件的配置的截面图。
图2示意性地示出了用于形成半导体器件的布线板、第一半导体芯片及第二半导体芯片的相对位置。
图3是示出其中第一半导体芯片与布线板耦接的部分以及其中第一半导体芯片与第二半导体芯片耦接的部分的配置的截面图。
图4示出了第一硅通孔在硅通孔区内的示例性布局。
图5示出了布线板的开口的示例性形状。
图6A至6C示出了用于制造半导体器件的方法。
图7A和7B示出了用于制造半导体器件的方法。
图8是示出布线板的配置的平面图。
图9是示出根据第一改型的半导体器件的配置的截面图。
图10示出了第二半导体芯片的截面结构。
图11是示出根据第二改型的半导体器件的配置的平面图。
图12是根据第三改型的电子器件的平面图。
图13是示出图12所示的电子器件的功能配置的框图。
具体实施方式
下面将参照附图来描述实施例。注意，在所有附图中，相似的构件以相似的附图标记来指示，并且因此如果不必要，则将不重复关于它们的解释。
[实施例]
图1是示出根据第一实施例的半导体器件SD的配置的截面图。图2示意性地示出了用于形成半导体器件SD的布线板IP、第一半导体芯片SC1及第二半导体芯片SC2的相对位置。图1对应于沿着图2中的A-A'截取的截面。根据第一实施例的半导体器件SD包括布线板IP、第一半导体芯片SC1及第二半导体芯片SC2。
第一半导体芯片SC1被安装于布线板IP的第一表面之上并且在平面图中是矩形的。第一半导体芯片SC1具有面朝第一表面的元件形成表面SFC11。第一半导体芯片SC1通过连接端子CUP耦接至布线板IP。
第一半导体芯片SC1具有多个第一硅通孔TSV1。每个第一硅通孔TSV1都被布置于成m行和n列(m>n)排布的网格点中的任意一个上。在图1和2所示的示例中，与第一半导体芯片SC1的长边SID11、SID13平行的方向(在图2中的X方向)被定义为列方向，并且与长边SID11、SID13垂直的方向(在图2中的Y方向)被定义为行方向。但是，行方向可以是与第一半导体芯片SC1的短边SID12、SID14平行的方向。
第二半导体芯片SC2被布置于第一半导体芯片SC1之上并且与第一半导体芯片SC1的第一硅通孔TSV1电耦接。
第一半导体芯片SC1还具有第一电路形成区LGC1。第一电路被形成于第一电路形成区LGC1内。第一电路在与第二半导体芯片SC2通信的同时执行信号处理。在平面图中，第一电路形成区LGC1不与通过耦接成m行和n列排布的最外侧网格点而界定的区域(在下文，称为硅通孔区TSVA1)重叠。在平面图中，一些连接端子CUP被定位于第一电路形成区LGC1与硅通孔区TSVA1之间。该布局允许在第一电路形成区LGC1内产生的热量的至少一部分通过连接端子CUP传递到布线板IP。因此，能够减少通过第一硅通孔TSV1从第一半导体芯片SC1传递到第二半导体芯片SC2的热量。
如上所述，第一半导体芯片SC1的元件形成表面SFC11面朝布线板IP的第一表面。该布局使得与元件形成表面SFC11面朝第二半导体芯片SC2的情形相比较第二半导体芯片SC2更不容易受来自第一半导体芯片SC1的热量所影响。该布局还使得热量容易从第一半导体芯片SC1传递到布线板IP。
下面将详细地描述半导体器件SD的配置。
下面将参照图1来描述半导体器件SD的配置。布线板IP是例如在至少两个面上具有布线层的树脂内插板(interposer)。布线板IP可以具有两个布线层或者四个或更多个布线层。布线板IP的厚度为例如100～300μm。但是，布线板IP能够比那些厚度更厚或更薄。在布线板IP的第一表面一侧(即，第一半导体芯片SC1安装于其上的那一侧)的布线包括电极IEL(该电极IEL将在后面参照图3来描述)。电极IEL与第一半导体芯片SC1电耦接。
布线板IP在第二表面上具有布线层，该第二表面是第一表面的相对面，并且电极LND被布置于在第二表面上的布线层之上。电极LND至少通过设置于布线板IP内的耦接部件(例如，设置于通孔内的导电层)与电极IEL耦接。外部连接端子SB被设置于电极LND之上。外部连接端子SB被用来将半导体器件SD附接至电路板(例如，主板)。外部连接端子SB是例如焊球。电极LND和外部连接端子SB至少沿着布线板IP的边缘排布。但是，电极LND和外部连接端子SB能够另外布置于布线板IP的中心。在这种情况下，电极LND和外部连接端子SB可以设置于布线板IP的整个表面上，或者排布于布线板IP的中心的一组外部连接端子SB与排布于布线板IP的边缘的一组外部连接端子SB可以在它们之间具有间隔，该间隔大于在各个组的网格点之间的距离。
如上所述，第一半导体芯片SC1与布线板IP的电极IEL耦接。在附图所示的实例中，第一半导体芯片SC1经由连接端子CUP耦接至电极IEL。连接端子CUP是例如由金属(例如，Cu)制成的导体柱。但是，焊料凸点同样能够被用作连接端子。
第一半导体芯片SC1具有比布线板IP薄的厚度，或者是例如布线板IP的厚度的一半或更薄。第一半导体芯片SC1的厚度是例如50～60μm，但并不仅限于此。
第一半导体芯片SC1比第二半导体芯片SC2薄。因此，第一硅通孔TSV1是相对较短的，由此使热量更容易地从第一半导体芯片SC1传递到第二半导体芯片SC2。
在第一半导体芯片SC1的元件形成表面SFC11之上，形成了至少一个逻辑电路(例如，在第一电路形成区LGC1内的电路)。该逻辑电路经由第一硅通孔TSV1耦接至第二半导体芯片SC2。
第二半导体芯片SC2是例如存储器芯片。包含于第二半导体芯片SC2内的存储器可以是WideI/O存储器或双倍数据率(DDR)存储器(例如，DDR2和DDR3)。但是，第二半导体芯片SC2能够是具有逻辑电路的半导体芯片或者是具有逻辑电路和存储器电路两者的半导体芯片。第二半导体芯片SC2具有面朝第一半导体芯片SC1的背表面SFC12的元件形成表面SFC21。
在图1所示的实例中，硅通孔区TSVA1与第一半导体芯片SC1的中心、第二半导体芯片SC2的中心及布线板IP的中心对齐，这可从沿着第一半导体芯片SC1的短边截取的截面看出。但是，第一半导体芯片SC1、第二半导体芯片SC2及布线板IP的相对位置并不限定于图1所示的实例。
在第一半导体芯片SC1与布线板IP的第一表面之间的间隔以第一密封树脂UFR1密封。在第二半导体芯片SC2与布线板IP的第一表面之间的间隔同样以第二密封树脂UFR2密封。因此，第一密封树脂UFR1被覆盖着第二密封树脂UFR2。第一密封树脂UFR1可以是管芯附着膜(DAF)，或者可以通过滴落液体树脂来形成。第二密封树脂UFR2通过例如滴落液体树脂来形成。
第一密封树脂UFR1的厚度，换言之，在第一半导体芯片SC1与布线板IP之间的距离，优选地小于第二密封树脂UFR2的厚度，换言之，在第一半导体芯片SC1与第二半导体芯片SC2之间的距离。较薄的第一密封树脂UFR1允许更多的热量从第一半导体芯片SC1传递到布线板IP，而较厚的第二密封树脂UFR2能够减少从第一半导体芯片SC1传递到第二半导体芯片SC2的热量。
另外，第一密封树脂UFR1的热导率优选地高于第二密封树脂UFR2的热导率。具有较高热导率的第一密封树脂UFR1能够进一步增加从第一半导体芯片SC1传递到布线板IP的热量。因此，通过第二密封树脂UFR2从第一半导体芯片SC1传递到第二半导体芯片SC2的热量被进一步减少。
布线板IP的第一表面、第一半导体芯片SC1、第二密封树脂UFR2及第二半导体芯片SC2以密封树脂MDR1密封。在图1所示的实例中，密封树脂MDR1具有与布线板IP的侧表面齐平(flush)的侧表面。但是，可从平面图看出，密封树脂MDR1的侧表面与布线板IP的侧表面相比能够被定位于更内侧。
下面将参照图2来描述半导体器件SD的配置。第一半导体芯片SC1在平面图中是矩形的，并且具有长边SID11、短边SID12、长边SID13和短边SID14。第一硅通孔TSV1位于通过耦接成m行和n列排布的最外侧网格点来界定的硅通孔区TSVA1内，并且分别排布于网格点上。硅通孔区TSVA1是具有与第一半导体芯片SC1的短边SID12、SID14平行的长边(即，行方向)的矩形。第一电路形成区LGC1位于硅通孔区TSVA1的长边与短边SID12之间。根据该布局，第一电路形成区LGC1能够位于远离硅通孔区TSVA1之处。在由第一半导体芯片SC1所拥有的电路当中，在第一电路形成区LGC1内的第一电路产生了最大量的热量。因此，在第一半导体芯片SC1内的温度上升至最高的区域是在平面图中与第一电路重叠的区域。第一电路是例如中央处理单元(CPU)。
硅通孔区TSVA1的长边能够与第一半导体芯片SC1的长边SID11、SID13平行。
在沿着第一半导体芯片SC1的短边截取的截面中可看出，第一半导体芯片SC1的中心(或重心)与布线板IP的中心(或重心)对齐。
另外，一些连接端子CUP(即，连接端子CUP1)沿着第一半导体芯片SC1的四个边(长边SID11、短边SID12、长边SID13和短边SID14)布置。在图2所示的实例中，连接端子CUP1沿着第一半导体芯片SC1的四个边布置，以致于形成多条线。
一些连接端子CUP(即，连接端子CUP2)位于第一电路形成区LGC1与硅通孔区TSVA1之间。由于该布局，在第一电路形成区LGC1内产生的热量的至少一部分能够在到达第一硅通孔TSV1之前通过连接端子CUP2散逸到布线板IP。即使对第一半导体芯片SC1施加应力，连接端子CUP2也能够防止硅通孔区TSVA1遭受到翘曲。因此，能够防止第一半导体芯片SC1的基板SUB1从硅通孔区TSVA1开始开裂。连接端子CUP2能够具有比连接端子CUP1更大的截面积。连接端子CUP2的较大的截面积增加了上述效应。在图2所示的实例中，连接端子CUP2被排布为包围着硅通孔区TSVA1。
在平面图中，连接端子CUP1的总面积大于第一硅通孔TSV1的总面积。这使得热量更加难以从第一半导体芯片SC1传递到第二半导体芯片SC2，同时使得热量更加易于从第一半导体芯片SC1传递到布线板IP。
至少一些连接端子CUP2能够通过形成于第一半导体芯片SC1的多层互连层MIL内的导线和通孔耦接至第一硅通孔TSV1。在这种情况下，与电极EL11直接耦接的连接端子CUP2与第二半导体芯片SC2的功率电极或接地电极耦接。
其他连接端子CUP可以设置于连接端子CUP2的外面。连接端子CUP同样能够通过形成于第一半导体芯片SC1的多层互连层MIL内的导线和通孔耦接至第一硅通孔TSV1。这些连接端子同样能够用作例如用于测试第二半导体芯片SC2的端子。
在布线板IP之上的电极IEL同样被排布从而与连接端子CUP相对应。
第二半导体芯片SC2在平面图中比第一半导体芯片SC1的至少一个边向外延伸得更远。在图2所示的实例中，第二半导体芯片SC2的长边与第一半导体芯片SC1的短边SID12平行。
在第二半导体芯片SC2是存储器芯片的情况下，第一硅通孔TSV1按照JEDECJESD229所给出的规范来排布。因此，这四个硅通孔区TSVA1被排布为两行和两列。另外，在平面图中，第一半导体芯片SC1在硅通孔区TSVA1周围的区域内具有控制电路形成区CNT。在控制电路形成区CNT中，存储器控制电路被形成用于控制第二半导体芯片SC2的存储器。在用于耦接存储器控制电路和第二半导体芯片SC2的耦接通路当中，该布局能够缩短形成于第一半导体芯片SC1的多层互连层MIL内的耦接通路。
在平面图中，第二电路形成区LGC2被排布为关于硅通孔区TSVA1与第一电路形成区LGC1相对。第二电路形成于第二电路形成区LGC2内。第二电路与第一电路相比产生较少量的热量，但是热量产生量大于在控制电路形成区CNT中的电路的热量产生量。第二电路是例如图形处理单元(GPU)。
而且，在平面图中，I/O电路IF被形成于接近于第一电路形成区LGC1的短边(即，在图2中的短边SID12)与第一电路形成区LGC1之间。另一个I/O电路IF被形成于沿短边SID14布置的连接端子CUP1与第二电路形成区LGC2之间。由I/O电路IF产生的热量比由第二电路产生的热量少，但是比由在控制电路形成区CNT内的电路产生的热量多。I/O电路IF同样被形成于接近于第二电路形成区LGC2短边(即，在图2中的短边SID14)与第二电路形成区LGC2之间。
图3是示出第一半导体芯片SC1与布线板IP的耦接部分以及第一半导体芯片SC1与第二半导体芯片SC2的耦接部分的配置的截面图。
第一半导体芯片SC1由基板SUB1组成。基板SUB1是半导体基板，例如，硅基板。晶体管Tr1被形成于基板SUB1之上。在基板SUB1的形成晶体管Tr1的表面之上，形成了多层互连层MIL1。第一半导体芯片SC1的各种电路以多层互连层MIL1内的导线和晶体管Tr1来配置。
第一硅通孔TSV1形成于基板SUB1内。第一硅通孔TSV1由导电材料(例如，铜)制成，以便穿过基板SUB1。绝缘膜(未示出)被形成于第一硅通孔TSV1与基板SUB1之间。
在多层互连层MIL1的最上层布线层之上，形成了电极EL11。在每个电极EL11之上，形成了作为导体柱(典型为Cu柱)的连接端子CUP。连接端子CUP与在布线板IP的第一表面上的电极IEL通过它们之间的焊料SLD1耦接。绝缘层SR(例如，阻焊层)被设置于布线板IP的第一表面之上。绝缘层SR在与电极IEL重叠的位置处具有开口SRO。电极IEL的外围可以用绝缘层SR覆盖，或者可以从绝缘层SR中露出。
一些电极EL11通过在多层互连层MIL1内的导线和通孔耦接至在元件形成表面SFC11一侧的第一硅通孔TSV1的端部。在背表面SFC12一侧的第一硅通孔TSV1的其他端部通过焊料SLD2耦接至第二半导体芯片SC2的连接端子EL21。
在图3所示的实例中，第二半导体芯片SC2的连接端子EL21在平面图中与第一半导体芯片SC1的第一硅通孔TSV1重叠。但是，至少一些连接端子EL21不需要在平面图中与对应的第一硅通孔TSV1重叠。在这种情况下，至少一个布线层被形成于第一半导体芯片SC1的背表面SFC12之上。通过布线层，连接端子EL21与第一硅通孔TSV1耦接。
第一硅通孔TSV1被排布为具有比连接端子CUP之间的间距更小的间距。将连接端子CUP排布为具有相对较大的间距能够使连接端子CUP变得比第一硅通孔TSV1更厚。当第一半导体芯片SC1耦接至布线板IP时，使连接端子CUP变得更厚能够提高机械可靠性。另外，连接端子CUP能够增加高度。在图3所示的实例中，在平面图中，一些第一硅通孔TSV1与连接端子CUP至少部分重叠。这能够放松对连接端子CUP和第一硅通孔TSV1的布局的限制。作为选择，第一硅通孔TSV1能够被设计为与任意连接端子CUP都不重叠。
图4示出了第一硅通孔TSV1在硅通孔区TSVA1内的示例性布局。如图4所示，第一硅通孔TSV1在硅通孔区TSVA1内分别排布于网格点上。硅通孔区TSVA1的长边比其短边长例如十倍或更多。在第一硅通孔TSV1排布于其内的网格图形中，相邻的四个网格点形成例如方形、矩形或平行四边形，但是形状并不仅限于此。另外，并不一定要将第一硅通孔TSV1排布于全部网格点上。第一硅通孔TSV1未排布于其上的网格点与全部网格点之比为例如10％或更小。
图5示出了布线板IP的开口SRO的示例性形状。在图5所示的实例中，并没有为每一单个电极IEL提供开口SRO，而是作为共同开口提供给多个电极IEL。特别地，第一开口SRO沿着布线板IP的边缘连续地形成，以致于与同连接端子CUP1对应的电极IEL重叠。然后，第二开口SRO被形成于布线板IP的中心，以致于与同连接端子CUP2对应的电极IEL以及同连接端子CUP3对应的电极IEL重叠。在图5所示的实例中，第二开口SRO的端部与第一开口SRO耦接。但是，第一开口SRO和第二开口SRO能够彼此分离。作为选择，第二开口SRO能够分成各自分配给每个硅通孔区TSVA1的多个开口。
下面将参照图6至8来描述用于制造半导体器件SD的方法。首先，第一半导体芯片SC1和第二半导体芯片SC2被制备。第一半导体芯片SC1和第二半导体芯片SC2按照例如以下方式来形成。
首先，元件隔离膜被形成于形式为晶片的基板(例如，基板SUB1)上。以该元件隔离膜来隔离元件形成区。元件隔离膜通过例如STI法来形成，但是同样能够通过LOCOS法来形成。然后，栅极绝缘膜和栅极电极被形成于基板SUB1的元件形成区内。栅极绝缘膜可以是氧化硅膜或者具有比氧化硅膜的介电常数高的介电常数的高k值电介质膜(例如，硅酸铪膜)。如果栅极绝缘膜是氧化硅膜，则栅极电极由多晶硅膜制成。如果栅极绝缘膜是高k值电介质膜，则栅极电极由金属膜(例如，TiN)和多晶硅膜的层合膜制成。在栅极电极由多晶硅制成的情况下，多晶硅电阻器能够在栅极电极的形成过程中形成于元件隔离膜之上。
然后，源极和漏极的扩展区被形成于基板的元件形成区内。然后，侧壁被形成于栅极电极的侧面上。然后，将要成为源极和漏极的杂质区被形成于基板的元件形成区内。因而，晶体管(例如，晶体管Tr1)被形成于基板之上。
随后，多层互连层(例如，多层互连层MIL1)被形成于元件隔离膜和晶体管之上。电极(例如，电极EL11)被形成于多层互连层的最上层之上。然后，保护绝缘膜(钝化膜)被形成于多层互连层之上。开口被形成于电极之上的保护绝缘膜内。
在形成多层互连层的过程中，还为第二半导体芯片SC2形成用作存储器单元的电容元件。
连接端子CUP被形成于第一半导体芯片SC1的电极EL11之上。如果连接端子CUP是导体柱，则连接端子CUP通过例如电镀来形成。焊料层被形成于连接端子CUP之上。
然后，第一硅通孔TSV1在上述步骤的任何时候形成于第一半导体芯片SC1内。例如，第一硅通孔TSV1可以在晶体管Tr1形成之前或者在电极EL11和保护绝缘膜已经形成之后形成。作为选择，第一硅通孔TSV1能够在晶体管Tr1和多层互连层已经部分形成之后形成。在这种情况下，在元件形成表面SFC11一侧的第一硅通孔TSV1的端部耦接至多层互连层的任意布线层。另外，电极可以在任何时候形成于第一半导体芯片SC1的背表面SFC12之上，以耦接至第一硅通孔TSV1。
随后，晶片被切割成半导体芯片。
图8所示的布线板IP被制备。图8示出了以划片区SL来相互耦接的多个布线板IP(参见图6A、6B、6C和其他附图)。
然后，如图6A所示，第一半导体芯片SC1被安装于布线板IP之上。在这点上，连接端子CUP耦接至电极IEL，并且第一密封树脂UFR1被形成。第一密封树脂UFR1能够通过使用膜形树脂(例如，管芯附着膜(DAF))来形成，或者能够通过滴落液体树脂来形成。在前一种情形中，第一密封树脂UFR1在第一半导体芯片SC1被安装于布线板IP上之前被施加于布线板IP之上。这能够使得更容易形成如参照图2所描述的第一密封树脂UFR1的平面形状。在后一种情形中，第一密封树脂UFR1在第一半导体芯片SC1已经被安装于布线板IP上之后被施加。同样，在后一种情形中，第一密封树脂UFR1的端部形成至少沿着第一半导体芯片SC1的边向下延伸的圆角(fillet)。
然后，如图6B所示，第二半导体芯片SC2被安装于第一半导体芯片SC1之上。在这点上，第一半导体芯片SC1的第一硅通孔TSV1与第二半导体芯片SC2的连接端子EL21耦接。第二密封树脂UFR2然后被形成。第二密封树脂UFR2通过例如滴落液体树脂来形成。因此，第二密封树脂UFR2的端部形成至少沿着第二半导体芯片SC2的边向下延伸的圆角。
图6A和6B所示出的步骤在每个布线板IP上执行。
随后，如图6C所示，密封树脂MDR1被形成。密封树脂MDR1通过例如使用通过一组成型构件(未示出)形成的单个空腔(未示出)一次性全部(all at once)形成于布线板IP之上(批量成型法)。
在形成密封树脂MDR1的步骤中，能够为每个布线板IP都设置空腔。在这种情况下，针对每个个体布线板IP来密封第一半导体芯片SC1和第二半导体芯片SC2的叠层(个体成型法)。在这种情况下，由于每个布线板IP都覆盖着个体空腔(未示出)，因而布线板IP的侧表面没有与密封树脂MDR1的侧表面齐平。
然后，如图7A所示，给每个布线板IP都提供外部连接端子SB。
随后，如图7B所示，布线板IP和密封树脂MDR1沿着划片区SL来分开。因而，半导体器件SD被制备。
然后，将描述本实施例的主要操作和效应。根据本实施例，在平面图中，一些连接端子CUP2被定位于第一电路形成区LGC1与硅通孔区TSVA1之间。该布局允许在第一电路形成区LGC1内产生的热量的至少一部分通过连接端子CUP传递到布线板IP。结果，能够减少通过第一硅通孔TSV1从第一半导体芯片SC1传递到第二半导体芯片SC2的热量。特别地，在本实施例中，连接端子CUP2被排布为完全包围着硅通孔区TSVA1。因此，上述效应被进一步增强。
[第一改型]
图9是示出根据第一改型的半导体器件SD的配置的截面图。根据本改型的半导体器件SD具有与该实施例的半导体器件SD相同的配置，除了下列方面。
第一差异是半导体器件SD包含多个第二半导体芯片SC2。第二半导体芯片SC2一个叠一个地堆叠。第二或位置更高的第二半导体芯片SC2中的至少一个(例如，最上层的第二半导体芯片SC21)被制作得比其他第二半导体芯片SC2厚。但是，最上层的第二半导体芯片SC21同样能够具有与其他第二半导体芯片SC2相同的厚度。彼此堆叠的第二半导体芯片SC2被堆叠于第一半导体芯片SC1之上。
每个第二半导体芯片SC2都具有第二硅通孔TSV2。第二硅通孔TSV2将一个第二半导体芯片SC2耦接至位于其上方的另一个第二半导体芯片SC2。因而，第一半导体芯片SC1通过第二硅通孔TSV2与第二或者位置更高的第二半导体芯片SC2电耦接。第二半导体芯片SC2例如全部是存储器芯片。但是，第二半导体芯片SC2中的至少一个可以包含逻辑电路。在图9所示的实例中，各个第二半导体芯片SC2的四个边在平面图中彼此重叠。另外，各个第二半导体芯片SC2的第二硅通孔TSV2在平面图中彼此重叠。
可从平面图看出，至少一些第二硅通孔TSV2与任一第一硅通孔TSV1重叠。按照上述方式来布设通孔能够简化在第二硅通孔TSV2以及与其耦接的第一硅通孔TSV1之间的导体的样式。
在图9所示的实例中，第二硅通孔TSV2排布于与第一硅通孔TSV1相同的网格点上。第二半导体芯片SC2同样具有与硅通孔区TSVA1相似的区域。例如，在第二半导体芯片SC2是存储器芯片的情况下，第二硅通孔TSV2按照JEDECJESD229所给出的规范排布。在平面图中，由第一硅通孔TSV1的阵列组成的网格分别与由第二硅通孔TSV2组成的网格重叠。
图10示出了第二半导体芯片SC2的截面结构。在图10所示的实例中，第二硅通孔TSV2被形成于第二半导体芯片SC2的基板SUB2内。第二硅通孔TSV2由导电材料(例如，铜)制成，并且穿过基板SUB2。同样，绝缘膜被嵌入基板SUB2之内，以致于包围着第二硅通孔TSV2。该绝缘膜可以比在第一半导体芯片SC1的基板SUB1与第一硅通孔TSV1之间的绝缘膜更厚。
在基板SUB2的元件形成表面SFC21之上，形成了多层互连层MIL2。第二硅通孔TSV2通过多层互连层内的通孔等耦接至设置于多层互连层MIL2之上的连接端子EL21。连接端子EL21是例如由铜或其他材料制成的导体柱。另外，电极EL22被形成于基板SUB2的背表面SFC22之上。电极EL22耦接至第二硅通孔TSV2。
用于制造根据第一改型的半导体器件SD的方法与用于制造根据第一实施例的半导体器件SD的方法相同，除了第二半导体芯片SC2预先彼此堆叠。
第一改型同样能够提供与实施例相同的效果。另外，使包围着第二半导体芯片SC2的基板SUB2内的第二硅通孔TSV2的绝缘膜变得比在第一半导体芯片SC1的基板SUB1与第一硅通孔TSV1之间的绝缘膜更厚能够减少通过第一硅通孔TSV1和第二硅通孔TSV2流入基板SUB2内的热量。
[第二改型]
图11是示出根据第二改型的半导体器件SD的配置的平面图。根据本改型的半导体器件SD具有与实施例或第一改型相同的配置，除了下列方面。
可从沿着硅通孔区TSVA1的短边截取的截面中看出，硅通孔区TSVA1的中心在与第一电路形成区LGC1的相反方向上偏离第一半导体芯片SC1的中心。尤其是在该截面中，优选的是第一半导体芯片SC1的中心不与硅通孔区TSVA1的中心对齐。
同样，在该截面中，第一电路形成区LGC1排布在相对于布线板IP的中心的一侧，而硅通孔区TSVA1排布在另一侧。
关于硅通孔区TSVA1，第二电路形成区LGC2安置于与第一电路形成区LGC1相同的一侧。在平面图中，第一电路形成区LGC1的至少一部分与第二半导体芯片SC2不重叠。同样，在平面图中，第二电路形成区LGC2的至少一部分与第二半导体芯片SC2不重叠。
在上述截面中，第二半导体芯片SC2的中心偏离布线板IP的中心。该布局能够使从第二半导体芯片SC2的至少一个侧表面到半导体器件SD的侧表面的距离变得更短，由此使得容易从半导体器件SD的侧表面释放第二半导体芯片SC2的热量。
同样，在该截面中，从第二半导体芯片SC2的中心到布线板IP的中心的距离比从第一半导体芯片SC1到布线板IP的中心的距离短。
如果第一半导体芯片SC1由通过使硅通孔区TSVA1平行于硅通孔区TSVA1的长边延伸而形成的区域划分，则包含第一电路形成区LGC1的区域具有数量比另一区域更多的连接端子CUP。该布局允许来自第一电路形成区LGC1的热量容易地通过连接端子CUP散逸到布线板IP。
第二改型同样能够提供与该实施例或第一改型相同的效果。可从沿着硅通孔区TSVA1的短边截取的截面中看出，硅通孔区TSVA1的中心在与第一电路形成区LGC1的相反方向上偏离第一半导体芯片SC1的中心。因此，在第一电路形成区LGC1与硅通孔区TSVA1之间的距离能够还要增大。因此，在第一电路形成区LGC1内产生且通过第一硅通孔TSV1到达第二半导体芯片SC2的热量能够被进一步减少。在上述截面中，第二半导体芯片SC2的中心优选地与硅通孔区TSVA1对齐。该布局能够使在第二半导体芯片SC2内的温度分布变平滑。
另外，从第二半导体芯片SC2的中心到布线板IP的中心的距离比从第一半导体芯片SC1到布线板IP的中心的距离短。因此，第二半导体芯片SC2至少一个侧表面能够安置于半导体器件SD的侧表面附近。因此，第二半导体芯片SC2的热量能够容易地从半导体器件SD的侧表面释放出。
另外，相对于硅通孔区TSVA1，第二电路形成区LGC2安置于与第一电路形成区LGC1相同的一侧。因此，其中第一电路形成区LGC1和第二电路形成区LGC2位于其内的第一半导体芯片SC1的区域的温度升高，由此使得在第一半导体芯片SC1与第一半导体芯片SC1周围的树脂之间的温度梯度变得更大。结果，能够增加从第一半导体芯片SC1散逸出的热量。
[第三改型]
图12是根据第三改型的电子器件ED的平面图。图12所示的电子器件ED是便携式电子器件，例如，便携式通信终端、便携式视屏游戏机和便携式个人计算机，并且包括半导体器件SD。电子器件ED还包括显示器DIS。显示器DIS通过使用半导体器件SD来控制。
图13是示出电子器件ED的功能配置的框图。在图13所示的实例中，第二半导体芯片SC2是存储器芯片。第一半导体芯片SC1使用第二半导体芯片SC2来控制电子器件ED。第一半导体芯片SC1的第一电路形成区LGC1是核心中央处理单元(CPU)，而第一半导体芯片SC1的第二电路形成区LGC2是图形处理单元(GPU)。第一半导体芯片SC1还包括多个电路区LGC3、LGC4(例如，调制解调电路、语音处理电路等)。电子器件ED还包括非易失性存储器(NVM)。
第一半导体芯片SC1与通信单元(有线或无线)、用于无线标签的通信接口(例如，RFIC)、模拟-数字转换器(ADC)、数字-模拟转换器(DAC)、电源控制器、SIM卡、图像拾取单元、存储卡、用户输入单元(例如，键盘)、USB通信单元及NVM通信。
本领域技术人员还应当理解，尽管上述描述已经针对本发明的实施例作出，但是本发明并不限定于此，并且在不脱离本发明的精神和所附权利要求书的范围的情况下可以进行各种变更和修改。

Claims (7)

1.一种半导体器件，包括：
布线板；
第一半导体芯片，其被安装于所述布线板的第一表面之上使得元件形成表面面朝所述第一表面，并且所述第一半导体芯片具有第一电路；
第二半导体芯片，其被布置于所述第一半导体芯片之上；以及
多个连接端子，其将所述第一半导体芯片与所述布线板耦接，
其中所述第一半导体芯片具有面朝所述第一表面的所述元件形成表面，并且所述第一半导体芯片具有多个第一硅通孔，
其中所述第二半导体芯片与所述第一半导体芯片的所述第一硅通孔电耦接，
其中每个所述第一硅通孔都被布置于成m行和n列排布的网格点中的任意一个上，其中m＞n，
其中通过将成m行和n列排布的最外侧网格点耦接来界定的硅通孔区在平面图中不与所述第一电路重叠，
其中所述硅通孔区在平面图中不与所述多个连接端子重叠，
其中所述多个连接端子包括多个第一连接端子，
其中所述多个第一连接端子中的一些连接端子在平面图中位于所述第一电路与所述第一硅通孔之间，
其中所述第一半导体芯片和所述硅通孔区两者在平面图中都是矩形的，
其中所述硅通孔区的长边在平面图中与所述第一半导体芯片的短边平行，
其中所述第一电路在平面图中位于所述硅通孔区的所述长边与所述第一半导体芯片的所述短边之间，
其中当在与所述硅通孔区平行的截面中观察时，所述硅通孔区的中心沿着与所述第一电路的相反方向偏离所述第一半导体芯片的中心，并且
其中如果所述第一半导体芯片由通过使所述硅通孔区平行于所述硅通孔区的所述长边延伸而形成的区域划分，则包含所述第一电路的区域具有数量比另一区域更多的连接端子。
2.根据权利要求1所述的半导体器件，
其中，在所述截面中，从所述第二半导体芯片的所述中心到所述布线板的所述中心的距离比从所述第一半导体芯片的所述中心到所述布线板的所述中心的距离短。
3.根据权利要求1所述的半导体器件，还包括：
第一密封树脂，其用于密封在所述第一半导体芯片与所述布线板之间的间隔；以及
第二密封树脂，其用于密封在所述第一半导体芯片与所述第二半导体芯片之间的间隔，
其中所述第一密封树脂比所述第二密封树脂薄。
4.根据权利要求1所述的半导体器件，
其中所述第一半导体芯片比所述第二半导体芯片薄。
5.根据权利要求1所述的半导体器件，
其中在平面图中所述第一半导体芯片和所述第二半导体芯片两者都是矩形的，并且
其中在平面图中所述第二半导体芯片的长边与所述第一半导体芯片的短边平行。
6.根据权利要求1所述的半导体器件，
其中所述第二半导体芯片具有多个第二硅通孔，
其中第三半导体芯片被布置于所述第二半导体芯片之上并且与所述第二半导体芯片的所述第二硅通孔电耦接，并且
其中所述第三半导体芯片比所述第二半导体芯片厚。
7.根据权利要求1所述的半导体器件，其中所述第一半导体芯片的所述第一电路是中央处理单元。
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