TWI474461B - 積體電路及三維堆疊之多重晶片模組 - Google Patents

積體電路及三維堆疊之多重晶片模組 Download PDF

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Publication number
TWI474461B
TWI474461B TW99134334A TW99134334A TWI474461B TW I474461 B TWI474461 B TW I474461B TW 99134334 A TW99134334 A TW 99134334A TW 99134334 A TW99134334 A TW 99134334A TW I474461 B TWI474461 B TW I474461B
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Taiwan
Prior art keywords
pad
integrated circuit
metal layer
pads
circuit
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TW99134334A
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English (en)
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TW201133762A (en
Inventor
Oscar M K Law
Kuo H Wu
Wei Chih Yeh
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Taiwan Semiconductor Mfg Co Ltd
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Publication of TW201133762A publication Critical patent/TW201133762A/zh
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Description

積體電路及三維堆疊之多重晶片模組
本發明係有關於一種積體電路，特別是有關於一種矽通孔電極(through silicon via,TSV)接線結構。
一般來說，打線接合(wire bonding)為一種在積體電路(integrated circuit,IC)與含有IC的封裝體之間形成連接或直接與印刷電路板形成連接的方法。在打線接合製程中，接線係用以自IC的接墊及封裝體上形成電性連接。接線可由金、鋁、銅、或其合金等所構成。打線接合製程通常認為是具有成本效益及彈性的，而使用於組裝相當多的半導體封裝。
用以將IC連接至外部電路或其他IC的另一技術為覆晶(flip chip)製程。在覆晶製程中，IC透過設置於晶片接墊上的焊料凸塊(solder bump)而連接至其他電路，例如外部電路或其他IC。焊料凸塊可在進行晶圓製程期間設置於半導體晶圓頂側的晶片接墊上。接著倒置IC(因而稱作覆晶)使其上表面向下，接著經過焊接而完成IC與外部電路或其他IC之間的內連接。覆晶技術利用焊料凸塊取代了打線接合技術中的接線，以作為外部信號連接及電源連接。由於焊料凸塊的使用而免除了又長又高阻值的接線，因此有助於大幅降低出現於打線接合用於高功率產品中的電流電阻(current-resistance,IR)壓降效應。信號及電源可配送於具有堆疊連接窗(via)結構的覆晶積體電路中。
在本發明一實施例中，一種積體電路，包括：一基底，具有一上表面及一下表面，其中一電路形成於上表面上；複數個接墊，形成於下表面的周邊，其中接墊中的一第一次組接墊經由複數個矽通孔電極而電性耦接至上表面上的電路；以及一背側金屬層，形成於下表面上且電性耦接至接墊中的一第二次組接墊，背側金屬層配送由第二次組接墊所提供的電子信號。
在本發明另一實施例中，一種積體電路，包括：一基底，具有一上表面及一下表面，其中一電路形成於上表面上；一第一接墊，設置於下表面上，其中第一接墊經由一矽通孔電極而電性耦接至上表面上的電路；以及一背側金屬層，設置於下表面上且電性耦接至設置於下表面上的一第二接墊，背側金屬層配送由第二接墊所提供的一信號。
在本發明又一實施例中，一種三維堆疊之多重晶片模組，包括：一第一積體電路及一第二積體電路其中第一積體電路貼合至第二積體電路。第一積體電路，包括一第一基底，其具有一第一上表面及一第一下表面，其中一第一電路形成於第一上表面上。第二積體電路，包括：一第二基底，具有一第二上表面及一第二下表面，其中一第二電路形成於第二上表面上；複數個接墊，形成於第二下表面的周邊，其中接墊中的一第一次組接墊經由複數個矽通孔電極而電性耦接至第二上表面上的第二電路；以及一背側金屬層，形成於第二下表面上且電性耦接至接墊中的一第二次組接墊，背側金屬層配送由第二次組接墊所提供的電子信號。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
以下說明本發明實施例之一特定背景，即包括多重晶片的系統級封裝(system in a package,SiP)。然而，上述實施例也可應用於三維堆疊之多重晶片模組、系統單晶片(system on a chip,SoC)、含單晶片的積體電路等等。
如之前所述，打線接合對於半導體封裝的組裝提供了成本效益及彈性的解決之道。然而，在高功率產品應用中，又長又薄(因而具有高阻值)的接線會造成大量的電流-電阻(IR)壓降。大量的IR壓降迫使需採用具有較高電壓的電源供應器，其難以實施或需要更高的成本。大量的IR壓降也迫使操作上需降低雜訊容限度(noise margin)，其導致裝置更容易受到電源雜訊的影響。
採用覆晶技術有助於在高功率產品應用中降低IR壓降。然而，覆晶技術需在多重晶片之間使用堆疊通孔結構來進行電源及信號配送，其導致較高的製造成本。另外，在具有垂直堆疊的多重晶片的系統級封裝(SiP)中，電源及信號配送必須通過整個垂直堆疊結構。此需要垂直堆疊結構中下方的覆晶對於通過覆晶的所有電源及信號具有內建補償(built-in compensation)。此需要下方的覆晶大於需要補償額外電源及信號而通過的覆晶。
第1圖係繪示出積體電路200的剖面示意圖。積體電路200的製造採用了矽通孔電極(TSV)結構，其中可經由穿過基底210的矽通孔電極來進行電源及信號的配送，例如電源通孔電極結構205及信號通孔電極結構206。經由矽通孔電極，電源及信號可透過典型結構中的內部金屬層而配送至內部電路。
矽通孔電極，例如電源通孔電極結構205，包括形成於基底210的一第一表面上的一第一導電接墊207，以及填入基底210內的通孔的一導電構件209，且可連接至位於基底210的一第二表面上的內部金屬佈線208。導電構件209電性連接第一導電接墊207及內部金屬佈線208。接著內部金屬佈線208可用於配送電子信號及/或電源。
然而，除了內部金屬佈線208之外，電源及信號的配送也可透過背側金屬層(backside metal layer,BML)220。背側金屬層220可形成於背向基底210的積體電路的一側上。背側金屬層220可用於電源及信號的配送。積體電路200可使用接線進行對外的連接，例如電源接線215及信號接線216。
背側金屬層220較佳由鋁、銅、金、及其合金等所構成，以提供用於電源及信號配送的一低電阻金屬。背側金屬層220的厚度也可大於常規的金屬層，以進一步降低背側金屬層220的電阻率。降低背側金屬層220的電阻率可具有低的IR壓降。由於背側金屬層220不具有前側金屬層機械應力及通孔尺寸限制，因此以上所述是合理的。背側金屬層220的總厚度較佳為常規金屬層的厚度的至少二倍(2×)，以降低其電阻率。再者，背側金屬層220可為垂直、水平、對角線、鋸齒形或任意排列，用以配送電源，而較佳為對角線排列。背側金屬層220也稱作重佈局線(redistribution layer,RDL)。
較佳的是將背側金屬層220與電源或信號電性連接，而矽通孔電極(如，電源通孔電極222)可用於將電源或信號連接至背側金屬層220。由於矽通孔電極的尺寸通常小於接墊，因此通孔電極直接接合至背側金屬層220內的接墊上，使背側金屬層220保有最小的尺寸大小。當使用大量的矽通孔電極來供應電源至背側金屬層220以將IR壓降最小化時，較小尺寸的矽通孔電極特別具有優勢。若採用打線接合來將電源及信號電性連接至背側金屬層220，使用矽通孔電即可不妨礙其他積體電路貼合至積體電路200。
除了經由矽通孔電極連接電源及信號之外，也可經由與背側金屬層220形成於相同側的連接線來將背側金屬層220電性連接至電源及信號。與背側金屬層220形成於相同側的連接線可直接連接至一接墊。
可使用形成於內部金屬層內電源及信號佈線來進行額外的電源及信號配送。電源/接地(P/G)佈線225及信號佈線226。再者，當難以檢驗內部金屬層的配送或者造成大量的IR壓降時，背側金屬層220可用於額外的電源及信號配送彈性測量。矽通孔電極可用於內部金屬層與背側金屬層220之間的連接。
積體電路200包括接墊，例如接墊230，以容許在積體電路200上放置焊料凸塊，其可容許積體電路200連接至外部電路或是其他使用覆晶技術的積體電路。積體電路200可為包括多重積體電路的系統單晶片(SoC)的一部分。第2a圖係繪示出系統單晶片300。系統單晶片300包括一母晶片(mother die)305及一子晶片(daughter die)310。子晶片310可使用覆晶技術而直接裝貼於母晶片305上。積體電路200也可為系統級封裝(SiP)的一部分。
第2b圖係繪示出系統單晶片325。系統單晶片325包括一母晶片330、一子晶片335、一子晶片340及一子晶片345。子晶片335直接裝貼於母晶片330上，而子晶片340直接裝貼於子晶片335上，且子晶片345直接裝貼於子晶片340上。雖然圖式中為四個垂直堆疊晶片，然而系統單晶片也可由其他可能的晶片組合所構成。舉例來說，在另一系統單晶片中，子晶片335及子晶片340可裝貼於母晶片330的不同部分上，且子晶片345可裝貼於子晶片340上。另外，子晶片335、子晶片340及子晶片345可分別裝貼於母晶片330的不同部分上。因此，本發明實施例的精神及範圍並未局限於圖式上的單一垂直堆疊。
然而，不同於覆晶技術中電源及信號是經由垂直堆疊中最下層積體電路或轉接板(interposer)來配送，採用矽通孔電極接線結構的積體電路垂直堆疊，例如積體電路200，可將電源及信號連接至各別的積體電路。第2c圖係繪示出打線接合之後的系統單晶片325。每一晶片(母晶片330、子晶片335、子晶片340及子晶片345)可使用接線進行外部連接。由外部連接至每一晶片能夠將電源及信號直接配送至晶片上而無需規劃未使用的電源及信號通過任何晶片。其有助於將IR壓降最小化。再者，由於晶片不需規劃未使用的電源及信號，因此可將晶片的尺寸最小化。如第2c圖所示，使用矽通孔電極將電源及信號電性耦接至背側金屬層220可容許積體電路(例如，子晶片335裝貼於母晶片330、子晶片340裝貼於子晶片335、以此類推)裝貼於積體電路中與背側金屬層220相同的一側上。
隨著技術的提升，設計複雜度顯著的增加。設計複雜度的增加導致設計中具有龐大的裝置總數及功能性。然而，增加裝置總數導致較高的電源消耗。較高的電源消耗需求導致不僅需要大量的電源接墊來供應內部電路所需的電源，而且需要密集的電源供應網路來將IR壓降最小化。密集的電源供應網路及相關的電源接墊消耗了設計中大量的可用電源及信號佈線資源。因此，設計的晶片尺寸及製造成本皆有顯著的增加。
第3a圖係繪示出習知的電源供應網路400。電源供應網路400包括配送電性接地(GND)的一第一網路405以及配送一第一電壓(VDD)的一第二網路410。第一網路405及第二網路410可由不同層所構成，例如不同的金屬層或是一者為金屬層而另一者為非金屬的導電層。在網線(例如第一網線415與第二網線416)的交界處，一電源接墊(例如，電源接墊420)可構成二網線之間的電性連接。再者，電源接墊下方可為電源佈線，以提供電源至內部電路。如第3a圖所示，積體電路中相當多的佈線資源(大約為總佈線資源的30%或以上)用於電源信號的佈線。
第3b圖係繪示出積體電路450的剖面示意圖，其中積體電路450包括習知的電源供應網路，用以將電源配送至積體電路450。如第3b圖所示，焊料凸塊455用於第二網路410與VDD之間的電性連接。電源佈線460將電源連接至積體電路450中的一第一電晶體。請參照第3b圖，一焊料凸塊465透過一信號佈線470而提供一信號至一第二電晶體。使用於電源及信號佈線中的堆疊連接窗陣列(via array)，例如電源佈線460以及信號佈線470，塞滿於積體電路450內，使得積體電路450內的內部信號佈線更為困難。
第4a圖係繪示出具有背側金屬層220的積體電路200的底視平面示意圖。如之前所述，背側金屬層220係用於電源及信號的配送。背側金屬層220可具有一環形結構，具有一電源環525形成於積體電路200的周邊，但通常位於複數個接墊內側，上述接墊包括用以將外部信號連接至內部信號的接墊(例如，接墊510及511)以及用以提供內部電路電源及接地的電源接墊(例如，接墊515及516)。上述接墊可構成單一的接墊環且圍繞電源環525，如第4a圖所示。另外，取決於上述接墊的數量，多重接墊環或少於單一接墊環的接墊可圍繞電源環525。
請參照第4a圖，電源環525及接墊可形成於積體電路200的周邊。然而，取決於電源及信號配送需求，電源環525可不形成於積體電路200的周邊。另外，電源環525可形成於積體電路200的背側或前側上或是積體電路200的兩側。
電源環525內側為複數個矽通孔電極(如虛線520內側所示)。上述矽通孔電極可用於配送電源至積體電路200的內部電路。上述矽通孔電極可電性耦接至電源環525外側的電源接墊。舉例來說，上述矽通孔電極的一些矽通孔電極可接地，而其他的矽通孔電極可電性耦接至VDD。上述矽通孔電極可水平、垂直、對角線、鋸齒形或任意排列，，而較佳為對角線排列。另外，矽通孔電極的排列可受積體電路200的內部電路的排列所支配而沒有特定的排列。電源環525可將一些或所有的電源接墊連接至上述矽通孔電極。電源環525可由背側金屬(即，電源環525可與背側金屬層220形成於同一側)、前側金屬(即，電源環525可與背側金屬層220形成於相對側)、或其組合所構成。
矽通孔電極的優勢在於其小於電源及/或信號接墊。因而接墊間距放寬，使得整體面積縮減。另外，矽通孔電極容許使用低成本的接線作為信號及電源的連接。再者，矽通孔電極有助於解決多重晶片堆疊的問題，其中晶片堆疊中位於上方的晶片，其電源必須佈線經過晶片堆疊中位於下方的晶片。此有助於緩和必須將晶片堆疊中下方的晶片的區域用於配送電源至晶片堆疊中位於上方的晶片。相似地，矽通孔電極可透過直接將電源連接至晶片堆疊中的晶片而解決IR壓降問題。雖然第4a圖所繪示的是連接電源接墊，然而上述矽通孔電極中一些矽通孔電極可電性連接至信號接墊。
第4b圖係繪示出用於一積體電路中電源配送的柵網矩陣排列平面示意圖。柵網矩陣可用於電源配送，其中電流經過低電阻的矽通孔電極(例如，上述矽通孔電極)而直接流至積體電路的內部電路。柵網矩陣排列容許使用少數金屬層(例如，金屬層1及金屬層2)作為局部電源連接。柵網矩陣排列可連接至背側金屬層220以進一步改善整體電源配送。請參照第4c圖，其繪示出一積體電路的剖面示意圖，其中積體電路包括背側金屬層220及用於積體電路中電源配送的柵網矩陣排列。如第4c圖所示，由於電源配送於背側金屬層220及柵網矩陣排列，因此積體電路中大部分的內部金屬層可用於信號配送。第4c圖也繪示出信號經由一矽通孔電極而配送至積體電路內部電路。
第5a圖係繪示出用於一積體電路中電源配送的柵網矩陣排列分劃600平面示意圖。積體電路通常可劃分成一柵網系統，其由一最小柵網及一最大柵網(如晶片邊界605及次區(tile)邊界610)所組成，其中最大柵網為多重的最小柵網。接著，矽通孔電極可放置於多重相鄰區塊共有的邊界上。舉例來說，矽通孔電極615可用於配送VDD，而矽通孔電極620可用於配送電性接地(VSS)。
第5b圖係繪示出用於一積體電路中電源配送的柵網矩陣排列分劃650平面示意圖。柵網矩陣排列分劃650相似於柵網矩陣排列分劃600，差別在於柵網矩陣排列分劃650中的矽通孔電極退離次區邊界610而形成隔離的電壓島(voltage island)。舉例來說，矽通孔電極655可僅用於配送VDD至單一電壓島，而矽通孔電極660可僅用於配送VSS至上述單一電壓島。
內部電路可在柵網矩陣排列之後設置，以最小化電流供應而不會遭遇任何金屬佈線阻礙的問題。電源柵網排列可為垂直、水平、對角線、鋸齒形排列等等，而較佳為對角線排列。
矽通孔電極接線結構可提供多於覆晶結構的優點。表1提供了矽通孔電極接線結構與使用電源供應網路配送電源(N45製程)的覆晶結構之間差異比較。
如表1所示，矽通孔電極接線結構與具有電源供應網路配送電源的覆晶結構之間顯著差異包括：電流從低電阻的矽通孔電極直接流入裝置，而不是經由多重金屬層來配送(因而具有低IR壓降)；不需要密集的中介(intermediate)電源佈線，僅需少許金屬層提供局部電源連接，因而顯著增加可佈線能力(routability)；柵網矩陣排列直接連接至背側金屬層以提供更佳的電流配送；相同電阻值的矽通孔電極尺寸小於堆疊連接窗陣列尺寸的10倍；降低晶片尺寸與所需的金屬層數量；以及矽通孔電極接線結構中電源雜訊大幅降低。另外，由於矽通孔電極接線結構而使設計週期與製造良率都有顯著的改善。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種更動、替代與潤飾。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。
 習知
400．．．電源供應網路
405．．．第一網路
410．．．第二網路
415．．．第一網線
416．．．第二網線
420．．．電源接墊
450．．．積體電路
455、465．．．焊料凸塊
460．．．電源佈線
470．．．信號佈線
實施例
200．．．積體電路
205．．．電源通孔電極結構
206．．．信號通孔電極結構
207．．．第一導電接墊
208．．．內部金屬佈線
209．．．導電構件
210．．．基底
215．．．電源接線
216．．．信號接線
220．．．背側金屬層
222．．．電源通孔電極
225．．．電源/接地佈線
226．．．信號佈線
230、510、511、515、516．．．接墊
300、325．．．系統級晶片
305、330．．．母晶片
310、335、340、345．．．子晶片
520．．．虛線
525．．．電源環
600、650．．．分劃
605．．．晶片邊界
610．．．次區邊界
615、620、655、660．．．矽通孔電極
第1圖係繪示出根據一積體電路剖面示意圖。
第2a圖係繪示出第一系統單晶片的剖面示意圖。
第2b圖係繪示出第二系統單晶片的剖面示意圖。
第2c圖係繪示出第三系統單晶片的剖面示意圖。
第3a圖係繪示出習知電源供應網路(power mesh)平面示意圖。
第3b圖係繪示出一積體電路剖面示意圖，其中積體電路使用習知電源供應網路。
第4a圖係繪示出一積體電路底視平面示意圖。
第4b圖係繪示出用於一積體電路中電源配送的柵網矩陣排列平面示意圖。
第4c圖係繪示出用於一積體電路，其中信號至積體電路的內部電路的配送係通過矽通孔電極。
第5a圖係繪示出用於一積體電路中電源配送的柵網矩陣排列分劃平面示意圖。
第5b圖係繪示出用於一積體電路中電源配送的柵網矩陣排列分劃平面示意圖。
200‧‧‧積體電路
220‧‧‧背側金屬層
510、511、515、516‧‧‧接墊
520‧‧‧虛線
525‧‧‧電源環

Claims (8)

  1. 一種積體電路，包括：一基底，具有一上表面及一下表面，其中一電路形成於該上表面上；複數個接墊，形成於該下表面的周邊，其中該等接墊中的一第一次組接墊經由複數個矽通孔電極而電性耦接至該上表面上的該電路；以及一背側金屬層，形成於該下表面上且電性耦接至該等接墊中的一第二次組接墊，該背側金屬層配送由該第二次組接墊所提供的電子信號，其中該背側金屬層形成於由該等接墊所構成的一邊界內。
  2. 如申請專利範圍第1項所述之積體電路，其中該第一次組接墊中耦接至該等接墊的每一矽通孔電極包括：一第一導電接墊，形成於該下表面；一第二導電接墊，形成於該上表面；以及一導電構件，將該第一導電接墊電性耦接至該第二導電接墊，該導電構件形成於該基底內的一孔洞內。
  3. 如申請專利範圍第1項所述之積體電路，其中該第二次組接墊內的該等接墊接地或耦接至一第一電壓，該背側金屬層包括排列成一柵網圖案的複數個導體連接至耦接於該上表面上的該電路的該等矽通孔電極，以配送電性接地或該第一電壓至該上表面上的該電路，且該背側金屬層更包括至少一凸塊接墊耦接至一矽通孔電極，該矽通孔電極作為該積體電路與一貼合的積體電路或一外部基底之間的電性連接。
  4. 一種積體電路，包括：一基底，具有一上表面及一下表面，其中一電路形成於該上表面上；一第一接墊，設置於該下表面上，其中該第一接墊經由一矽通孔電極而電性耦接至該上表面上的該電路；一背側金屬層，設置於該下表面上且電性耦接至設置於該下表面上的一第二接墊，該背側金屬層配送由該第二接墊所提供的一第一信號；以及一電源環，設置於該基底的周邊，該電源環配送電源至該上表面上的該電路。
  5. 如申請專利範圍第4項所述之積體電路，其中該第二接墊經由二矽通孔電極而電性耦接至該背側金屬層，其中一第一矽通孔電極將該第二接墊的該第一信號傳送至該上表面，且一第二矽通孔電極將該第一信號傳送至該背側金屬，其中該第一矽通孔電極經由一導體而電性耦接至該第二矽通孔電極。
  6. 如申請專利範圍第4項所述之積體電路，其中該背側金屬層更配送由一第三接墊所提供的一第二信號，其中該第三接墊直接耦接至該背側金屬層。
  7. 一種三維堆疊之多重晶片模組，包括：一第一積體電路，包括一第一基底，其具有一第一上表面及一第一下表面，其中一第一電路形成於該第一上表面上；以及一第二積體電路，包括：一第二基底，具有一第二上表面及一第二下表面， 其中一第二電路形成於該第二上表面上；複數個第一接墊，形成一環形結構且位於該第二下表面的周邊，其中該等第一接墊中的一第一次組接墊經由複數個第一矽通孔電極而電性耦接至該第二上表面上的該第二電路；以及一第一背側金屬層，形成於該第二下表面上的該環形結構內且電性耦接至該等第一接墊中的一第二次組接墊，該第一背側金屬層配送由該第二次組接墊所提供的電子信號；其中該第一積體電路貼合至該第二積體電路。
  8. 如申請專利範圍第7項所述之三維堆疊之多重晶片模組，其中該第一積體電路更包括：複數個第二接墊，形成於該第一下表面的周邊，其中該等第二接墊中的一第三次組接墊經由複數個第二矽通孔電極而電性耦接至該第一上表面上的該第一電路，其中該等第二接墊的每一接墊經由接線電性耦接至外部信號；以及一第二背側金屬層，形成於該第一下表面上且電性耦接至該等第二接墊中的一第四次組接墊，該第二背側金屬層配送由該第四次組接墊所提供的電子信號。
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