CN102044512A - 集成电路及三维堆叠的多重芯片模块 - Google Patents

集成电路及三维堆叠的多重芯片模块 Download PDF

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Publication number
CN102044512A
CN102044512A CN201010505136XA CN201010505136A CN102044512A CN 102044512 A CN102044512 A CN 102044512A CN 201010505136X A CN201010505136X A CN 201010505136XA CN 201010505136 A CN201010505136 A CN 201010505136A CN 102044512 A CN102044512 A CN 102044512A
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integrated circuit
pad
metal layer
silicon
backside metal
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CN102044512B (zh
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罗明健
吴国雄
叶威志
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明揭示一种集成电路及三维堆叠的多重芯片模块，该集成电路包括：一基底，具有一上表面及一下表面，而一电路形成于上表面上；多个焊盘，形成于下表面的周边；以及一背侧金属层，形成于下表面上。焊盘中的一第一次组焊盘经由多个硅通孔电极而电性耦接至上表面上的电路。背侧金属层电性耦接至焊盘中的一第二次组焊盘。背侧金属层配送由第二次组焊盘所提供的电子信号。本发明由于硅通孔电极接线结构而使设计周期与制造良率都有显著的改善。

Description

集成电路及三维堆叠的多重芯片模块
技术领域
本发明涉及一种集成电路，特别涉及一种硅通孔电极(through silicon via，TSV)接线结构。
背景技术
一般来说，打线接合(wire bonding)为一种在集成电路(integrated circuit，IC)与含有IC的封装体之间形成连接或直接与印刷电路板形成连接的方法。在打线接合工艺中，接线用以自IC的焊盘及封装体上形成电性连接。接线可由金、铝、铜、或其合金等所构成。打线接合工艺通常认为是具有成本效益及弹性的，而使用于组装相当多的半导体封装。
用以将IC连接至外部电路或其他IC的另一技术为倒装芯片(flip chip)工艺。在倒装芯片工艺中，IC通过设置于芯片焊盘上的焊料凸块(solderbump)而连接至其他电路，例如外部电路或其他IC。焊料凸块可在进行晶片工艺期间设置于半导体晶片顶侧的芯片焊盘上。接着倒置IC(因而称作倒装芯片)使其上表面向下，接着经过焊接而完成IC与外部电路或其他IC之间的内连接。倒装芯片技术利用焊料凸块取代了打线接合技术中的接线，以作为外部信号连接及电源连接。由于焊料凸块的使用而免除了又长又高阻值的接线，因此有助于大幅降低出现于打线接合用于高功率产品中的电流电阻(current-resistance，IR)压降效应。信号及电源可配送于具有堆叠连接窗(via)结构的倒装芯片集成电路中。
发明内容
本发明的目的在于克服现有技术中的缺陷。
在本发明一实施例中，一种集成电路，包括：一基底，具有一上表面及一下表面，其中一电路形成于上表面上；多个焊盘，形成于下表面的周边，其中焊盘中的一第一次组焊盘经由多个硅通孔电极而电性耦接至上表面上的电路；以及一背侧金属层，形成于下表面上且电性耦接至焊盘中的一第二次组焊盘，背侧金属层配送由第二次组焊盘所提供的电子信号。
在本发明另一实施例中，一种集成电路，包括：一基底，具有一上表面及一下表面，其中一电路形成于上表面上；一第一焊盘，设置于下表面上，其中第一焊盘经由一硅通孔电极而电性耦接至上表面上的电路；以及一背侧金属层，设置于下表面上且电性耦接至设置于下表面上的一第二焊盘，背侧金属层配送由第二焊盘所提供的一信号。
在本发明又一实施例中，一种三维堆叠的多重芯片模块，包括：一第一集成电路及一第二集成电路其中第一集成电路贴合至第二集成电路。第一集成电路，包括一第一基底，其具有一第一上表面及一第一下表面，其中一第一电路形成于第一上表面上。第二集成电路，包括：一第二基底，具有一第二上表面及一第二下表面，其中一第二电路形成于第二上表面上；多个焊盘，形成于第二下表面的周边，其中焊盘中的一第一次组焊盘经由多个硅通孔电极而电性耦接至第二上表面上的第二电路；以及一背侧金属层，形成于第二下表面上且电性耦接至焊盘中的一第二次组焊盘，背侧金属层配送由第二次组焊盘所提供的电子信号。
本发明由于硅通孔电极接线结构而使设计周期与制造良率都有显著的改善。
附图说明
图1示出根据一集成电路剖面示意图。
图2a示出第一系统单芯片的剖面示意图。
图2b示出第二系统单芯片的剖面示意图。
图2c示出第三系统单芯片的剖面示意图。
图3a示出公知电源供应网路(power mesh)平面示意图。
图3b示出一集成电路剖面示意图，其中集成电路使用公知电源供应网路。
图4a示出一集成电路底视平面示意图。
图4b示出用于一集成电路中电源配送的栅网矩阵排列平面示意图。
图4c示出用于一集成电路，其中信号至集成电路的内部电路的配送是通过硅通孔电极。
图5a示出用于一集成电路中电源配送的栅网矩阵排列分划平面示意图。
图5b示出用于一集成电路中电源配送的栅网矩阵排列分划平面示意图。
其中，附图标记说明如下：
公知
400～电源供应网路；
405～第一网路；
410～第二网路；
415～第一网线；
416～第二网线；
420～电源焊盘；
450～集成电路；
455、465～焊料凸块；
460～电源布线；
470～信号布线；
实施例
200～集成电路；
205～电源通孔电极结构；
206～信号通孔电极结构；
207～第一导电焊盘；
208～内部金属布线；
209～导电构件；
210～基底；
215～电源接线；
216～信号接线；
220～背侧金属层；
222～电源通孔电极；
225～电源/接地布线；
226～信号布线；
230、510、511、515、516～焊盘；
300、325～系统级芯片；
305、330～母芯片；
310、335、340、345～子芯片；
520～虚线；
525～电源环；
600、650～分划；
605～芯片边界；
610～次区边界；
615、620、655、660～硅通孔电极。
具体实施方式
以下说明本发明实施例的制作与使用。然而，可轻易了解本发明实施例提供许多合适的发明概念而可实施于广泛的各种特定背景。所揭示的特定实施例仅仅用于说明以特定方法制作及使用本发明，并非用以局限本发明的范围。
以下说明本发明实施例的一特定背景，即包括多重芯片的系统级封装(system in a package，SiP)。然而，上述实施例也可应用于三维堆叠的多重芯片模块、系统单芯片(system on a chip，SoC)、含单芯片的集成电路等等。
如之前所述，打线接合对于半导体封装的组装提供了成本效益及弹性的解决之道。然而，在高功率产品应用中，又长又薄(因而具有高阻值)的接线会造成大量的电流-电阻(IR)压降。大量的IR压降迫使需采用具有较高电压的电源供应器，其难以实施或需要更高的成本。大量的IR压降也迫使操作上需降低噪声容限度(noise margin)，其导致装置更容易受到电源噪声的影响。
采用倒装芯片技术有助于在高功率产品应用中降低IR压降。然而，倒装芯片技术需在多重芯片之间使用堆叠通孔结构来进行电源及信号配送，其导致较高的制造成本。另外，在具有垂直堆叠的多重芯片的系统级封装(SiP)中，电源及信号配送必须通过整个垂直堆叠结构。此需要垂直堆叠结构中下方的倒装芯片对于通过倒装芯片的所有电源及信号具有内建补偿(built-incompensation)。此需要下方的倒装芯片大于需要补偿额外电源及信号而通过的倒装芯片。
图1示出集成电路200的剖面示意图。集成电路200的制造采用了硅通孔电极(TSV)结构，其中可经由穿过基底210的硅通孔电极来进行电源及信号的配送，例如电源通孔电极结构205及信号通孔电极结构206。经由硅通孔电极，电源及信号可通过典型结构中的内部金属层而配送至内部电路。
硅通孔电极，例如电源通孔电极结构205，包括形成于基底210的一第一表面上的一第一导电焊盘207，以及填入基底210内的通孔的一导电构件209，且可连接至位于基底210的一第二表面上的内部金属布线208。导电构件209电性连接第一导电焊盘207及内部金属布线208。接着内部金属布线208可用于配送电子信号及/或电源。
然而，除了内部金属布线208之外，电源及信号的配送也可通过背侧金属层(backside metal layer，BML)220。背侧金属层220可形成于背向基底210的集成电路的一侧上。背侧金属层220可用于电源及信号的配送。集成电路200可使用接线进行对外的连接，例如电源接线215及信号接线216。
背侧金属层220较佳由铝、铜、金、及其合金等所构成，以提供用于电源及信号配送的一低电阻金属。背侧金属层220的厚度也可大于常规的金属层，以进一步降低背侧金属层220的电阻率。降低背侧金属层220的电阻率可具有低的IR压降。由于背侧金属层220不具有前侧金属层机械应力及通孔尺寸限制，因此以上所述是合理的。背侧金属层220的总厚度较佳为常规金属层的厚度的至少二倍(2×)，以降低其电阻率。再者，背侧金属层220可为垂直、水平、对角线、锯齿形或任意排列，用以配送电源，而较佳为对角线排列。背侧金属层220也称作重布局线(redistribution layer，RDL)。
较佳的是将背侧金属层220与电源或信号电性连接，而硅通孔电极(如，电源通孔电极222)可用于将电源或信号连接至背侧金属层220。由于硅通孔电极的尺寸通常小于焊盘，因此通孔电极直接接合至背侧金属层220内的焊盘上，使背侧金属层220保有最小的尺寸大小。当使用大量的硅通孔电极来供应电源至背侧金属层220以将IR压降最小化时，较小尺寸的硅通孔电极特别具有优势。若采用打线接合来将电源及信号电性连接至背侧金属层220，使用硅通孔电即可不妨碍其他集成电路贴合至集成电路200。
除了经由硅通孔电极连接电源及信号之外，也可经由与背侧金属层220形成于相同侧的连接线来将背侧金属层220电性连接至电源及信号。与背侧金属层220形成于相同侧的连接线可直接连接至一焊盘。
可使用形成于内部金属层内电源及信号布线来进行额外的电源及信号配送。电源/接地(P/G)布线225及信号布线226。再者，当难以检验内部金属层的配送或者造成大量的IR压降时，背侧金属层220可用于额外的电源及信号配送弹性测量。硅通孔电极可用于内部金属层与背侧金属层220之间的连接。
集成电路200包括焊盘，例如焊盘230，以容许在集成电路200上放置焊料凸块，其可容许集成电路200连接至外部电路或是其他使用倒装芯片技术的集成电路。集成电路200可为包括多重集成电路的系统单芯片(SoC)的一部分。图2a示出系统单芯片300。系统单芯片300包括一母芯片(motherdie)305及一子芯片(daughter die)310。子芯片310可使用倒装芯片技术而直接装贴于母芯片305上。集成电路200也可为系统级封装(SiP)的一部分。
图2b示出系统单芯片325。系统单芯片325包括一母芯片330、一子芯片335、一子芯片340及一子芯片345。子芯片335直接装贴于母芯片330上，而子芯片340直接装贴于子芯片335上，且子芯片345直接装贴于子芯片340上。虽然附图中为四个垂直堆叠芯片，然而系统单芯片也可由其他可能的芯片组合所构成。举例来说，在另一系统单芯片中，子芯片335及子芯片340可装贴于母芯片330的不同部分上，且子芯片345可装贴于子芯片340上。另外，子芯片335、子芯片340及子芯片345可分别装贴于母芯片330的不同部分上。因此，本发明实施例的精神及范围并未局限于附图上的单一垂直堆叠。
然而，不同于倒装芯片技术中电源及信号是经由垂直堆叠中最下层集成电路或转接板(interposer)来配送，采用硅通孔电极接线结构的集成电路垂直堆叠，例如集成电路200，可将电源及信号连接至各别的集成电路。图2c示出打线接合之后的系统单芯片325。每一芯片(母芯片330、子芯片335、子芯片340及子芯片345)可使用接线进行外部连接。由外部连接至每一芯片能够将电源及信号直接配送至芯片上而无需规划未使用的电源及信号通过任何芯片。其有助于将IR压降最小化。再者，由于芯片不需规划未使用的电源及信号，因此可将芯片的尺寸最小化。如图2c所示，使用硅通孔电极将电源及信号电性耦接至背侧金属层220可容许集成电路(例如，子芯片335装贴于母芯片330、子芯片340装贴于子芯片335、以此类推)装贴于集成电路中与背侧金属层220相同的一侧上。
随着技术的提升，设计复杂度显著的增加。设计复杂度的增加导致设计中具有庞大的装置总数及功能性。然而，增加装置总数导致较高的电源消耗。较高的电源消耗需求导致不仅需要大量的电源焊盘来供应内部电路所需的电源，而且需要密集的电源供应网路来将IR压降最小化。密集的电源供应网路及相关的电源焊盘消耗了设计中大量的可用电源及信号布线资源。因此，设计的芯片尺寸及制造成本皆有显著的增加。
图3a示出公知的电源供应网路400。电源供应网路400包括配送电性接地(GND)的一第一网路405以及配送一第一电压(VDD)的一第二网路410。第一网路405及第二网路410可由不同层所构成，例如不同的金属层或是一者为金属层而另一者为非金属的导电层。在网线(例如第一网线415与第二网线416)的交界处，一电源焊盘(例如，电源焊盘420)可构成二网线之间的电性连接。再者，电源焊盘下方可为电源布线，以提供电源至内部电路。如图3a所示，集成电路中相当多的布线资源(大约为总布线资源的30％或以上)用于电源信号的布线。
图3b示出集成电路450的剖面示意图，其中集成电路450包括公知的电源供应网路，用以将电源配送至集成电路450。如图3b所示，焊料凸块455用于第二网路410与VDD之间的电性连接。电源布线460将电源连接至集成电路450中的一第一晶体管。请参照图3b，一焊料凸块465通过一信号布线470而提供一信号至一第二晶体管。使用于电源及信号布线中的堆叠连接窗阵列(via array)，例如电源布线460以及信号布线470，塞满于集成电路450内，使得集成电路450内的内部信号布线更为困难。
图4a示出具有背侧金属层220的集成电路200的底视平面示意图。如之前所述，背侧金属层220用于电源及信号的配送。背侧金属层220可具有一环形结构，具有一电源环525形成于集成电路200的周边，但通常位于多个焊盘内侧，上述焊盘包括用以将外部信号连接至内部信号的焊盘(例如，焊盘510及511)以及用以提供内部电路电源及接地的电源焊盘(例如，焊盘515及516)。上述焊盘可构成单一的焊盘环且围绕电源环525，如图4a所示。另外，取决于上述焊盘的数量，多重焊盘环或少于单一焊盘环的焊盘可围绕电源环525。
请参照图4a，电源环525及焊盘可形成于集成电路200的周边。然而，取决于电源及信号配送需求，电源环525可不形成于集成电路200的周边。另外，电源环525可形成于集成电路200的背侧或前侧上或是集成电路200的两侧。
电源环525内侧为多个硅通孔电极(如虚线520内侧所示)。上述硅通孔电极可用于配送电源至集成电路200的内部电路。上述硅通孔电极可电性耦接至电源环525外侧的电源焊盘。举例来说，上述硅通孔电极的一些硅通孔电极可接地，而其他的硅通孔电极可电性耦接至VDD。上述硅通孔电极可水平、垂直、对角线、锯齿形或任意排列，，而较佳为对角线排列。另外，硅通孔电极的排列可受集成电路200的内部电路的排列所支配而没有特定的排列。电源环525可将一些或所有的电源焊盘连接至上述硅通孔电极。电源环525可由背侧金属(即，电源环525可与背侧金属层220形成于同一侧)、前侧金属(即，电源环525可与背侧金属层220形成于相对侧)、或其组合所构成。
硅通孔电极的优势在于其小于电源及/或信号焊盘。因而焊盘间距放宽，使得整体面积缩减。另外，硅通孔电极容许使用低成本的接线作为信号及电源的连接。再者，硅通孔电极有助于解决多重芯片堆叠的问题，其中芯片堆叠中位于上方的芯片，其电源必须布线经过芯片堆叠中位于下方的芯片。此有助于缓和必须将芯片堆叠中下方的芯片的区域用于配送电源至芯片堆叠中位于上方的芯片。相似地，硅通孔电极可通过直接将电源连接至芯片堆叠中的芯片而解决IR压降问题。虽然图4a所示的是连接电源焊盘，然而上述硅通孔电极中一些硅通孔电极可电性连接至信号焊盘。
图4b示出用于一集成电路中电源配送的栅网矩阵排列平面示意图。栅网矩阵可用于电源配送，其中电流经过低电阻的硅通孔电极(例如，上述硅通孔电极)而直接流至集成电路的内部电路。栅网矩阵排列容许使用少数金属层(例如，金属层1及金属层2)作为局部电源连接。栅网矩阵排列可连接至背侧金属层220以进一步改善整体电源配送。请参照图4c，其示出一集成电路的剖面示意图，其中集成电路包括背侧金属层220及用于集成电路中电源配送的栅网矩阵排列。如图4c所示，由于电源配送于背侧金属层220及栅网矩阵排列，因此集成电路中大部分的内部金属层可用于信号配送。图4c也示出信号经由一硅通孔电极而配送至集成电路内部电路。
图5a示出用于一集成电路中电源配送的栅网矩阵排列分划600平面示意图。集成电路通常可划分成一栅网系统，其由一最小栅网及一最大栅网(如芯片边界605及次区(tile)边界610)所组成，其中最大栅网为多重的最小栅网。接着，硅通孔电极可放置于多重相邻区块共有的边界上。举例来说，硅通孔电极615可用于配送VDD，而硅通孔电极620可用于配送电性接地(VSS)。
图5b示出用于一集成电路中电源配送的栅网矩阵排列分划650平面示意图。栅网矩阵排列分划650相似于栅网矩阵排列分划600，差别在于栅网矩阵排列分划650中的硅通孔电极退离次区边界610而形成隔离的电压岛(voltage island)。举例来说，硅通孔电极655可仅用于配送VDD至单一电压岛，而硅通孔电极660可仅用于配送VSS至上述单一电压岛。
内部电路可在栅网矩阵排列之后设置，以最小化电流供应而不会遭遇任何金属布线阻碍的问题。电源栅网排列可为垂直、水平、对角线、锯齿形排列等等，而较佳为对角线排列。
硅通孔电极接线结构可提供多于倒装芯片结构的优点。表1提供了硅通孔电极接线结构与使用电源供应网路配送电源(N45工艺)的倒装芯片结构之间差异比较。
表1：硅通孔电极接线结构与具有电源供应网路的倒装芯片结构
如表1所示，硅通孔电极接线结构与具有电源供应网路配送电源的倒装芯片结构之间显著差异包括：电流从低电阻的硅通孔电极直接流入装置，而不是经由多重金属层来配送(因而具有低IR压降)；不需要密集的中介(intermediate)电源布线，仅需少许金属层提供局部电源连接，因而显著增加可布线能力(routability)；栅网矩阵排列直接连接至背侧金属层以提供更佳的电流配送；相同电阻值的硅通孔电极尺寸小于堆叠连接窗阵列尺寸的10倍；降低芯片尺寸与所需的金属层数量；以及硅通孔电极接线结构中电源噪声大幅降低。另外，由于硅通孔电极接线结构而使设计周期与制造良率都有显著的改善。
虽然本发明已以较佳实施例公开如上，然其并非用以限定本发明，任何所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，当可作各种更动、替代与润饰。再者，本发明的保护范围并未局限于说明书内所述特定实施例中的工艺、机器、制造、物质组成、装置、方法及步骤，任何所属技术领域中普通技术人员可从本发明揭示内容中理解现行或未来所发展出的工艺、机器、制造、物质组成、装置、方法及步骤，只要可以在此处所述实施例中实施大体相同功能或获得大体相同结果皆可使用于本发明中。因此，本发明的保护范围包括上述工艺、机器、制造、物质组成、装置、方法及步骤。

Claims (10)

1.一种集成电路，包括：
一基底，具有一上表面及一下表面，其中一电路形成于该上表面上；
多个焊盘，形成于该下表面的周边，其中所述多个焊盘中的一第一次组焊盘经由多个硅通孔电极而电性耦接至该上表面上的该电路；以及
一背侧金属层，形成于该下表面上且电性耦接至所述多个焊盘中的一第二次组焊盘，该背侧金属层配送由该第二次组焊盘所提供的电子信号。
2.如权利要求1所述的集成电路，其中该第一次组焊盘中耦接至所述多个焊盘的每一硅通孔电极包括：
一第一导电焊盘，形成于该底表面；
一第二导电焊盘，形成于该上表面；以及
一导电构件，将该第一导电焊盘电性耦接至该第二导电焊盘，该导电构件形成于该基底内的一孔洞内。
3.如权利要求1所述的集成电路，其中该第二次组焊盘内的所述多个焊盘接地或耦接至一第一电压，该背侧金属层包括排列成一栅网图案的多个导体连接至耦接于该上表面上的该电路的所述多个硅通孔电极，以配送电性接地或该第一电压至该上表面上的该电路，且该背侧金属层还包括至少一凸块焊盘耦接至一硅通孔电极，该硅通孔电极作为该集成电路与一贴合的集成电路或一外部基底之间的电性连接。
4.如权利要求1所述的集成电路，其中该背侧金属层形成于由所述多个焊盘所构成的一边界内。
5.一种集成电路，包括：
一基底，具有一上表面及一下表面，其中一电路形成于该上表面上；
一第一焊盘，设置于该下表面上，其中该第一焊盘经由一硅通孔电极而电性耦接至该上表面上的该电路；以及
一背侧金属层，设置于该下表面上且电性耦接至设置于该下表面上的一第二焊盘，该背侧金属层配送由该第二焊盘所提供的一第一信号。
6.如权利要求5所述的集成电路，其中该第二焊盘经由两个硅通孔电极而电性耦接至该背侧金属层，其中一第一硅通孔电极将该第二焊盘的该第一信号传送至该上表面，且一第二硅通孔电极将该第一信号传送至该背侧金属，其中该第一硅通孔电极经由一导体而电性耦接至该第二硅通孔电极。
7.如权利要求5所述的集成电路，其中该背侧金属层更配送由一第三焊盘所提供的一第二信号，其中该第三焊盘直接耦接至该背侧金属层。
8.如权利要求5所述的集成电路，还包括一电源环，设置于该基底的周边，该电源环配送电源至该上表面上的该电路。
9.一种三维堆叠的多重芯片模块，包括：
一第一集成电路，包括一第一基底，其具有一第一上表面及一第一下表面，其中一第一电路形成于该第一上表面上；以及
一第二集成电路，包括：
一第二基底，具有一第二上表面及一第二下表面，其中一第二电路形成于该第二上表面上；
多个第一焊盘，形成于该第二下表面的周边，其中所述多个第一焊盘中的一第一次组焊盘经由多个第一硅通孔电极而电性耦接至该第二上表面上的该第二电路；以及
一第一背侧金属层，形成于该第二下表面上且电性耦接至所述多个第一焊盘中的一第二次组焊盘，该第一背侧金属层配送由该第二次组焊盘所提供的电子信号；
其中该第一集成电路贴合至该第二集成电路。
10.如权利要求9所述的三维堆叠的多重芯片模块，其中该第一集成电路还包括：
多个第二焊盘，形成于该第一下表面的周边，其中所述多个第二焊盘中的一第三次组焊盘经由多个第二硅通孔电极而电性耦接至该第一上表面上的该第一电路，其中所述多个第二焊盘的每一焊盘经由接线电性耦接至外部信号；以及
一第二背侧金属层，形成于该第一下表面上且电性耦接至所述多个第二焊盘中的一第四次组焊盘，该第二背侧金属层配送由该第四次组焊盘所提供的电子信号。
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