JP2003243560A - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JP2003243560A JP2003243560A JP2002035400A JP2002035400A JP2003243560A JP 2003243560 A JP2003243560 A JP 2003243560A JP 2002035400 A JP2002035400 A JP 2002035400A JP 2002035400 A JP2002035400 A JP 2002035400A JP 2003243560 A JP2003243560 A JP 2003243560A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- substrate
- hole
- insulating film
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/114—Pad being close to via, but not surrounding the via
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
- H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
- H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
- H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
- H01L2224/4848—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball outside the semiconductor or solid-state body
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/12—Passive devices, e.g. 2 terminal devices
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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Abstract
半導体装置を提供する。 【解決手段】半導体チップおよびはんだボールを搭載す
る基板(109)と、基板のはんだボール(111)搭
載側に形成され、はんだボールを搭載する第1の孔(2
11)と、基板のボール搭載側と反対側に形成され、導
通用の第1の孔より小径の第2の孔(311)と、基板
全体に形成された絶縁膜(108)と、絶縁膜上に形成
された導電性金属の配線(107,108)とを積層し
た配線層とを備え、第1の孔と第2の孔が、基板を貫通
してなる。
Description
し、特に、発熱量の大きい半導体装置に関する。
基板とヒートスプレッダもしくはヒートシンクを備えて
いる。このような発熱量の大きい、従来の第1の半導体
装置は、例えば、特開平10−199899号公報に開
示されている。
使用して、ヒートスプレッダと呼ばれる放熱板を具備す
る。
半導体装置が特開平11−97586号公報に、およ
び、従来の第3の半導体装置が特開2001−2742
02号公報に開示されている。
形成された従来の第4の半導体装置が特開平8−559
31号公報の図4に開示されている。この従来の第4の
半導体装置は、金属箔ラミネートを行いエッチングにて
配線を形成する構成である。
10−199899号公報に記載の従来の第1の半導体
装置は、チップの部分が、はんだボールを搭載できず、
パッケージ寸法が大きくなる。また、従来の第2の半導
体装置、および、従来の第3の半導体装置は、基板に樹
脂を使用しており、放熱性がよくない。
上部からの配線を形成する場合、この孔がへこみ蒸着等
によるファインな配線を形成することは困難である。従
来の第4の半導体装置は、金属箔ラミネートを行いエッ
チングにて配線を形成する手法で形成されるから、配線
幅を25μm以下にすることは困難である。
側からのみ行っているので小径の穴を形成することは困
難である。エッチング反応速度のばらつきにより孔の大
きさがバラツク。従って、上方の配線接続部の大きさを
必要以上に大きくするため接続部同士の間に形成する配
線の本数が少なくなる。
レッダを必要とする発熱量の大きい半導体装置で、低コ
ストの基板を提供し、パッケージ全体にはんだボールを
搭載しパッケージサイズを小さくすることである。本発
明は蒸着方法により配線を形成するため0.5μm以下
の配線幅が可能である。
半導体チップ上の電極とパッケージとを金属細線によっ
て接合配線される半導体装置において、前記半導体チッ
プおよびはんだボールを搭載する基板と、前記基板の前
記はんだボール搭載側に形成され、前記はんだボールを
搭載する第1の孔と、前記基板のボール搭載側と反対側
に形成され、導通用の前記第1の孔より小径の第2の孔
と、前記基板全体に形成された絶縁膜と、前記絶縁膜上
に形成された導電性金属の配線とを積層した配線層とを
備え、前記第1の孔と前記第2の孔が前記基板を貫通し
てなる構成である。
金属であり、前記金属は銅、チタン、アルミ、鉄であ
る。
明の実施の形態の半導体装置について、詳細に説明す
る。図1は、本発明の第1の実施の形態の半導体装置の
構成を示す断面図である。
半導体装置は、電流消費量が大きいため発熱量の大きい
半導体装置で、チップ101やはんだボール111を搭
載する基板109に金属を使用し、金属は銅、チタン、
アルミ、鉄等を素材としている。
基板109は、はんだボール111搭載側には、はんだ
ボールを搭載する孔をエッチングやドリル加工、レーザ
加工等により形成し、基板109のはんだボール111
搭載側と反対側には、同様にして、導通用の更に小径の
穴を形成し、貫通孔とする。
は、基板全体を酸化シリコン、酸化チタン、窒化アルミ
ナ、樹脂等で絶縁膜108を蒸着や接着等で形成した
後、導電性金属の銅やアルミで配線107を形成する。
る。基板にチップを接合搭載し、ワイヤー102をパッ
ド104にワイヤボンディングする、または、バンプに
て接合し、樹脂封入を行う。金属基板の孔にも前記導電
性金属を蒸着して、はんだボールを搭載しリフローによ
り接合して、放熱性を高め低コストで製造できる。
実施の形態の半導体装置は、厚さ125μm程度の銅板
基板109の下方より、直径が400μm程度のはんだ
ボール直径より少し小さい釣鐘上の孔112をエッチン
グにて下より100μm程度形成する。
13を、同じくエッチングにて形成する。さらに、本発
明の第1の実施の形態の半導体装置基板全体を酸化手法
により絶縁膜108を形成する。レジスト液を塗布し、
露光にて上側は第1層の配線107を形成する。釣鐘状
の孔112にも、配線材と同じ導電性金属110を形成
する。
り導通する。基板109の上面には続いて第2層、第3
層と必要な配線層を形成する。チップ101を接合し、
ワイヤ102をボンディングする。
だボール111を搭載する。
す断面図である。図2を参照すると、本発明の半導体装
置は、まず、基板109にレジスト液を塗布し、所定の
位置を露光し、はんだボール111の直径より少し小さ
い孔(211、212)をエッチングにて形成される。
基板109の厚みは125μmであるが、孔(211、
212)の深さは、100μm程度となり、釣鐘形状と
なる。
直径30μm程度の孔(311、312)が形成され
る。
剤にて絶縁膜608が形成される。図5では、基板10
9の上下にレジスト液を塗布し、所定の位置を露光す
る。レジスト液のないところに導電性金属を蒸着し、配
線ならびにはんだボールの孔で導電層110が形成され
る。図6では、同様な手法で、基板の上方に絶縁膜60
6を形成し、第2層目の配線106を形成する。同様な
手法で第3層以上も形成する。
搭載し、ワイヤボンディングをし、樹脂103の封入を
行う。図8では、はんだボール111を設置する。その
後リフローを行いはんだボール111を接合する。
の半導体装置の構成を示す断面図である。
形態の半導体装置は、銅基板のワイヤボンディングする
個所をエッチングやドリル加工、レーザ加工等により孔
を形成する。
下方より接着剤にて銅箔を貼り付ける。ボンディング点
とはんだボールを搭載する点をエッチング加工により形
成する。ボンディング点とはんだボール搭載点を蒸着等
により配線する。
ワイヤボンディングを行う。ワイヤボンディングは銅箔
側からパッドへのリバースボンディングで行う。これに
より基板のボンディング用孔を最小限に小さくできる。
はんだボール搭載個所以外は絶縁膜でカバーする。はん
だボールを搭載する。
によれば、熱伝導性の高い銅等の金属基板に直接チップ
を搭載し、配線を行い、はんだボールを搭載するため
に、従来必要であったヒートスプレッダが不要となり、
実装面積が小さくなる効果がある。
図である。
フローを説明する半導体装置の第1の断面図である。
フローを説明する半導体装置の第2の断面図である。
フローを説明する半導体装置の第3の断面図である。
フローを説明する半導体装置の第4の断面図である。
フローを説明する半導体装置の第5の断面図である。
フローを説明する半導体装置の第6の断面図である。
フローを説明する半導体装置の第7の断面図である。
図である。
Claims (13)
- 【請求項1】 半導体チップ上の電極とパッケージとを
金属細線によって接合配線される半導体装置において、 前記半導体チップおよびはんだボールを搭載する基板
と、前記基板の前記はんだボール搭載側に形成され、前
記はんだボールを搭載する第1の孔と、前記基板のボー
ル搭載側と反対側に形成され、導通用の前記第1の孔よ
り小径の第2の孔と、前記基板全体に形成された絶縁膜
と、前記絶縁膜上に形成された導電性金属の配線とを積
層した配線層とを備え、前記第1の孔と前記第2の孔が
前記基板を貫通してなることを特徴とする半導体装置。 - 【請求項2】 前記基板は、金属である請求項1記載の
半導体装置。 - 【請求項3】 前記金属は、銅である請求項2記載の半
導体装置。 - 【請求項4】 前記金属は、チタンである請求項2記載
の半導体装置。 - 【請求項5】 前記金属は、アルミである請求項2記載
の半導体装置。 - 【請求項6】 前記金属は、鉄である請求項2記載の半
導体装置。 - 【請求項7】 前記第1の孔および前記第2の孔は、エ
ッチングで加工される請求項1、2、3、4、5または
6記載の半導体装置。 - 【請求項8】 前記第1の孔および前記第2の孔は、ド
リルで加工される請求項1、2、3、4、5または6記
載の半導体装置。 - 【請求項9】 前記第1の孔および前記第2の孔は、レ
ーザーで加工される請求項1、2、3、4、5または6
記載の半導体装置。 - 【請求項10】 前記絶縁膜は、酸化シリコンである請
求項1、2、3、4、5、6、7、8または9記載の半
導体装置。 - 【請求項11】 前記絶縁膜は、酸化チタンである請求
項1、2、3、4、5、6、7、8または9記載の半導
体装置。 - 【請求項12】 前記絶縁膜は、窒化アルミナである請
求項1、2、3、4、5、6、7、8または9記載の半
導体装置。 - 【請求項13】 前記絶縁膜は、樹脂である請求項1、
2、3、4、5、6、7、8または9記載の半導体装
置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002035400A JP2003243560A (ja) | 2002-02-13 | 2002-02-13 | 半導体装置 |
US10/352,036 US20030151139A1 (en) | 2002-02-13 | 2003-01-28 | Semiconductor device |
CN03103845A CN1438698A (zh) | 2002-02-13 | 2003-02-12 | 半导体器件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002035400A JP2003243560A (ja) | 2002-02-13 | 2002-02-13 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2003243560A true JP2003243560A (ja) | 2003-08-29 |
Family
ID=27654971
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002035400A Pending JP2003243560A (ja) | 2002-02-13 | 2002-02-13 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20030151139A1 (ja) |
JP (1) | JP2003243560A (ja) |
CN (1) | CN1438698A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009171732A (ja) * | 2008-01-16 | 2009-07-30 | Nissan Motor Co Ltd | 電力変換装置 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040118349A1 (en) * | 2002-12-19 | 2004-06-24 | 3M Innovative Properties Company | Vapor deposition shield for optical fibers |
TWI299551B (en) * | 2003-06-25 | 2008-08-01 | Via Tech Inc | Quad flat no-lead type chip carrier |
US20050085016A1 (en) * | 2003-09-26 | 2005-04-21 | Tessera, Inc. | Structure and method of making capped chips using sacrificial layer |
US20050116344A1 (en) * | 2003-10-29 | 2005-06-02 | Tessera, Inc. | Microelectronic element having trace formed after bond layer |
US20060183270A1 (en) * | 2005-02-14 | 2006-08-17 | Tessera, Inc. | Tools and methods for forming conductive bumps on microelectronic elements |
US8143095B2 (en) | 2005-03-22 | 2012-03-27 | Tessera, Inc. | Sequential fabrication of vertical conductive interconnects in capped chips |
SG130061A1 (en) * | 2005-08-24 | 2007-03-20 | Micron Technology Inc | Microelectronic devices and microelectronic support devices, and associated assemblies and methods |
US20070138644A1 (en) * | 2005-12-15 | 2007-06-21 | Tessera, Inc. | Structure and method of making capped chip having discrete article assembled into vertical interconnect |
US7936062B2 (en) | 2006-01-23 | 2011-05-03 | Tessera Technologies Ireland Limited | Wafer level chip packaging |
US7772107B2 (en) * | 2006-10-03 | 2010-08-10 | Sandisk Corporation | Methods of forming a single layer substrate for high capacity memory cards |
US8604605B2 (en) | 2007-01-05 | 2013-12-10 | Invensas Corp. | Microelectronic assembly with multi-layer support structure |
JP5330697B2 (ja) * | 2007-03-19 | 2013-10-30 | 株式会社リコー | 機能素子のパッケージ及びその製造方法 |
US8264067B2 (en) * | 2009-10-09 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through silicon via (TSV) wire bond architecture |
CN102157477B (zh) * | 2011-03-23 | 2012-10-03 | 南通富士通微电子股份有限公司 | 半导体装置的制造方法 |
DE112013001425T5 (de) * | 2012-03-15 | 2014-12-18 | Fuji Electric Co., Ltd. | Halbleitervorrichtung und Verfahren zum Herstellen derselben |
US9508702B2 (en) * | 2013-09-27 | 2016-11-29 | Freescale Semiconductor, Inc. | 3D device packaging using through-substrate posts |
US9508701B2 (en) | 2013-09-27 | 2016-11-29 | Freescale Semiconductor, Inc. | 3D device packaging using through-substrate pillars |
US9515006B2 (en) * | 2013-09-27 | 2016-12-06 | Freescale Semiconductor, Inc. | 3D device packaging using through-substrate posts |
US10147673B2 (en) * | 2016-09-30 | 2018-12-04 | Stmicroelectronics, Inc. | Tapeless leadframe package with underside resin and solder contact |
-
2002
- 2002-02-13 JP JP2002035400A patent/JP2003243560A/ja active Pending
-
2003
- 2003-01-28 US US10/352,036 patent/US20030151139A1/en not_active Abandoned
- 2003-02-12 CN CN03103845A patent/CN1438698A/zh active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009171732A (ja) * | 2008-01-16 | 2009-07-30 | Nissan Motor Co Ltd | 電力変換装置 |
Also Published As
Publication number | Publication date |
---|---|
CN1438698A (zh) | 2003-08-27 |
US20030151139A1 (en) | 2003-08-14 |
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