TWI824647B - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TWI824647B
TWI824647B TW111129311A TW111129311A TWI824647B TW I824647 B TWI824647 B TW I824647B TW 111129311 A TW111129311 A TW 111129311A TW 111129311 A TW111129311 A TW 111129311A TW I824647 B TWI824647 B TW I824647B
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Taiwan
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package
die
vias
semiconductor package
molding compound
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TW111129311A
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TW202308071A (zh
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郭哲宏
楊忠旻
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聯發科技股份有限公司
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Abstract

本發明公開一種半導體封裝，包括：底部封裝，包括由模塑料包圍的應用處理器晶粒；頂部封裝，安裝在該底部封裝上；頂部重分佈層結構，設置在該頂部封裝和該底部封裝之間；複數個貫穿模制通孔，設置在該模塑料中，用於將該頂部封裝與該應用處理器晶粒電連接，其中，該複數個貫穿模制通孔中的每一個在俯視時具有橢圓形或矩形形狀；以及底部重分佈層結構，其中該應用處理器晶粒和該複數個貫穿模制通孔互連到該底部重分佈層結構。

Description

半導體封裝
本發明涉及半導體技術領域，尤其涉及一種半導體封裝。
由於行動(mobile)應用新興市場的快速增長，封裝技術變得比以往任何時候都更具挑戰性，推動先進的矽(Si)節點(node)、更精細的凸塊間距(bump pitch)以及更精細的線寬(line width)和間距基板製造能力，以滿足行動設備(mobile device)日益增長的需求。
封裝上封裝(Package on Package，PoP)技術已用於組合離散封裝(discrete package)。PoP通常由兩個封裝組成，例如包含記憶體晶片的頂部封裝安裝在包含邏輯晶片的底部封裝上。頂部封裝可以透過中介層連接到底部封裝。
業界亟需一種新穎的PoP封裝結構，其中邏輯晶片與存儲晶片之間的連接路徑的長度需要進一步縮短，以提高電性能。
有鑑於此，本發明提供一種半導體封裝，具有減小的連接長度，以解決上述問題。
根據本發明的第一方面，公開一種半導體封裝，包括：底部封裝，包括由模塑料包圍的應用處理器晶粒；頂部封裝，安裝在該底部封裝上；頂部重分佈層結構，設置在該頂部封裝和該底部封裝之間； 複數個貫穿模制通孔，設置在該模塑料中，用於將該頂部封裝與該應用處理器晶粒電連接，其中，該複數個貫穿模制通孔中的每一個在俯視時具有橢圓形或矩形形狀；以及底部重分佈層結構，其中該應用處理器晶粒和該複數個貫穿模制通孔互連到該底部重分佈層結構。
根據本發明的第二方面，公開一種半導體封裝，包括：半導體基板，具有有源區和由該有源區包圍的無源區；多晶矽電阻結構，設置在該無源區的隔離結構上，並沿第一方向延伸；虛設多晶矽電阻結構，沿第二方向排列在該隔離結構上並沿第一方向延伸；以及多晶矽環狀結構，設置於該隔離結構上，環繞該多晶矽電阻結構，其中該虛設多晶矽電阻結構沿該第二方向設置於該多晶矽電阻結構與該多晶矽環狀結構之間。
根據本發明的第三方面，公開一種半導體封裝，包括：至少一個邏輯晶片，由該模塑料包圍；記憶體裝置，設置在該至少一個邏輯晶粒附近；複數個通孔，圍繞該至少一個邏輯晶粒，用於將該至少一個邏輯晶粒電連接到該記憶體裝置，其中當從上方觀察時，該複數個通孔中的每一個具有橢圓形或矩形形狀。
本發明的半導體封裝由於包括：底部封裝，包括由模塑料包圍的應用處理器晶粒；頂部封裝，安裝在該底部封裝上；頂部重分佈層結構，設置在該頂部封裝和該底部封裝之間；複數個貫穿模制通孔，設置在該模塑料中，用於將該頂部封裝與該應用處理器晶粒電連接，其中，該複數個貫穿模制通孔中 的每一個在俯視時具有橢圓形或矩形形狀；以及底部重分佈層結構，其中該應用處理器晶粒和該複數個貫穿模制通孔互連到該底部重分佈層結構。將貫穿模制通孔中的每一個設置為橢圓形或矩形，並且其中橢圓形或矩形的寬度較長度小，使得貫穿模制通孔之間的間距相對於先前技術中圓形的貫穿模制通孔之間的間距更小，從而使相同數量的貫穿模制通孔佔用的寬度(或尺寸)更小，使這些貫穿模制通孔更加向中間位置靠攏，這樣就可以讓設置在應用處理器晶粒的焊盤連接到貫穿模制通孔時的路徑變短，從而縮小了應用處理器晶粒連接到貫穿模制通孔，以及連接到記憶體封裝的連接長度。
1,2,3,4,5:半導體封裝
ST:凸塊
20,40:頂部封裝
PI:凸塊焊盤
PT:金屬跡線
RT,RS,705,1004,1007:RDL結構
110v,320v,1006v:TMV
10,30:底部封裝
S1,S2,S3:頂表面
PB:球焊盤
IS:互連
100,300,500:AP晶粒
100a:有源表面
101:導電凸塊
SB:焊球
PD:無源元件
DL:介電層
110,320,520,1006:模塑料
D1:第一方向
D2:第二方向
W:寬度
Sh,Sv,P1,P2:間距
L:長度
310:兩層基板
330:多層基板
510:頂部橋接基板
522:通孔基板
522v,704v:通孔
530,80:基板
600:記憶體裝置
PP:訊號路徑
70:扇出晶片封裝
701,702,1001,1002,1003:邏輯晶粒
703:橋接通孔基板
704:週邊通孔結構
90:記憶體封裝
1005:TSV晶粒
1005v:矽通孔
透過閱讀後續的詳細描述和實施例可以更全面地理解本發明，本實施例參照附圖給出，其中：圖1是顯示根據本發明實施例的示例性半導體封裝的示意性截面圖；圖2是根據本發明實施例的AP晶粒周圍的TMV的局部俯視佈局示意圖；圖3顯示了以3x2陣列排列的交錯TMV；圖4顯示了示例性HBPoP；圖5示出了示例性半導體封裝；圖6示出了另一示例性半導體封裝；以及圖7示出又一示例性半導體封裝。
在下面對本發明的實施例的詳細描述中，參考了附圖，這些附圖構成了本發明的一部分，並且在附圖中透過圖示的方式示出了可以實踐本發明的 特定的優選實施例。對這些實施例進行了足夠詳細的描述，以使所屬技術領域具有通常知識者能夠實踐它們，並且應當理解，在不脫離本發明的精神和範圍的情況下，可以利用其他實施例，並且可以進行機械，結構和程式上的改變。本發明。因此，以下詳細描述不應被理解為限制性的，並且本發明的實施例的範圍僅由所附申請專利範圍限定。
將理解的是，儘管術語“第一”、“第二”、“第三”、“主要”、“次要”等在本文中可用於描述各種元件、元件、區域、層和/或部分，但是這些元件、元件、區域、這些層和/或部分不應受到這些術語的限制。這些術語僅用於區分一個元件、元件、區域、層或部分與另一區域、層或部分。因此，在不脫離本發明構思的教導的情況下，下面討論的第一或主要元件、元件、區域、層或部分可以稱為第二或次要元件、元件、區域、層或部分。
此外，為了便於描述，本文中可以使用諸如“在...下方”、“在...之下”、“在...下”、“在...上方”、“在...之上”之類的空間相對術語，以便於描述一個元件或特徵與之的關係。如圖所示的另一元件或特徵。除了在圖中描述的方位之外，空間相對術語還意圖涵蓋設備在使用或運行中的不同方位。該設備可以以其他方式定向(旋轉90度或以其他定向)，並且在此使用的空間相對描述語可以同樣地被相應地解釋。另外，還將理解的是，當“層”被稱為在兩層“之間”時，它可以是兩層之間的唯一層，或者也可以存在一個或複數個中間層。
術語“大約”、“大致”和“約”通常表示規定值的±20%、或所述規定值的±10%、或所述規定值的±5%、或所述規定值的±3%、或規定值的±2%、或規定值的±1%、或規定值的±0.5%的範圍內。本發明的規定值是近似值。當沒有具體描述時，所述規定值包括“大約”、“大致”和“約”的含義。本文所使用的術語僅出於描述特定實施例的目的，並不旨在限制本發明。如本文所使 用的，單數術語“一”，“一個”和“該”也旨在包括複數形式，除非上下文另外明確指出。本文所使用的術語僅出於描述特定實施例的目的，並不旨在限制本發明構思。如本文所使用的，單數形式“一個”、“一種”和“該”也旨在包括複數形式，除非上下文另外明確指出。
將理解的是，當將“元件”或“層”稱為在另一元件或層“上”、“連接至”、“耦接至”或“鄰近”時，它可以直接在其他元件或層上、與其連接、耦接或相鄰、或者可以存在中間元件或層。相反，當元件稱為“直接在”另一元件或層“上”、“直接連接至”、“直接耦接至”或“緊鄰”另一元件或層時，則不存在中間元件或層。
注意：(i)在整個附圖中相同的特徵將由相同的附圖標記表示，並且不一定在它們出現的每個附圖中都進行詳細描述，並且(ii)一系列附圖可能顯示單個專案的不同方面，每個方面都與各種參考標籤相關聯，這些參考標籤可能會出現在整個序列中，或者可能只出現在序列的選定圖中。
本發明涉及具有減小(或更短)的連接長度的半導體封裝，其適用於包括但不限於扇出層疊封裝(fan-out package-on-package，扇出PoP)和高頻寬層疊封裝(high-bandwidth package-on-package，HBPoP)的應用.
“扇出(fan-out)”封裝可以定義為任何具有從晶片表面扇出連接的封裝，從而支持更多的外部I/O(輸入/輸出，input/output)。傳統的扇出封裝使用環氧樹脂模塑料來完全嵌入晶粒，而不是將它們放置在基板或中介層上。扇出封裝通常涉及在矽晶圓(silicon wafer)上切割晶片，然後將已知良好的晶片非常精確地定位在薄的“重組”或載體晶圓上，然後對其進行模制，然後在模制區域(晶片和扇出區域)頂部形成重分佈層(redistribution layer，RDL)，然後在頂部形成焊球。HBPoP通常包括頂部2層(2-layer)基板、中間成型件(middle molding)和底部3層(3-layer)基板(三層基板)，以封裝 應用處理器(application processor，AP)晶片。與扇出PoP相比，HBPoP的AP封裝成本更低。
圖1是顯示根據本發明實施例的示例性半導體封裝的示意性截面圖。如圖1所示，半導體封裝1可以是扇出PoP，但不限於此。根據一個實施例，半導體封裝1可以包括底部封裝10和安裝在底部封裝10上的頂部封裝20。例如，底部封裝10包括被模塑料110包圍(圍繞)的應用處理器(AP)晶粒100。介電層DL可以設置在AP晶粒100的有源表面(主動面)100上。複數個導電凸塊或柱101可以設置在介電層DL中並且可以電耦合到有源表面100a。在執行研磨或化學機械拋光(chemical mechanical polishing，CMP)製程之後，介電層DL的頂面(上表面)S1可以與周圍的模塑料110的頂面(上表面)S2共面(或齊平)。
根據本發明一個實施例，重分佈層(re-distributed layer，RDL)結構RS可以設置在介電層DL的頂表面(上表面)S1和周圍的模塑料110的頂表面S2上。RDL結構RS可以包括多層互連IS。根據本發明一個實施例，複數個球焊盤PB可以分佈在RDL結構RS的頂表面S3上。焊球SB可以安裝在每個球焊盤PB上以用於進一步連接。可選地，諸如去耦電容器或任何合適的表面貼裝器件(surface mount device，SMD)的無源元件(被動元件)PD可以設置在焊球SB之間的RDL結構RS的頂表面S3上。
根據本發明一個實施例，複數個貫穿模制通孔(through molding via，TMV)110v設置在模塑料110中以將RDL結構RS電連接到上覆的重分佈層(RDL)結構RT(RDL結構RS與RDL結構RT分別設置在模塑料110相對的兩側)。根據一個實施例，RDL結構RT可以至少包括複數個凸塊焊盤PI和用於連接凸塊焊盤PI與TMV 110v的金屬跡線PT。頂部封裝20透過諸如微凸塊的凸塊ST安裝在凸塊焊盤PI上。根據本發明一個實施例，例如，頂部封裝20可以是DRAM封裝，例如DDR DRAM封裝。在一些實施例中，TMV 110v可以是插入柱或焊點。頂部封裝 20可以是記憶體封裝。
請參考圖2。圖2為本發明一個實施例的圖1中AP晶粒100周圍的TMV 110v的局部俯視佈局示意圖。如圖2所示，當從上面看時，每個TMV 110v可以具有橢圓形或矩形形狀。每個TMV 110v沿第二方向D2或通孔到晶粒100的方向伸長。每個TMV 110v的最大長度(尺寸)為L，每個TMV 110v的最大寬度(尺寸)為W，其中L大於W；以上這些形狀大小的描述適用於橢圓形或矩形形狀。
根據一個實施例，示例性3x2陣列中的TMV 110v可以沿第一方向D1(即與AP晶粒100的相鄰側邊緣平行的方向)具有W+Sh的水平間距P1，其中Sh是在沿第一方向D1的兩個相鄰TMV 110v之間的間距。根據一個實施例，3x2陣列中的TMV 110v可具有沿第二方向D2的L+Sv的垂直間距P2，其中Sv是沿第二方向D2的兩個相鄰TMV 110v之間的間距。根據一個實施例，第一方向D1與第二方向D2正交。根據本發明一個實施例，TMV 110v的垂直間距P2大於水平間距P1。
透過提供這樣的配置，TMV 110v可以比現有技術更緊密地佈置在AP晶粒100周圍。由於橢圓形的TMV 110v，特別是那些設置在半導體封裝1的週邊區域或拐角區域的TMV 110v，可以減少記憶體封裝(頂部封裝)20和AP晶粒100之間的連接長度。具體來說，如圖2所示，將每個TMV 110v設置為橢圓形或矩形，並且其中橢圓形或矩形的寬度較長度小，使得TMV 110v之間的間距P1相對於先前技術中圓形的TMV 110v之間的間距更小，從而使相同數量的TMV 110v(橢圓形或矩形)佔用的寬度(或尺寸)更小，使這些TMV 110v更加向中間位置靠攏，這樣就可以讓設置在AP晶粒100的焊盤連接到TMV 110v(橢圓形或矩形)時的路徑變短，從而縮小了AP晶粒100連接到TMV 110v(橢圓形或矩形)，以及連接到記憶體封裝(頂部封裝)20的連接長度。如圖2所示的示例中，上述的焊盤可以是設置在AP晶粒100的與TMV 110v相鄰或靠近的一側的焊盤。對於位於(靠近或相鄰)AP晶粒100不同側的TMV 110v，垂直於AP晶粒100相對應 的一側延伸的方向為TMV 110v的長度方向(第二方向)，而平行於AP晶粒100相對應的該一側延伸的方向為TMV 110v的寬度方向(第一方向)，並且將TMV 110v的寬度設置為較長度小，這樣就可以使在AP晶粒100相對應的該一側的寬度方向上設置相同的TMV 110v時，佔用該一側的寬度方向上的距離更小，也即在寬度方向上TMV 110v(陣列)設置的更加緊湊，從而讓AP晶粒100相對應的該一側上的焊盤可以以更短的路徑(更短的佈線長度)連接到TMV 110v，減少連接路徑。
為簡單起見，僅一個3x2陣列的TMV 110v如圖所示。根據本發明一個實施例，兩行TMV 110v可以在第二方向D2上彼此對齊。根據另一個實施例，如圖3所示，TMV 110v的3x2陣列可以是交錯的，即前排與後排錯開。採用這種方式可以提供不同的需求設計，增加設計彈性。
如圖2和圖3所示的橢圓形TMV 110v可以適用於其他種類的半導體封裝，例如HBPoP。圖4圖示了示例性HBPoP。如圖4所示，HBPoP 2具有底部封裝30和頂部封裝40，例如安裝在底部封裝30上的DRAM封裝。底部封裝30包括頂部2層(2-層或兩層)基板310、中間模塑料(中間成型件或模塑料)320、以及底部多層基板330，用於封裝應用處理器(AP)晶粒300。同樣，複數個TMV 320v設置在AP晶粒300周圍。TMV 320v設置在模塑料320中並且用於電連接頂部2層(2-層或兩層)基板310與底部多層基板330。設置在中間模塑料中的TMV 320v將頂部封裝與AP晶粒電連接，其中複數個TMV中的每一個具有橢圓形狀、矩形形狀或其組合。如圖2和圖3所示的TMV 110v設置在AP晶粒100的上側，此時第一方向D1為AP晶粒100的寬度方向，為了使得佈置相同的TMV 110v時佔用寬度方向上的尺寸更少，根據本發明上述實施例，即可將TMV 110v在第一方向D1(也即此時AP晶粒100的寬度方向，或稱為與該TMV 110v靠近或相鄰的AP晶粒100的一側的寬度方向)尺寸進行縮小(例如設置為本 實施例中的橢圓形或矩形)，而使得每個TMV 110v在第一方向D1上的寬度(或尺寸)小於每個TMV 110v在第二方向D2上的長度(或尺寸)，其中第二方向D2垂直於第一方向D1。對於AP晶粒100其他的側，可以根據上述描述對應設置，也即在對應的AP晶粒100的該一側的寬度方向上(也即與該一側平行的方向上)，每個TMV 110v的尺寸更小(每個TMV 110v在該寬度方向上的尺寸比每個TMV 110v在於該寬度方向相垂直的方向上(也即與該一側垂直的方向上)的尺寸小)。採用本發明上述實施例的方式，可以讓每個TMV 110v在平行於該AP晶粒100對應的一側的方向上(也即寬度方向上)的尺寸縮小(小於垂直於該AP晶粒100對應的一側的方向上(也即長度方向上)的尺寸)，從而使佈置相同數量的TMV 110v佔用的寬度方向上的尺寸更小，TMV 110v的佈置更加緊湊，這樣該AP晶粒100對應的一側的焊盤連接到TMV 110v的線路長度將更短，從而顯著減小了訊號傳輸路徑，提高了半導體封裝的電氣性能。
圖5示出了示例性半導體封裝。如圖5所示，半導體封裝3包括由模塑料520封裝並由具有複數個通孔522v的通孔基板522圍繞的AP晶粒500。AP晶粒500和諸如DRAM封裝的記憶體裝置600以並排方式安裝在基板530上。頂部橋接基板(bridge substrate)510設置在通孔基板522和模塑料520上。訊號路徑PP顯示來自AP晶粒500的訊號透過左側的基板530、通孔基板522和通孔522v傳輸、頂部橋接基板510、右側的過孔(或通孔)基板522和過孔(或通孔)522v，以及基板530傳輸到記憶體晶粒600。如圖2和圖3所示的矩形或橢圓形過孔(或通孔)522v可以顯著減少訊號傳輸路徑PP的連接長度(減少佈線的長度)，所以提高了半導體封裝3的電氣性能。
圖6示出了另一示例性半導體封裝。如圖6所示，半導體封裝4包括安裝在基板80上的扇出晶片封裝70。扇出晶片封裝70和諸如DRAM封裝的記憶體封裝(頂部封裝)90以並排方式安裝在基板上。根據一些實施例，扇出晶片封 裝70可以包括兩個邏輯晶粒701和702，它們互連到橋接通孔基板703和圍繞橋接通孔基板703的週邊通孔結構704。RDL結構705設置在橋接通孔基板703與基板80之間以及週邊通孔結構704與基板80之間。如圖2和圖3所示的矩形或橢圓形通孔704v可以顯著提高半導體封裝4的電性能，因為連接可以減少訊號傳輸路徑的長度。
圖7示出又一示例性半導體封裝。如圖7所示，半導體封裝5可以包括邏輯晶粒1001和1002，以及透過RDL結構1004互連的記憶體晶粒1003。RDL結構1004進一步互連到由模塑料1006包圍的矽通孔(TSV)晶粒1005。TSV晶粒1005包括穿過TSV晶粒1005的複數個矽通孔1005v。複數個TMV 1006v設置在模塑料1006中用於訊號傳輸。TMV 1006v可以透過底部RDL結構1007電連接到TSV晶粒1005。此外，TSV晶粒1005可以透過底部RDL結構1007、TMV 1006v和RDL結構1004電連接到邏輯晶粒1001和1002以及記憶體晶粒1003。如圖2和圖3所示的矩形或橢圓形過孔(或通孔)1006v可以顯著提高半導體封裝5的電性能，因為可以減少訊號傳輸路徑的連接長度。
儘管已經對本發明實施例及其優點進行了詳細說明，但應當理解的是，在不脫離本發明的精神以及申請專利範圍所定義的範圍內，可以對本發明進行各種改變、替換和變更。所描述的實施例在所有方面僅用於說明的目的而並非用於限制本發明。本發明的保護範圍當視所附的申請專利範圍所界定者為准。本領域技術人員皆在不脫離本發明之精神以及範圍內做些許更動與潤飾。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1:半導體封裝
ST:凸塊
20:頂部封裝
PI:凸塊焊盤
PT:金屬跡線
RT,RS:RDL結構
110v:TMV
10:底部封裝
S1,S2,S3:頂表面
PB:球焊盤
IS:互連
100:AP晶粒
100a:有源表面
101:導電凸塊
SB:焊球
PD:無源元件
DL:介電層
110:模塑料

Claims (9)

  1. 一種半導體封裝，包括：底部封裝，包括由模塑料包圍的應用處理器晶粒；頂部封裝，安裝在該底部封裝上；頂部重分佈層結構，設置在該頂部封裝和該底部封裝之間；複數個貫穿模制通孔，設置在該模塑料中，用於將該頂部封裝與該應用處理器晶粒電連接，其中，該複數個貫穿模制通孔中的每一個在俯視時具有橢圓形或矩形形狀；以及底部重分佈層結構，其中該應用處理器晶粒和該複數個貫穿模制通孔互連到該底部重分佈層結構；其中，該複數個貫穿模制通孔設置為與該應用處理器晶粒的側邊緣相鄰以及設置在該底部封裝的拐角區域，該複數個貫穿模制通孔具有沿第一方向的水平間距和沿第二方向的垂直間距，其中該垂直間距大於該水平間距。
  2. 如請求項1之半導體封裝，其中，該複數個貫穿模制通孔沿該第二方向排列。
  3. 如請求項1之半導體封裝，其中，該複數個貫穿模制通孔以交錯方式排列。
  4. 如請求項1之半導體封裝，其中，複數個焊球設置於該底部重布層結構的表面上。
  5. 一種半導體封裝，包括：底部封裝，包括頂部兩層基板、中間模塑料和底部多層基板，用於封裝應用處理器晶粒；頂部封裝，安裝在該底部封裝上；複數個貫穿模制通孔，設置在該中間模塑料中，用於將該頂部封裝與該應 用處理器晶粒電連接，其中，當俯視時，該複數個貫穿模制通孔中的每一個具有橢圓形或矩形形狀；其中，該複數個貫穿模制通孔設置為與該應用處理器晶粒的側邊緣相鄰以及設置在該底部封裝的拐角區域，該複數個貫穿模制通孔具有沿第一方向的水平間距和沿第二方向的垂直間距，其中該垂直間距大於該水平間距。
  6. 一種半導體封裝，包括：至少一個邏輯晶粒，由模塑料包圍；記憶體裝置，設置在該至少一個邏輯晶粒附近；複數個通孔，圍繞該至少一個邏輯晶粒，用於將該至少一個邏輯晶粒電連接到該記憶體裝置，其中當從上方觀察時，該複數個通孔中的每一個具有橢圓形或矩形形狀；其中，該複數個通孔設置為與該至少一個邏輯晶粒的側邊緣相鄰以及設置在該半導體封裝的拐角區域，該複數個通孔具有沿第一方向的水平間距和沿第二方向的垂直間距，其中該垂直間距大於該水平間距。
  7. 如請求項6之半導體封裝，還包括：頂部橋接基板，與該複數個通孔互連。
  8. 如請求項6之半導體封裝，還包括：與該至少一個邏輯晶粒互連的橋接通孔基板。
  9. 如請求項6之半導體封裝，還包括：由該模塑料圍繞的矽通孔晶粒，其中該複數個通孔設置在該模塑料中。
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