TW201735287A - 用於具有分離的表面安裝及引線接合安裝表面的垂直整合之嵌入式引線接合線 - Google Patents

用於具有分離的表面安裝及引線接合安裝表面的垂直整合之嵌入式引線接合線 Download PDF

Info

Publication number
TW201735287A
TW201735287A TW105141581A TW105141581A TW201735287A TW 201735287 A TW201735287 A TW 201735287A TW 105141581 A TW105141581 A TW 105141581A TW 105141581 A TW105141581 A TW 105141581A TW 201735287 A TW201735287 A TW 201735287A
Authority
TW
Taiwan
Prior art keywords
wire
microelectronic device
microelectronic
coupled
wire bond
Prior art date
Application number
TW105141581A
Other languages
English (en)
Inventor
賈維爾Ａ 迪拉克魯茲
阿比歐拉 奧佐拉
阿修克Ｓ 普拉布
克里斯多夫Ｗ 拉丁
孫卓文
Original Assignee
英帆薩斯公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 英帆薩斯公司 filed Critical 英帆薩斯公司
Publication of TW201735287A publication Critical patent/TW201735287A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/117—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0284—Details of three-dimensional rigid printed circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/1623—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705—Shape
    • H01L2224/17051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48108—Connecting bonding areas at different heights the connector not being orthogonal to a side surface of the semiconductor or solid-state body, e.g. fanned-out connectors, radial layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

在一種垂直整合的微電子封裝中，一第一微電子裝置係在該微電子封裝的一只有引線接合的表面區域中耦接至一電路平台的一上表面。引線接合線係耦接至該第一微電子裝置的一上表面，而且從該第一微電子裝置的該上表面延伸離開。一處於一面朝下的朝向的第二微電子裝置係在一只有表面安裝的區域中耦接至該些引線接合線的上方的末端。該第二微電子裝置係位在該第一微電子裝置之上，而且至少部分地重疊該第一微電子裝置。一保護層係被設置在該電路平台以及該第一微電子裝置之上。該保護層的一上表面係具有該只有表面安裝的區域。該保護層的該上表面係在該只有表面安裝的區域中具有被設置於其上的處於該面朝下的朝向的該第二微電子裝置，以用於耦接至該些第一引線接合線的該些上方的末端。

Description

用於具有分離的表面安裝及引線接合安裝表面的垂直整合之嵌入式引線接合線
以下的說明係大致有關用於垂直整合的引線接合線。更具體而言，以下的說明係有關於互連接至一封裝的各種的表面的引線接合線，以用於分離的表面安裝表面以及引線接合安裝表面的多層級的互連。
相關申請案之交互參照
此申請案茲主張在2015年12月30日申請的美國臨時專利申請案序號US 62/273,145的優先權，該專利申請案的整體係藉此為了所有的目的而被納入在此作為參考。
微電子組件一般包含一或多個IC，例如是一或多個經封裝的晶粒("晶片")或是一或多個晶粒。此種IC中的一或多個可被安裝在一電路平台之上，例如一像是晶圓層級封裝("WLP")的晶圓、印刷板("PB")、一印刷線路板("PWB")、一印刷電路板("PCB")、一印刷線路組件("PWA")、一印刷電路組件("PCA")、一封裝基板、一中介體、或是一晶片載體。此外，一IC可被安裝在另一IC之上。一中介體可以是一被動式IC或是一主動式IC， 其中後者係包含一或多個例如是電晶體的主動裝置，而前者並不包含任何主動裝置，但是可包含一或多個例如是電容器、電感器、及/或電阻器的被動裝置。再者，一中介體可被形成像是一PWB，亦即不具有任何的電路元件，例如是不具有任何被動或主動裝置。此外，一中介體可包含至少一穿過基板的貫孔(via)。
一IC例如可包含導電的元件，例如是路徑、線路、軌跡、貫孔、接點、像是接觸墊及焊墊的墊、插塞、節點、或是端子，其可被使用於與一電路平台電互連。這些配置可以使得被用來提供IC的功能的電連接變得容易。一IC可以藉由接合來耦接至一電路平台，例如是接合此種電路平台的線路或端子至一IC的焊墊或是接腳或柱的露出的末端或類似者；或是一IC可以藉由焊接來耦接至一電路平台。此外，一重分佈層("RDL")可以是一IC的部分，以例如使得一覆晶的配置、晶粒堆疊、或是焊墊的更便利或可接達的位置變得容易。
某些被動或主動微電子裝置可被使用在一系統級封裝("SiP")或是其它多晶粒/構件的封裝內。然而，對於某些應用而言，某些SiP可能會佔用過大的區域。再者，對於某些低矮的應用而言，某些SiP可以被使用；然而，利用穿過基板的貫孔來形成一用於堆疊的SiP對於某些應用而言可能是過於昂貴的。
於是，提供用於一SiP的垂直整合將會是所期望而且有用的。
一種設備係大致有關於一垂直整合的微電子封裝。在此種設 備中，一電路平台係具有一上表面以及一與其之上表面相對的下表面。該電路平台的上表面係具有一只有引線接合的表面區域。一第一微電子裝置係在該只有引線接合的表面區域中耦接至該電路平台的上表面。第一引線接合線係耦接至該第一微電子裝置的一上表面，而且從該第一微電子裝置的該上表面延伸離開。一處於一面朝下的朝向的第二微電子裝置係在一只有表面安裝的區域中耦接至該些第一引線接合線的上方的末端。該第二微電子裝置係位在該第一微電子裝置之上，而且至少部分地重疊該第一微電子裝置。第二引線接合線係在該只有引線接合的表面區域中耦接至該電路平台的上表面，並且耦接至該第一微電子裝置的上表面。一保護層係被設置在該電路平台以及該第一微電子裝置之上。該保護層係具有一下表面以及一與其之下表面相對的上表面，其中該保護層的下表面係接觸該電路平台的上表面。該保護層的上表面係具有該只有表面安裝的區域。該保護層的上表面係在該只有表面安裝的區域中具有被設置於其上的處於該面朝下的朝向的該第二微電子裝置，以用於耦接至該些第一引線接合線的上方的末端。
一種設備係大致有關於一倒置的垂直整合的微電子封裝。在此種設備中，一電路平台係具有一上表面以及一與其之上表面相對的下表面。該電路平台的下表面係具有一只有引線接合的表面區域。一第一微電子裝置係在該只有引線接合的表面區域中耦接至該電路平台的下表面。第一引線接合線係耦接至該第一微電子裝置的一下表面，而且從該第一微電子裝置的該下表面延伸離開。一處於一面朝上的朝向的第二微電子裝置係在一只有表面安裝的區域中耦接至該些第一引線接合線的下方的末端。該 第二微電子裝置係位在該第一微電子裝置之下，而且至少部分地下方重疊該第一微電子裝置。第二引線接合線係在該只有引線接合的表面區域中耦接至該電路平台的下表面，而且從該電路平台的下表面延伸離開，並且耦接至該第一微電子裝置的下表面。一保護層係被設置在該電路平台以及該第一微電子裝置之下。該保護層係具有一下表面以及一與其之下表面相對的上表面，其中該保護層的上表面係接觸該電路平台的下表面。該保護層的下表面係具有該只有表面安裝的區域。該保護層的下表面係具有在該只有表面安裝的區域中被設置於其上的處於該面朝上的朝向的該第二微電子裝置，以用於耦接至該些第一引線接合線的下方的末端。
一種設備係大致有關於一微電子構件。在此種設備中有一具有一第一上表面的基板。一導電層係被設置在該第一上表面上，該第一上表面係包含分別具有第一上表面以及第二上表面的引線接合墊以及覆晶的墊。一焊料遮罩係被設置在介於該些引線接合墊以及該些覆晶的墊之間的該第一上表面上。該焊料遮罩係具有一被設置在該些第一上表面以及該些第二上表面之上的第二上表面。一共晶層係被設置在該些第一上表面以及該些第二上表面上。引線接合線係分別接合至該些引線接合墊。
10‧‧‧系統級封裝(SiP)
11‧‧‧主動微電子裝置
12‧‧‧被動微電子裝置
13‧‧‧IC晶粒
15‧‧‧引線接合
17‧‧‧微凸塊互連
19‧‧‧封裝基板
19L‧‧‧下方的封裝基板
19U‧‧‧上方的封裝基板
20‧‧‧EMI屏蔽
21、22‧‧‧引線接合
23‧‧‧頂端導電板
24‧‧‧底部導電板
100‧‧‧SiP(多個微電子裝置的封裝)
100L‧‧‧下方的SiP
100U‧‧‧上方的SiP
130‧‧‧導電的表面
131‧‧‧引線接合線
131i‧‧‧內部的引線接合線
131L‧‧‧下方的引線接合線
131o‧‧‧外部的引線接合線
131s‧‧‧信號引線接合線
131U‧‧‧上方的引線接合線
132‧‧‧上表面
133‧‧‧屏蔽區域
136‧‧‧BVA配置
137‧‧‧孔洞
140‧‧‧接地面
140L‧‧‧下方的接地面
140U‧‧‧上方的接地面
141‧‧‧球體接合
142‧‧‧貫孔
143‧‧‧模製層
144‧‧‧間隙
145‧‧‧微電子裝置
145L‧‧‧下方的微電子裝置
145U‧‧‧微電子裝置
146‧‧‧上表面
148‧‧‧上方的末端(尖端)
149‧‧‧下表面
150‧‧‧導電的覆蓋
153‧‧‧法拉第籠
160‧‧‧接地面
161‧‧‧互連
162‧‧‧貫孔
165‧‧‧微電子裝置
168‧‧‧上表面
169‧‧‧上方的基板
170‧‧‧焊墊
171‧‧‧間距
180‧‧‧互連
190‧‧‧堆疊式封裝的(PoP)裝置
191‧‧‧互連
192L‧‧‧下方的法拉第籠
192U‧‧‧上方的法拉第籠
200‧‧‧垂直整合的微電子封裝
201‧‧‧上表面
202‧‧‧上表面(只有SMT的表面區域)
203‧‧‧側壁
204‧‧‧互連共晶體
231、231-1‧‧‧引線接合線
252‧‧‧最下面的表面
261、262、263、264‧‧‧整體完成後的長度
271‧‧‧微電子裝置
274‧‧‧互連共晶體
400‧‧‧電路平台
401‧‧‧電路平台
402、402-1‧‧‧黏著層
403‧‧‧下表面
404‧‧‧側壁表面
405‧‧‧上表面
406‧‧‧下表面
407‧‧‧上表面
408‧‧‧上表面
410‧‧‧微電子裝置
411‧‧‧微電子裝置
413‧‧‧互連(微凸塊)
414‧‧‧中介體(電路平台)
415‧‧‧互連
416‧‧‧微電子裝置
418‧‧‧互連表面
431‧‧‧引線接合線
432‧‧‧引線接合線
441‧‧‧上表面
501‧‧‧互連(球體)
502‧‧‧SMT積體電路晶粒(接觸墊)
503、503-1‧‧‧引線接合的積體電路晶粒
505‧‧‧下表面
507‧‧‧間隙區域
508‧‧‧只有引線接合的區域
509‧‧‧只有SMT的區域(引線接合線)
510‧‧‧只有SMT的區域
511‧‧‧主動微電子裝置
512‧‧‧被動微電子裝置
531、531-1、531-2‧‧‧引線接合線
541‧‧‧焊墊
600‧‧‧基板
601‧‧‧引線接合墊
602‧‧‧覆晶的墊
603‧‧‧導電層
604‧‧‧焊料遮罩
605‧‧‧上表面
606、607‧‧‧間隙
608、609‧‧‧焊料墊
611‧‧‧上表面
613‧‧‧上表面
615‧‧‧上表面
616‧‧‧上表面
617‧‧‧下表面
648‧‧‧接點
649‧‧‧覆晶的IC晶粒
650‧‧‧微電子構件
所附的圖式係展示根據範例的設備或方法的一或多個特點之範例實施例。然而，所附的圖式不應該被視為限制申請專利範圍的範疇，而只是用於解說及理解而已。
圖1A是描繪一範例的習知的系統級封裝("SiP")的側視方塊圖。
圖1B是描繪另一範例的習知的SiP的側視方塊圖。
圖2是描繪一習知的電磁干擾("EMI")屏蔽的一範例的部分之角落的俯視立體圖。
圖3A及3B是描繪個別的具有EMI屏蔽的範例的SiP的俯視方塊圖。
圖4是描繪一具有EMI屏蔽的範例的SiP的側視橫截面方塊圖。
圖5是描繪一範例的SiP的側視橫截面方塊圖，其係具有一導電的覆蓋並且具有在該導電的覆蓋之下的一EMI屏蔽區域中的信號引線接合線。
圖6是描繪一具有利用一上方的基板的EMI屏蔽的範例的SiP的側視橫截面方塊圖。
圖7是描繪在一法拉第籠(Faraday cage)的一上方的導電的表面的加入之前的一SiP的一範例的部分的俯視方塊圖。
圖8是描繪在一法拉第籠的一上方的導電的表面的加入之前的另一SiP的一範例的部分的俯視方塊圖。
圖9A是描繪一具有EMI屏蔽的堆疊式封裝("PoP")裝置的一範例的部分的側視橫截面方塊圖。
圖9B是描繪另一具有EMI屏蔽的PoP裝置的一範例的部分的側視橫截面方塊圖。
圖10是描繪另一SiP的一範例的部分的側視橫截面方塊圖。
圖11A是描繪一SiP的一範例的部分的側視橫截面方塊圖。
圖11B是描繪另一SiP的一範例的部分的側視橫截面方塊圖。
圖12A至12D是描繪個別的SiP的範例的部分之個別的側視橫截面方塊圖。
圖13A至13D是描繪個別的具有垂直整合的微電子封裝的SiP的範例 的部分之個別的側視橫截面方塊圖。
圖14A至14D是描繪用於一垂直整合的微電子封裝的範例的SiP之個別的側視橫截面方塊圖。
圖15A至15D是描繪一範例的SiP之個別的側視橫截面方塊圖。
圖16A及16B是描繪範例的SiP 100之個別的側視橫截面方塊圖。
圖17A至17C是描繪範例的倒置的SiP之個別的側視橫截面方塊圖。
圖18A至18D是描繪引線接合墊以及覆晶的墊在同一基板上的進展形成的側視方塊圖。
在以下的說明中，許多特定的細節係被闡述，以提供在此所述的特定例子之更徹底的說明。然而，對於熟習此項技術者而言應該明顯的是，一或多個其它例子或是這些例子的變化可以在無所有以下給出的特定細節下加以實施。在其它實例中，眾所週知的特點並未詳細地敘述，以防模糊在此的例子的說明。為了便於說明起見，相同的元件符號係在不同的圖中被使用以參照到相同的項目；然而，在替代的例子中，該些項目可以是不同的。
範例的設備及/或方法係在此加以描述。應瞭解的是，該字詞"範例的"係在此被使用以表示"當作為一個例子、實例、或是例證"。任何在此敘述為"範例"的例子或特點並不一定被解釋為相對其它例子或特點為較佳或是有利的。
在微電子裝置中的干擾可能是來自於電磁干擾("EMI")及/或射頻干擾("RFI")。干擾屏蔽的以下的說明可被使用於這些類型的干擾的任一 種或是兩者。然而，為了舉例且非限制性之清楚的目的起見，大致只有針對EMI的屏蔽係在以下用額外的細節來加以描述。
圖1A是描繪一範例的習知系統級封裝("SiP")的側視方塊圖。在SiP 10中，可以有耦接至一封裝基板19的一或多個主動微電子裝置11、被動微電子裝置12、及/或IC晶粒13。在此例子中，可以是一被動式或主動式的晶粒的IC晶粒13可能會遭受到EMI。IC晶粒13可以利用引線接合15而被引線接合至封裝基板19，該些引線接合15是用於載有輸入/輸出信號及其它信號、一電源電壓、以及接地參考電壓。
封裝基板19可以是由稱為積層或積層基板的薄層所形成的。積層可以是有機或無機的。用於"剛性"封裝基板的材料例子係包含一例如是FR4或FR5的環氧樹脂基的積層、一例如是雙馬來醯亞胺-三嗪("BT")樹脂基的積層、一陶瓷基板(例如，一低溫共燒陶瓷("LTCC"))、一玻璃基板、或是其它形式的剛性封裝基板。再者，一封裝基板19在此可以是一PCB或是其它電路板。為了清楚的目的起見，其它有關習知的SiP 10的已知的細節並未被敘述。
圖1B是描繪另一範例的習知的SiP 10的側視方塊圖。除了例如是微凸塊的覆晶的("FC")互連17被使用，而不是引線接合15之外，圖1B的SiP 10係與圖1A的SiP 10相同的。即使微凸塊互連17係說明性地被描繪，但是其它類型的晶粒表面安裝的互連亦可被使用。再者，儘管未說明性地描繪在圖1B中，但是微凸塊互連17可以在引線接合15之外另外被使用。
圖2是描繪一習知的EMI屏蔽20的一範例的部分的角落的 俯視立體圖。在習知的EMI屏蔽20中，一頂端導電板23可被設置在一底部導電板24之上，其中此種底部導電板24係具有一大於此種頂端導電板23的表面積。
導電板23及24分別可以耦接至一具有引線接合21及22的列之封裝基板19。因此，頂端板23的兩個側邊可以與對應的列的引線接合21來加以引線接合，並且底部板24的兩個側邊同樣地可以與對應的列的引線接合22來加以引線接合。非導電的間隙壁(未顯示)可被用來隔離引線接合21與底部導電板24。一待被EMI屏蔽的微電子裝置(未顯示)可被夾設在頂端及底部導電板23及24之間。此類型的具有引線接合的EMI屏蔽對於許多應用而言可能是過於龐大的。再者，在相關提供側邊EMI屏蔽的引線接合之相對的側邊上可能會有間隙。
干擾屏蔽
圖3A及3B是描繪個別的具有EMI屏蔽之範例的SiP 100的俯視方塊圖。SiP 100的每一個都可包含一封裝基板19，其係具有耦接至其之一上表面132的一或多個主動微電子裝置11、一或多個被動微電子裝置12、以及引線接合線131，其中此種引線接合線131的下方的末端可以耦接至封裝基板19的一上表面132。上表面132可以是一導電的表面。引線接合線131可包含等於或小於約0.0508毫米(2密耳)的導線直徑。
引線接合線131的一部分可被設置以界定一屏蔽區域133。以此種方式，引線接合線131的一BVA配置136的列與行可被用來包圍或者是圍繞一屏蔽區域133。此種引線接合線131的至少一子集合之圍繞一屏蔽區域133的上方的末端可被用來支撐導電的表面130，因而此種導電的表 面130可以是在此種屏蔽區域133之上，以用於其之覆蓋。
導電的表面130可以是一導電的剛性或撓性的表面。在一實施方式中，導電的表面130可以是撓性的，例如是在一撓性的片的一表面上之一撓性的導電的塗層。在另一實施方式中，一剛性板可以提供一導電的表面。一剛性板可以是由一種導電材料所做成的。然而，一導電的塗層可被噴塗或是擦塗在一剛性板或是撓性的片上。在圖3B的例子中，如同在以下以額外的細節敘述的，導電的表面130可以具有孔洞137，以用於容許引線接合線131中的界定一屏蔽區域133的至少某些個的上方的部分能夠延伸穿過導電的表面130。
圖4是描繪一具有EMI屏蔽之範例的SiP 100的側視橫截面方塊圖。SiP 100可包含一封裝基板19，其係具有耦接至其之一上表面132的一或多個主動微電子裝置11、一或多個被動微電子裝置12、以及引線接合線131，其中此種引線接合線131的上方的末端可以耦接至一導電的表面130。即使一SiP 100係被描述，但是其它類型的具有免於EMI的保護的微電子封裝亦可被使用。
封裝基板19係具有一上表面132以及一與該上表面相對的下表面149。封裝基板19可以具有位在表面132及149之間的一接地面140以及貫孔142，其中貫孔142可以為了導電而互連接至此種接地面140。
引線接合線131可以利用貫孔142來耦接至接地面140。某些引線接合線131可以利用用於導電的球體接合141來機械式地耦接至上表面132；然而，在其它實施方式中，其它類型的接合亦可被使用。再者，並非所有的引線接合線131都需要耦接至接地面140。某些引線接合線131可 被使用於在SiP 100之內載有供應電壓或信號。某些引線接合線131可被使用於耦接至在SiP 100之內的其它裝置。
一主動或被動的微電子裝置145可以耦接至封裝基板19的上表面132。微電子裝置145可包含一主動的積體電路晶粒及/或一被動構件。一被動構件例如可以是一電容器、一電感器、或是一電阻器、或是其之任意組合。
微電子裝置145可以利用如先前所述的球體或凸塊互連及/或引線接合線來耦接至封裝基板19。再者，微電子裝置145可以利用一黏著劑或是一底膠填充層(未顯示)來耦接至上表面132。
微電子裝置145可被設置在一介電保護材料中，該介電保護材料可被設置為圍堰填充(dam fill)或是一模製層("模製層")143。此種模製層143可以是一密封劑或是一模製材料，以用於至少覆蓋微電子裝置145的一上表面及側壁。引線接合線131可被設置在微電子裝置145的側壁的周圍。
導電的表面130可以是位在介電保護材料模製層143的一頂端或上表面146之上、或是耦接至其。然而，在另一實施方式中，如同在以下以額外的細節敘述的，介電保護材料模製層143的一頂表面可以是位在一高於引線接合線131的尖端148的高度處。導電的表面130可被設置在和法拉第籠153相關的引線接合線131之上。此種引線接合線131的上方的末端或尖端148可以機械式地耦接至導電的表面130。此耦接可以是利用一熱壓接合或是其它形式的機械式耦接。
法拉第籠153可以是接地面140的一部分例如利用貫孔142來互連接至支撐一導電的表面130的引線接合線131的一組合。在另一實施 方式中，在導電的表面130與引線接合線131的某些個的尖端148之間可以有一間隙144。以此種方式，導電的表面130的一底部，例如是一導電板的一底部例如可以附接至、或是安置在介電保護材料模製層143的一頂表面之上，因而介電保護材料模製層143的高度可以是大於引線接合線131的高度。
因此，一導電的表面130可被設置在引線接合線131的一部分之上，其中其之上方的末端或尖端148係和導電的表面130間隔開。然而，一種具有一間隙144的配置可能會提供一較不有效的法拉第籠153，因而為了例如且非限制性的清楚的目的起見，應假設是沒有間隙的。
耦接至接地面140而從封裝基板19的上表面132向上突出或延伸離開的引線接合線131可加以排列。以此種方式，即使引線接合線131的一種Bond Via ArrayTM或是BVA®配置136的單一列與行在一實施方式中可以存在，但是一種BVA配置136的多個列及/或多個行的引線接合線131可以沿著一屏蔽區域133的一或多個側邊而存在。
為了重述要點，引線接合線131中的某些例如是在界定一屏蔽區域133的BVA配置136中的引線接合線131可被設置，以提供此種避免EMI或相關EMI的屏蔽區域133給微電子裝置145。引線接合線131的其它位在屏蔽區域133之外的部分可能並未被使用於EMI屏蔽。再者，一或多個其它主動或被動微電子裝置11及/或12可以耦接至基板19，並且是位在屏蔽區域133之外，因而不是此種屏蔽區域的部分、或是被設置用於此種屏蔽區域。
圖5是描繪一範例的SiP 100的側視橫截面方塊圖，其係具 有一導電的覆蓋150，並且在導電的覆蓋150之下的一EMI屏蔽區域中具有信號引線接合線131s。圖5的SiP 100是與圖4的SiP 100相同的，但是具有以下的差異。
在此例子中，引線接合線131的一部分係具有一高度大於引線接合線131的另一部分的一高度。兩組的引線接合線131都可以接近微電子裝置145而且在微電子裝置145的周圍來加以設置。然而，引線接合線131的較高的部分可以是用於提供一相關EMI的屏蔽區域133給微電子裝置145。然而，引線接合線131的其它較矮的部分("引線接合線131s")可以是耦接微電子裝置145至封裝基板19的導體的信號線。此種較矮的引線接合線131s的某些個可以是在一法拉第籠153之內。較高的引線接合線131的高度可能會受限於低矮的封裝應用。
導電的覆蓋150可以耦接至封裝基板19的上表面132。導電的覆蓋150可以覆蓋SiP 100的耦接至上表面132的構件，其係包含微電子裝置145、微電子裝置11、12以及引線接合線131。並非BVA配置136的部分之引線接合線131可以將導電的覆蓋150以及接地面140互連。此耦接可被使用以降低內部的雜訊。然而，法拉第籠153可以是位在覆蓋150之下，以用於內部的EMI屏蔽。選配的是，導電的表面130可被省略，而有利於利用導電的覆蓋150作為法拉第籠153的一上方的導電的表面，而不論在尖端148與導電的覆蓋150的一底面之間具有或是不具有一間隙144。
某些在BVA配置136之內的引線接合線131可以是信號線，亦即引線接合線131s。引線接合線131s可以不耦接至接地面140，而是可以耦接至封裝基板19的線路(未顯示)。引線接合線131s的尖端可以在 介電保護材料模製層143的使用之前，先被接合或是焊接至微電子裝置145。在另一實施方式中，相關微電子裝置145的介電保護材料模製層143可被省略。
引線接合線131s可被接合到被動微電子裝置12或是主動微電子裝置11中的一或多個的上表面。這些引線接合線131s可以是用於在SiP 100之內的互連。
圖6是描繪一範例的SiP 100的側視橫截面方塊圖，其係具有利用一上方的基板169的EMI屏蔽。圖6的SiP 100係與圖5的SiP 100相同的，但是並不具有導電的覆蓋150，而且具有以下的差異。
上方的基板169可包含貫孔162以及一接地面160。引線接合線131的尖端或是上方的末端148可以沿著上方的基板169的一底表面，利用互連161(例如是利用微球體或微凸塊)來互連接至貫孔162，例如以用於耦接至接地面160。互連161可被設置在介電保護材料模製層143的一上表面168上。接地面160可以提供法拉第籠153的一上方的導電的表面130。
另一不論是主動或被動的微電子裝置165可以耦接至上方的基板169的一頂表面。微電子裝置165可以利用引線接合線15來耦接至基板169的貫孔或線路。然而，微球體或是微凸塊可以在另一實施方式中被使用。微電子裝置165可以耦接在法拉第籠153之外。
圖7是描繪在一法拉第籠153的一上方的導電的表面130的加入之前的一SiP 100的一範例的部分的俯視方塊圖。焊墊170可以接近微電子裝置145而且在微電子裝置145的周圍來加以設置，以用於將引線接合線131分別耦接至其，以用於提供法拉第籠153的屏蔽區域133。屏蔽區域 133可被界定在一BVA配置136之內。
焊墊170可以在介電保護材料模製層143的側邊周圍和彼此間隔開。在介電保護材料模製層143中的微電子裝置145可以是位在屏蔽區域133的一中央部分中。焊墊170的一墊至墊的間距171可以是等於或小於約250微米。焊墊170的間距171可以針對於和例如是EMI及/或RFI的干擾相關的頻率來加以選擇，以將微電子裝置145與EMI及/或RFI屏蔽開。再者，微電子裝置145可能是一干擾的輻射體，並且因而此種屏蔽可以是用以保護SiP 100的其它構件免於由微電子裝置145所產生的干擾。
即使單一列與行的焊墊170係說明性地被描繪，但是在另一實施方式中可以有超過一或兩個列及/或行。再者，焊墊170的列及/或行可以相關彼此來交錯的，以提供較稠密的屏蔽。引線接合線131可以有效地被用來提供一低通濾波器的法拉第籠，以用於降低相關微電子裝置145的操作的EMI。以此種方式，儘管並非必要的，但焊墊170的設置以及因此的引線接合線131的設置可以是一致的。引線接合線131可以針對於被調適以屏蔽前往微電子裝置145、或是來自微電子裝置145的一特定範圍的頻率之密度來加以置放及/或調整。
圖8是描繪在一法拉第籠153的一上方的導電的表面130的加入之前的另一SiP 100的一範例的部分的俯視方塊圖。在此例子中，引線接合線131的一BVA配置136的兩個列以及兩個行係被用來界定一屏蔽區域133。在此例子中，在列與行之間的間隔是交錯的，以提供一較稠密的引線接合線131的樣式。
在此例子中，BVA配置136的引線接合線131中的某些個 係用於載有信號，亦即引線接合線131s。以此種方式，互連180可被形成以用於從微電子裝置145延伸到介電保護材料模製層143之外，以用於與信號引線接合線131s的互連，該些信號引線接合線131s可包含一或多個信號線。
圖9A是描繪一具有EMI屏蔽的堆疊式封裝的("PoP")裝置190的一範例的部分的側視橫截面方塊圖。PoP裝置190可包含一上方的SiP 100U，其係堆疊在一下方的SiP 100L的頂端上。PoP裝置190例如可包含一或多個在一屏蔽區域之外的其它微電子裝置以及其它的細節，例如是先前參考圖3A至8所述者。於是，為了清楚且非限制性的目的起見，先前針對於SiP 100所敘述的細節並未在以下加以敘述。
一下方的SiP 100L的一下方的封裝基板19L可包含一下方的接地面140L，其係使得下方的引線接合線131L從下方的封裝基板19L的一上表面向上地延伸。此種下方的引線接合線131L及接地面140L可以例如是利用如先前所述的貫孔及球體接合來互連接至彼此，以用於形成一法拉第籠153的一下方的部分。下方的引線接合線131L的尖端148可以沿著上方的封裝基板19U的一下方側，利用互連191而被接合或耦接至針對其之墊及貫孔。
選配的是，上方的封裝基板19U可包含一上方的接地面140U，以用於形成一法拉第籠153來作為兩個法拉第籠的一堆疊，亦即一上方的法拉第籠192U以及一下方的法拉第籠192L。法拉第籠192U及192L的每一個都可包含分別耦接至封裝基板19U及19L的上表面之個別的封裝的微電子裝置145U及145L。
上方的基板19U的上方的接地面140U可以是位在一下方的微電子裝置145L之上，因而下方的引線接合線131L的尖端或上方的末端148可以沿著上方的封裝基板19U的一底表面，利用互連191來互連接至墊或接點以用於電耦接至上方的接地面140U。上方的引線接合線131U以及選配的接地面140U可以例如利用如先前所述的貫孔以及球體接合來互連接至彼此，以用於形成一法拉第籠153的一上方部分。上方的引線接合線131U的尖端148可被接合或是耦接至導電的表面130，以用於完成此種上方的法拉第籠192U。
在另一實施方式中，上方的基板封裝19U的貫孔可以在不連接至一上方的接地面140U之下，互連下方的引線接合線131L以及上方的引線接合線131U，以形成一用於兩個微電子裝置145U、145L的"兩個樓層的"或是兩層的法拉第籠153。即使只有兩層係說明性地被描繪，但是超過兩層亦可被使用在其它的實施方式中。
圖9B是描繪另一具有EMI屏蔽的PoP裝置190的一範例的部分的側視橫截面方塊圖。PoP裝置190例如可包含一或多個在一屏蔽區域之外的其它的微電子裝置以及其它細節，例如是先前參考圖3A至9A所述者。於是，為了清楚且非限制性的目的起見，先前針對於SiP 100所敘述的細節並未在以下加以敘述。
除了以下的差異之外，圖9B的PoP裝置190可以是與圖9A的PoP裝置190相同的。圖9B的PoP裝置190可包含信號引線接合線131s。信號引線接合線131s可以是位在法拉第籠153之內，其係包含在法拉第籠192U之內。
在此配置中的信號引線接合線131s可以從一下方的微電子裝置145L的一上表面向上地延伸。從下方的微電子裝置145L的一上表面延伸之引線接合線131s的尖端或上方的末端148可以例如是利用互連191而互連接至上方的封裝基板19U的一下面側。貫孔及/或線路(未顯示)可以利用信號引線接合線131s來電耦接上方及下方的微電子裝置145。再者，下方的基板封裝19L可包含用於與下方的微電子裝置145互連的貫孔及/或線路(未顯示)。
圖10是描繪另一SiP 100的一範例的部分的側視橫截面方塊圖。SiP 100例如可包含一或多個在一屏蔽區域之外的其它的微電子裝置以及其它細節，例如是先前參考圖3A至9B所述者。於是，為了清楚且非限制性的目的起見，先前針對於SiP 100所敘述的細節並未在以下加以敘述。
在此例子中，引線接合線131以及一例如是IC晶粒的微電子裝置145係被一介電保護材料模製層143所保護。微電子裝置145可以在沉積或是注入介電保護材料模製層143之前，利用微凸塊互連17來互連至封裝基板19的一上表面。同樣地，在沉積或是注入介電保護材料模製層143之前，引線接合線131可以被球體接合到封裝基板19的一上表面。
選配的是，信號引線接合線131s可以在沉積或是注入介電保護材料模製層143之前，被球體接合到微電子裝置145的一上表面201。信號引線接合線131s因此可以是在一法拉第籠153的一屏蔽區域133之內。
引線接合線131的尖端或上方的末端148以及選配的信號引線接合線131s可以延伸在介電保護材料模製層143的一上表面202之上。焊料球體或是其它的互連共晶體204可加以沉積到尖端148之上，以用於例 如是在此的別處所描述的後續的互連。
不具有干擾屏蔽的垂直的整合
圖11A是描繪一SiP 100的一範例的部分的側視橫截面方塊圖。圖11B是描繪另一SiP 100的一範例的部分的側視橫截面方塊圖。同時參考圖11A及11B，分別被說明性地描繪在那些圖中的SiP 100係進一步加以敘述。SiP 100的每一個都可以包含一或多個其它微電子裝置以及其它細節，例如是先前所敘述者。於是，為了清楚且非限制性的目的起見，先前針對於SiP 100所敘述的細節並未在以下加以敘述。
SiP 100的每一個係包含一垂直整合的微電子封裝200。微電子封裝200的每一個係包含一基板19，其係具有一上表面132以及一與該上表面相對的下表面149。封裝基板19可以具有位在表面132及149之間的一接地面140、以及互連接至此種接地面以用於導電的貫孔142。
一微電子裝置145可以耦接至基板19的上表面132，其中微電子裝置是一被動微電子裝置。以此種方式，在一SiP 100中，可以有被動或主動微電子裝置中的任一者或是兩者的一或多個耦接至上表面132。此表示有此種微電子裝置的上表面在過去對於垂直的整合而言可能已經變成是未使用的，但是現在則藉由使得如同在此所述地接合被附接至此種微電子裝置的此種上表面的引線接合線。
以此種方式，引線接合線131可以耦接至基板19的上表面132並且從該上表面132延伸離開，並且引線接合線231可以耦接至微電子裝置145的一上表面201並且從該上表面201延伸離開。引線接合線131及231分別可以利用用於導電的球體接合141來機械式地耦接至上表面132及 201。然而，在其它實施方式中，其它類型的接合亦可被使用。引線接合線231係在長度上比引線接合線131短的。
參考圖11A，引線接合線131可以具有一整體完成後的長度261，並且引線接合線231可以具有一整體完成後的長度262。然而，引線接合線131及231的完成後的高度可以是大致相同的。引線接合線131及231的尖端或是上方的末端148可以延伸在模製層143的一上表面202之上。
上方的末端148可以為了大致是共面的而為毗連的。焊料球體或是其它的互連共晶體204可以在上表面202上，而分別加以沉積在上方的末端148之上，以用於與在一主動或被動微電子裝置165的一正面的底面上的墊(未顯示)形成互連。
一被動微電子裝置145可以耦接至封裝基板19的上表面132。微電子裝置145可包含導電線路，並且可以只包含被動構件。一被動構件可包含一電容器、一電感器、或是一電阻器中的一或多個、或是其之任意組合。
如同先前所述的，微電子裝置145可以利用球體或凸塊互連及/或引線接合線來耦接至封裝基板19。再者，微電子裝置145可以利用一黏著劑或是一底膠填充層(未顯示)來耦接至上表面132。
在此實施方式中，微電子裝置145以及微電子裝置165可以具有面向下的朝向，亦即朝向基板19的上表面132之面朝下的朝向。然而，在另一實施方式中，微電子裝置165可以具有一向上背對基板19的一上表面132之正面的面。
一微電子裝置165可以被耦接在模製層143的最上面的表面 202之上。在一實施方式中，一微電子裝置165可以利用共晶體204或是其它機械式互連來耦接至引線接合線131及231之上方的末端148。微電子裝置165可以是位在微電子裝置145之上，並且至少部分地重疊此種微電子裝置145。
模製層143可以具有一最上面的表面202以及一與該最上面的表面相對的最下面的表面252。模製層143可被設置以用於圍繞引線接合線131及231兩者的長度261及262的部分。上方的末端148例如可以像是藉由用於一注入模製的一模製輔助膜的使用而不被模製層143所覆蓋。在另一實施方式中，模製層143可以暫時完全覆蓋長度261及262，接著是一回蝕以露出上方的末端148。
在一垂直整合的微電子封裝200的一實施方式中，微電子裝置145可被設置在模製層143中。以此種方式，在一實施方式中，微電子裝置145可以完全位在模製層143的最上面的表面202與最下面的表面252之間。引線接合線131可被設置在微電子裝置145的側壁203的周圍，儘管在此範例實施方式中並非是用於干擾的屏蔽。
引線接合線131可以耦接至接地面140，以用於從封裝基板19的上表面132向上地突出或延伸，並且可加以排列。以此種方式，儘管引線接合線131及/或231的一BVA®配置的單一列與行在一實施方式中可以存在，但是多個列及/或多個行的此種引線接合線亦可以是在一BVA®配置中。
在垂直整合的微電子封裝200的一實施方式中，本身是一被動微電子裝置的微電子裝置165可被使用。然而，在垂直整合的微電子封 裝200的另一實施方式中，本身是一主動微電子裝置的微電子裝置165可被使用。
參考圖11B，內部的引線接合線131i可以具有一整體完成後的長度263，並且引線接合線231可以具有一整體完成後的長度264。如同先前參考圖11A所述的，外部的引線接合線131o可以具有一整體完成後的高度261。引線接合線131i及231在形成之後的完成後的高度可以是大致相同的。引線接合線131i及231的上方的末端148可以是大致與彼此為高低相同的。
引線接合線131i及231的上方的末端148可以是為了大致是共面的而為毗連的。焊料球體或是其它的互連共晶體274分別可以將一主動或被動微電子裝置271的一下表面耦接至引線接合線131i及231的上方的末端148，以用於與在一主動或被動微電子裝置271的一正面的底面上的墊(未顯示)形成互連。在微電子裝置271處於適當的地方下，一模製材料可被注入以形成模製材料層143，並且因此微電子裝置271的一下表面可以接觸到模製層143的模製材料。為了模製，一模製輔助膜可被用來容許外部的引線接合線131o的尖端148、以及微電子裝置271的墊或是其它互連(未顯示)，能夠延伸在模製層143的上表面202之上。在另一實施方式中，模製層143可以暫時完全地覆蓋長度261，接著是一回蝕以露出其之上方的末端148。
微電子裝置271可以耦接至微電子裝置145而且位在微電子裝置145之上，並且可以至少部分地重疊微電子裝置145。以此種方式，微電子裝置271可以橫向地延伸在微電子裝置145的一周邊之外，以用於內部 的引線接合線131i在基板19的上表面132與微電子裝置271的一面對此種上表面132的下表面之間的互連。引線接合線131i以及引線接合線131o可被設置在微電子裝置145的側壁203的周圍，儘管在此範例實施方式中並非用於干擾的屏蔽。
同樣地，一被動微電子裝置145可以耦接至封裝基板19的上表面132。微電子裝置145可包含導電線路，並且可以只包含主動構件、只包含被動構件、或是其之一組合。一被動構件可包含一電容器、一電感器、或是一電阻器、或是其之任意組合。如先前所述，微電子裝置145可以利用球體或是凸塊互連及/或引線接合線來耦接至封裝基板19。再者，微電子裝置145可以利用一黏著劑或是一底膠填充層(未顯示)來耦接至上表面132。
模製層143可以具有一最上面的表面202以及一與該最上面的表面相對的最下面的表面252。模製層143可被設置以用於圍繞引線接合線131o的長度261的部分，並且用於圍繞引線接合線131i及231兩者的長度263及264。
在垂直整合的微電子封裝200的一實施方式中，微電子裝置145可被設置在模製層143中，並且完全位在模製層143的最上面的表面202與最下面的表面252之間。微電子裝置271可被設置在模製層143中，並且至少部分地位在模製層143的最上面的表面202與最下面的表面252之間。微電子裝置165可以被耦接在模製層143的最上面的表面202之上。
對於一被動微電子裝置271而言，微電子裝置271可包含導電線路，並且可以只包含被動構件。微電子裝置271可包含一RDL。一被 動構件可以是一電容器、一電感器、或是一電阻器、或是其之任意組合。在此實施方式中，微電子裝置145及271、以及微電子裝置165係具有面向下的朝向，亦即朝向基板19的上表面132之面朝下的朝向。然而，在另一實施方式中，微電子裝置165及/或微電子裝置271可以具有從基板19的一上表面132面向上的一正面的側面。
在垂直整合的微電子封裝200的一實施方式中，本身是一被動微電子裝置的微電子裝置165可被使用。然而，在垂直整合的微電子封裝200的另一實施方式中，本身是一主動微電子裝置的微電子裝置165可被使用。一微電子裝置165可以耦接在模製層143的最上面的表面202之上，以用於與微電子裝置271的互連。在一實施方式中，一微電子裝置165可以利用用於導電的共晶體204或是其它的機械式互連來耦接至微電子裝置271的一上表面。
微電子裝置165可以是位在微電子裝置271之上，並且至少部分地重疊此種微電子裝置271。以此種方式，一微電子裝置165可以耦接在模製層143的最上面的表面202之上，以用於與外部的引線接合線131o的上方的末端148的互連、以及與微電子裝置271的一上表面的互連。
引線接合線131i及131o可以耦接至接地面140，以用於從封裝基板19的上表面132向上地突出或延伸，並且可加以排列。以此種方式，即使引線接合線131i、131o及/或231的一BVA®配置的單一列與行在一實施方式中可以存在，但是多個列及/或多個行的此種引線接合線可以是在一BVA®配置中。
圖12A是描繪另一SiP 100的一範例的部分的側視橫截面方 塊圖。除了以下的細節之外，圖12A的SiP 100可以是與在圖11A中的相同。在一垂直整合的微電子封裝200的此實施方式中，微電子裝置165可以懸臂伸出，以用於橫向地延伸超過一引線接合線131並且在其之上。以此種方式，引線接合線131的上方的末端148可以利用共晶體204來互連至一微電子裝置165的一下表面。
圖12B是描繪另一SiP 100的一範例的部分的側視橫截面方塊圖。除了以下的細節之外，圖12B的SiP 100可以是與在圖11B中的相同。在一垂直整合的微電子封裝200的此實施方式中，微電子裝置165並未懸臂伸出以用於橫向地延伸超過一引線接合線131i並且在其之上。以此種方式，一微電子裝置165以及微電子裝置271對於其分別的下表面以及上表面可以具有大致相等的表面積。
圖12C是描繪另一具有或是不具有整合的引線接合線EMI屏蔽之SiP 100的一範例的部分的側視橫截面方塊圖。除了以下的細節之外，圖12C的SiP 100可以是與在圖12A中的相同。在一垂直整合的微電子封裝200的此實施方式中，微電子裝置165係懸臂伸出以用於在該圖中的微電子裝置145的一右側以及一左側上橫向地延伸超過引線接合線131並且在其之上。以此種方式，引線接合線131的上方的末端148可以利用共晶體204來互連至一微電子裝置165的一下表面。於是，應該體認到的是，被設置在一微電子裝置的周圍並且互連接至一微電子裝置165的引線接合線131可被使用於扇出。
圖12D是描繪另一具有或是不具有整合的引線接合線EMI屏蔽之SiP 100的一範例的部分的側視橫截面方塊圖。除了以下的細節之 外，圖12D的SiP 100可以是與在圖12B中的相同。在一垂直整合的微電子封裝200的此實施方式中，微電子裝置165係並未懸臂伸出以用於橫向地延伸超過一引線接合線131o並且在其之上。以此種方式，微電子裝置165以及微電子裝置271對於其分別的下表面以及上表面可以具有大致相等的表面積。以此種方式，引線接合線131i的上方的末端148可以利用共晶體274來互連至一微電子裝置271的一下表面。於是，應該體認到的是，被設置在一微電子裝置145的周圍並且互連接至一微電子裝置271的引線接合線131i可被使用於扇出。
圖13A是描繪一具有一垂直整合的微電子封裝200之範例的SiP 100的側視橫截面方塊圖。在此實施方式中，一垂直整合的微電子封裝200可以是一耦接至基板19的獨立的封裝，即如同在圖12D中的一SiP 100。由於SiP 100的構件先前已經例如是參考圖4來加以敘述，因而此種說明並未予以重複。
在此實施方式中，例如是焊料球的共晶體274係被形成在模製層143的一上表面202上、在一重分佈層上、或是在該些引線接合線131i及231的尖端上。共晶體274係將引線接合線131i及231的上方的末端148互連至微電子裝置271的一下表面。在另一實施方式中，共晶體274可被封入在模製層143中。在此例子中，微電子裝置271的一下表面並未接觸到模製層143的一上表面202。
再者，在此範例實施方式中，除了其之接觸末端之外，信號引線接合線131s可被封入在模製層143的模製材料中。信號引線接合線131s可以是短於內部的引線接合線131i，並且可以是如先前所述的用於與一微 電子裝置145的互連。以此種方式，微電子裝置271可以耦接至例如是引線接合線131i之被耦接到上表面132的引線接合線131的一較高的部分的上方的末端148。微電子裝置271可以進一步耦接至引線接合線231的上方的末端148。例如是先前所敘述的，引線接合線131的另一耦接至上表面132的部分(例如是信號引線接合線131s)可以使得其之上方的末端148耦接至微電子裝置145的一上表面。
選配的是，引線接合線331可以耦接至主動微電子裝置11及/或被動微電子裝置12的一或多個上表面，而微電子裝置11及/或12係直接被耦接到基板19的一上表面132。
有關圖13A的SiP 100的其它細節先前已經加以敘述，並且因此為了清楚且非限制性的目的起見而未予以重複。
圖13B是描繪一具有一垂直整合的微電子封裝200之範例的SiP 100的側視橫截面方塊圖。在此實施方式中，如同在圖13A中的一SiP 100，一垂直整合的微電子封裝200可以是一耦接至基板19之獨立的封裝。由於SiP 100的構件先前已經例如參考圖4來加以敘述，因而此種說明並不予以重複。
除了以下的差異之外，圖13B的SiP 100係類似於圖13A的SiP 100。在圖13B的SiP 100中，垂直整合的微電子封裝200係省略微電子裝置271。因此，例如是先前敘述的，一微電子裝置165可以利用共晶體204來直接耦接至模製層143的一上表面202。
圖13C是描繪又一具有一垂直整合的微電子封裝200的範例的SiP 100的側視橫截面方塊圖。在此實施方式中，如同在圖13A中的一SiP 100，一垂直整合的微電子封裝200可以是一耦接至基板19的獨立的封裝。由於SiP 100的構件先前已經例如參考圖4來加以敘述，因而此種說明並不予以重複。
除了以下的差異之外，圖13C的SiP 100係類似於圖13A的SiP 100。在圖13C的SiP 100中，垂直整合的微電子封裝200係具有某些如先前所述的被封入在模製層143的模製材料中的引線接合線131i，並且具有某些並未被封入在模製層143的模製材料中的引線接合線131i。
圖13D是描繪又一具有一垂直整合的微電子封裝200之範例的SiP 100的側視橫截面方塊圖。在此實施方式中，如同在圖13B中的一SiP 100，一垂直整合的微電子封裝200可以是一耦接至基板19的獨立的封裝。由於SiP 100的構件先前已經例如參考圖4來加以敘述，因而此種說明並不予以重複。
除了以下的差異之外，圖13D的SiP 100係類似於圖13B的SiP 100。在圖13D的SiP 100中，垂直整合的微電子封裝200並不具有被封入在模製層143的模製材料中的引線接合線131。
圖14A是描繪又一具有一垂直整合的微電子封裝200之範例的SiP 100的側視橫截面方塊圖。由於圖14A的SiP 100係類似於先前在此所述的SiP 100，因此為了清楚的目的起見，大致只有差異才在以下用額外的細節來加以描述。
在此範例實施方式中，一電路平台400可以是一例如為封裝基板19的封裝基板、一晶粒基板或中介體、一導線架、或是一例如為RDL的繞線層。在此例子中，一被動微電子裝置271係大致被表示為一電路平 台401，其可以是一繞線層、一晶粒基板或中介體、或是一封裝基板。垂直的引線接合線131i可以互連電路平台400的一上表面405至電路平台401的一下表面403。在此例子中，微電子裝置145是一只有引線接合的裝置，其係在此種面對的表面之間利用一環氧樹脂或是其它黏著層402，而使得其之一下表面406耦接至電路平台401的一上表面405。
微電子裝置145可以是處於一面朝上的朝向。引線接合線131s可以將電路平台401的一上表面405互連至微電子裝置145的一上表面407。較短的垂直的引線接合線231可以互連微電子裝置145的一上表面407與電路平台401的一下表面403。
介電保護材料模製層143可以是一模製層或是一圍堰填充的層，並且儘管只有展示覆蓋該SIP的一部分，但是可以替代地覆蓋在該SIP 100中的構件的任一個或是全部。微電子裝置145可以利用黏著層402來耦接至電路平台400，接著是將引線接合線131s及231引線接合。在加上一模製或圍堰填充的層的介電保護材料模製層143之前，引線接合線231及131i可以耦接至電路平台401的一下表面403。相較於只使得引線接合線131i及231支撐電路平台401，介電保護材料可以提供一更剛性的結構，因為一下表面403以及一側壁表面404的至少部分可被覆蓋此種介電保護材料模製層143。
圖14B是描繪又一具有一垂直整合的微電子封裝200的範例的SiP 100的側視橫截面方塊圖。由於圖14B的SiP 100係類似於圖14A的SiP 100，因此大致只有差異才在以下用額外的細節來加以描述。
除了在微電子裝置145的一上表面407上的引線接合線231 之外，另一微電子裝置410可以在此種面對的表面之間利用另一環氧樹脂或是其它黏著層402，而使得其之一下表面耦接至微電子裝置145的一上表面。另一組利用垂直的引線接合線432所提供的互連可以耦接在微電子裝置410的一上表面以及電路平台401的一下表面403之間，以用於在微電子裝置410以及電路平台401之間的電性通訊。微電子裝置145及410可以組合地形成一晶粒堆疊，其中此種裝置兩者都處於一面朝上的朝向以用於引線接合至其之上表面。
再者，除了具有引線接合線231以及微電子裝置410在微電子裝置145的上表面407上的一開始的設置之外，另一組引線接合線431可以耦接至上表面407，以用於與微電子裝置410的一上表面408互連。引線接合線431可以向上彎弧以用於耦接至上表面408。這些引線接合線431因此可以將微電子裝置145及410的上方的面彼此互連。微電子裝置145及410可以是主動裝置、被動裝置、或是主動及被動裝置的一組合。
同時參考到圖14A及14B，耦接至電路平台401的可以是一表面安裝技術("SMT")的構件(其可以是一主動或被動SMT微電子裝置165)、以及一引線接合安裝的構件(例如是一主動或被動引線接合微電子裝置411)的任一或是兩者。一主動或被動SMT微電子裝置165可以面向下地被安裝至電路平台401的一上表面441，並且一主動或被動引線接合微電子裝置411可以面向上地被安裝至電路平台401的上表面441。
圖14C是描繪又一具有一垂直整合的微電子封裝200之範例的SiP 100的側視橫截面方塊圖。由於圖14C的SiP 100係類似於圖14A及14B的SiP 100，因此大致只有差異才在以下用額外的細節來加以描述。
在此範例實施方式中，一中介體或是其它電路平台414的一下表面係利用微凸塊或是其它小形狀因數的互連413來互連接至在一面朝上的微電子裝置145的一上表面上的接點。中介體414的一上表面係利用微凸塊或是其它小形狀因數的互連415來互連接至在一面朝下的微電子裝置416的一下表面上的接點。引線接合線131s的遠端可以耦接至中介體414的一上表面，以用於互連至電路平台400的一上表面405。引線接合線231的近端或是下方的末端可以耦接至中介體414的一上表面，其中此種引線接合線的遠端或是上方的末端係耦接至電路平台401的下表面403。藉由利用一中介體414以及覆晶或類似的微電子裝置416，更多用於引線接合線231及/或131s的區域、以及在微電子裝置145及416之間更多的互連線可加以設置。
圖14D是圖14C的方塊圖，儘管是利用一具有一保護介電材料的模製層143來覆蓋電路平台400。此保護介電材料的模製層143係在電路平台400的一上表面405之上提供互連表面418。引線接合線131及331可以使得其之尖端或是上方的末端延伸在表面418之上，以用於一或多個被動或主動電路的互連。
這些是用於一SiP 100的一垂直整合的微電子封裝200的各種實施方式中某些個。這些或其它實施方式可以根據在此的說明來加以提供。然而，以上具有混合SMT及引線接合裝置的實施方式已經加以敘述。如同在以下用額外的細節所敘述的，其之表面或是至少部分可被保留來用於任一只有SMT或是只有引線接合的裝置。
具有分開的安裝表面類型之垂直的整合
有關耦接包含但不限於在一耦接至一電路板的多晶粒的封裝中的一或多個VLSI晶粒的微電子裝置的例如是線路及貫孔的長距離的繞線可能會導致相當大的電流-電阻的下降("IR下降")或是電壓下降。以此種方式，VLSI晶粒傳統上已經被設計成其中焊墊或是其它的引線接合接點是在此種晶粒或封裝的一周邊處、或是在周邊的附近，以用於引線接合的互連。再者，隨著VLSI晶粒以及多晶粒的封裝變成更大的，至主動區域的距離或是至構件的距離係分別變成更長的，並且這些更長的距離可能會導致相應更大的IR下降。有關VLSI晶粒以及多晶粒的封裝，在繞線的長度上的差異以及在繞線上的寄生效應上的差異可能會造成在傳輸於其上的信號上的差異或是變化。有關積體電路晶粒，這些晶片上的差異可被稱為晶片上的變化("OCV")。此種差異可能會影響電壓位準、時序(亦即，信號傳遞延遲)、及/或信號的相互作用、以及其它參數。在某些實例中，一VLSI晶粒或是一多晶粒的封裝可能會變慢且/或汲取額外的功率來考量此種OCV或是IR下降。
在記住以上的背景下，例如是用於VLSI晶粒及/或SiP的繞線距離係進一步加以敘述。為了降低IR下降的影響，如同已知的，電容可以加入以調整一電阻-電容("RC")時序延遲。然而，電容器可能是大的而且並不容易整合到一VLSI製程中，並且因此外部的電容器可以耦接至一VLSI晶粒。SiP應用可包含但不限於一或多個引線接合至一平台的VLSI晶粒、以及一或多個耦接至同一平台的SMT構件。SiP可被用在RF以及其它應用中，其可能包含表面安裝構件，例如是振盪器、電容器、耦接器、及/或雙工器、以及其它構件。
在一SiP中，引線接合構件以及表面安裝構件可以一起被安裝在同一安裝表面上。以此種方式，表面安裝構件可以耦接至一例如是中介體或導線架的封裝基板、或是一例如為RDL的繞線層，其中在此種表面安裝構件之間的間隙係用於引線接合構件的後續安裝至此種封裝基板或繞線層。這些間隙可能是足夠寬的，以避免使得焊料助焊劑及/或焊料、或是其它和一共晶耦接相關的材料污染引線接合墊或是引線接合的接點。此間隔係因為增加在構件之間的距離而實際上增加IR下降。
如同在以下用額外的細節敘述的，一SiP或是其它多微電子裝置的封裝可以具有一電路平台，其係具有一只有引線接合的表面、或是具有一用於兩個或多個只有引線接合的構件的部分，而在此種兩個或多個只有引線接合的構件之間並無任何表面安裝技術("SMT")構件。一模製或是圍堰填充的層可以被加在此種具有例如是一或多個VLSI晶粒的引線接合的構件的電路平台之上，以提供一只有表面安裝的區域，亦即一只有表面安裝技術的("只有SMT的")表面區域("只有SMT的區域")，其係至少部分地對應於此種只有引線接合的表面區域或是表面區域部分("只有引線接合的區域")。
圖15A是描繪一範例的SiP 100的側視橫截面方塊圖。SiP 100是一垂直整合的微電子封裝，其係包含一具有一上表面405以及一相對其之此種上表面的下表面505的電路平台400。球體或是其它互連501可以耦接至下表面505。一或多個積體電路晶粒或是其它微電子裝置502及/或503可以耦接至上表面405。在此例子中，積體電路晶粒502係利用微凸塊413來耦接至上表面405。在此例子中，積體電路晶粒503係利用一黏著層 402來耦接至上表面405。再者，在此例子中，積體電路晶粒502及503是主動構件，但是在另一實施方式中，此種積體電路晶粒502及/或503中的一或多個可以是被動構件。
上表面405的區域的一部分508可以是一用於一或多個積體電路晶粒503的耦接之只有引線接合的區域，並且上表面405的區域的另一部分509可以是一用於一或多個積體電路晶粒502的耦接之只有SMT的區域。為了避開一只有SMT的區域的助焊劑或是其它污染與和引線接合相關的污染物，區域508及509可以是和彼此間隔開一間隙區域507。
處於一面朝下的朝向的SMT積體電路晶粒502可以在只有SMT的區域509中加以耦接，並且處於一面朝上的朝向之引線接合的積體電路晶粒503可以在只有引線接合的區域508中加以耦接。引線接合線131可以耦接至上表面405的只有引線接合的區域508並且從該區域508延伸離開，以用於互連至一被動微電子裝置512。引線接合線131可以是在一對應的積體電路晶粒503的一周邊之外。
引線接合線231可以耦接至微電子裝置503的一上表面407並且從該上表面407延伸離開，以用於互連至一被動微電子裝置512，其中引線接合線231可以是短於引線接合線131。引線接合線231可以是在一對應的積體電路晶粒503的一周邊之內。被動微電子裝置512可以是位在上表面407之上，並且至少部分地重疊上表面407。
微電子裝置512可以耦接至引線接合線131及231的上方的末端。引線接合線531可以在只有引線接合的區域508中耦接至上表面405以及耦接至上表面407。引線接合線509可以在只有引線接合的區域508中 耦接至相鄰的積體電路晶粒503的上表面407。以此種方式，一或多個被動微電子裝置512可以是在只有引線接合的區域508之上，而且在只有引線接合的區域508之內。在只有引線接合的區域508之內的相鄰的積體電路晶粒503可以使得例如是引線接合線531及131的引線接合線耦接至在此種積體電路晶粒503的側壁/周邊之間的上表面405，而在此種積體電路晶粒503之間的此種空間中並無任何SMT裝置。
一模製層143可被設置在電路平台400以及一或多個微電子裝置502及503之上。模製層143可被設置以用於圍繞至少引線接合線131及231的長度的部分，並且用於覆蓋引線接合線509及531。以此種方式，引線接合線131及231的上方的末端可以延伸在模製層143的一上表面202之上。模製層143可以具有一接觸上表面405的下表面252，並且可以具有一相對此種下表面252的上表面202。上表面202可以是一只有SMT的表面、或是使得其之一部分是只有SMT的，例如是只有SMT的部分或區域510。只有SMT的區域510可以是與只有引線接合的區域508相對的，並且可以對應於只有引線接合的區域508。
一或多個處於一面朝下的朝向的被動微電子裝置512可被設置在上表面202上，以用於將其之接點耦接至引線接合線131及231的上方的末端。此SMT耦接可以藉由一熱超音波接合或是回焊焊接的操作來加以執行。
為了重述要點，一或多個積體電路晶粒502及/或503可被設置在模製層143中，因此完全地位在上表面202及405之間。然而，一或多個微電子裝置512可以在一只有SMT的區域510中耦接在上表面202之 上，該只有SMT的區域510可以對應於一只有引線接合的區域508。
相較於產生過長的距離之穿過一電路板的例如是線路及貫孔的繞線，藉由引線接合線131及231的使用而相當接近一積體電路晶粒503來設置一或多個微電子裝置512，可以獲得在IR下降上的顯著的降低。再者，因為在繞線的長度上的差異、以及在繞線上的寄生效應上的差異可能會造成在傳輸於其上的信號上的差異或是變化，所以藉由具有行進較短的距離，這些差異可以藉由引線接合線131及231的使用而被降低。
為了降低IR下降的影響，如同已知的，電容可以加入以調整一RC時序延遲。然而，電容器可能是大的而且不容易整合到一VLSI製程中，並且因此外部的電容器可以耦接至一VLSI晶粒。因此，藉由擁有一種能力來具有顯著大於那些在一VLSI晶粒中的電容之電容器，RC時序延遲可以更容易地加以解決。再者，此種額外的電容可以被加入到一VLSI晶粒的一中央區域，其中來自在此種VLSI晶粒的一周邊附近的焊墊之信號的RC延遲可能會花一段相當長的時間量來到達此種VLSI晶粒的一中央內部區域。SiP 100可被用在RF以及其它應用中，其可包含耦接至表面202的表面安裝構件，例如是振盪器、電容器、耦接器、及/或雙工器、以及其它被動SMT構件512。
在一SiP 100中，引線接合構件以及表面安裝構件可以在分開的安裝表面上被安裝在一起。以此種方式，引線接合構件可以耦接至一例如是中介體或導線架的封裝基板、或是一例如為RDL的繞線層，相較於在此種只有引線接合的區域508之外的一區域中被安裝至此種封裝基板或繞線層的SMT及引線接合構件的混合，其在只有引線接合的區域508中的 此種引線接合構件之間具有較窄的間隙。在一只有引線接合的區域508中的構件之間的間隙可以是足夠寬的，以避免使得焊料助焊劑及/或焊料、或是其它和一共晶耦接相關的材料污染相鄰的引線接合墊，但是此種間隙可以是遠窄於在此種混合中具有SMT構件的間隙。此只有引線接合的間隔係藉由減小在構件之間的距離，亦即藉由有效地將例如一被動微電子裝置512重新安置到上表面202，而不是將此種構件安裝在下表面252上，來有效地減小IR下降。
如上用額外的細節所述的，一SiP 100或是其它多個微電子裝置的封裝100可以具有一電路平台400，該電路平台400係具有一只有引線接合的表面508、或是具有一用於只有引線接合的構件的表面部分508，而在此種只有引線接合的構件之間無任何SMT構件。一模製或圍堰填充的層143可以被加入到此種電路平台以及例如是一或多個VLSI晶粒的引線接合的構件之上，以提供一對應於此種只有引線接合的表面或表面部分508的只有SMT的表面區域202。
因為用於一被動微電子裝置512的一外部的電容器可被使用於一積體電路晶粒503，所以此種被動微電子裝置可以是幾個數量級大於積體電路晶粒503的一內部的電容器。以此種方式，被動微電子裝置512可以具有一0.1或更大的微法拉的電容。除了此種較大的電容之外，一積體電路晶粒503可以利用此種緊鄰附近的外部的被動微電子裝置512來獲得一較大的響應頻率。以此種方式，一用於一被動微電子裝置512的電容器可以針對於一個1或更高GHz的頻率響應來耦接至一積體電路晶粒503。應該體認到的是，電容及電感是"競爭的"力量。然而，相較於具有耦接至一 PCB的一外部的電容器，藉由具有用於引線接合線131及231的短的線，自感可被降低，此係容許有此種頻率響應。以此種方式，引線接合線131可以具有大約一毫微亨利(nanohenry)或更小的自感，並且當然越短的引線接合線231可以具有比越長的引線接合線131更小的自感。
即使一被動微電子裝置512係被描述，但是如同在以下用額外的細節所敘述的，一主動微電子裝置511可以耦接至一上表面202。圖15B是描繪另一範例的SiP 100的側視橫截面方塊圖。SiP 100是一包含一電路平台400的垂直整合的微電子封裝，該電路平台400係具有一上表面405以及一與其之此種上表面相對的下表面505。球體或是其它互連501可以耦接至下表面505。
一或多個積體電路晶粒或是其它微電子裝置503可以耦接至上表面405。在此例子中，積體電路晶粒503係利用一黏著層402來耦接至上表面405。再者，在此例子中，積體電路晶粒503是主動構件，但是在另一實施方式中，此種積體電路晶粒503中的一或多個可以是被動構件。
上表面405的區域的至少一部分可以是用於一或多個積體電路晶粒503的耦接之一只有引線接合的區域508。以此種方式，在一實施方式中，上表面405可以是一只有引線接合的表面，而其並沒有用於任何積體電路晶粒502的SMT耦接之部分。因此，為了一具有例如是積體電路晶粒503的只有引線接合的構件之更密集封裝的表面，由間隙區域507所提供的間隙可加以避免，因為避開一只有SMT的區域的助焊劑或其它污染與和引線接合相關的污染物可以是藉由具有一只有引線接合的上表面405來加以提供。
引線接合的積體電路晶粒503可以在只有引線接合的區域508中處於一面朝上的朝向來加以耦接，並且其它引線接合的積體電路晶粒503-1可以利用黏著層402-1來耦接在對應的引線接合的積體電路晶粒503的上表面407上。引線接合的積體電路晶粒503-1可以處於一面朝上的朝向來加以耦接，以用於耦接在積體電路晶粒503及503-1的上表面407之間的引線接合線531-1。引線接合的積體電路晶粒503-1可以處於一面朝上的朝向來加以耦接，以用於耦接在上表面252與積體電路晶粒503-1的上表面407之間的引線接合線531-2。引線接合線531-1及/或531-2的一部分可以延伸在一上表面202之上。
引線接合線131可以耦接至上表面405的只有引線接合的區域508，並且從該只有引線接合的區域508延伸離開，以用於互連至一被動微電子裝置512或是一主動微電子裝置511。引線接合線131可以是在一對應的積體電路晶粒503的一周邊之外。
引線接合線231可以耦接至一微電子裝置503的上表面407並且從該上表面407延伸離開，以用於互連至一被動微電子裝置512，其中引線接合線231可以是短於引線接合線131。引線接合線231-1可以耦接至微電子裝置503-1的上表面407並且從該上表面407延伸離開，以用於互連至一被動微電子裝置412，其中引線接合線231-1可以是短於引線接合線231。引線接合線231-1可以是在一對應的積體電路晶粒503-1的一周邊內。被動微電子裝置412可以是位在微電子裝置503及503-1兩者的上表面407之上，並且至少部分地重疊該些上表面407。
微電子裝置512可以耦接至引線接合線131及231的上方的 末端，並且微電子裝置412可以耦接至引線接合線231-1的上方的末端。引線接合線531可以在只有引線接合的區域508中耦接至上表面405而且耦接至積體電路晶粒503的上表面407，並且引線接合線531-1可以在只有引線接合的區域508中耦接至一積體電路晶粒503的上表面407而且耦接至一晶粒堆疊的只有引線接合的積體電路晶粒503及503-1中的一積體電路晶粒503-1的上表面407。引線接合線509可以耦接至在只有引線接合的區域508中的相鄰的積體電路晶粒503的上表面407。以此種方式，一或多個被動微電子裝置512可以是在只有引線接合的區域508之上，而且在只有引線接合的區域508之內。在只有引線接合的區域508之內的相鄰的積體電路晶粒503可以具有被引線接合到在此種積體電路晶粒503的側壁/周邊之間的上表面405的引線接合線，例如是引線接合線131、531以及531-2，而在只有引線接合的區域508之內的此種積體電路晶粒503之間的此種空間中並無任何SMT裝置。
一模製層143可被設置在電路平台400以及一或多個微電子裝置503及503-1之上。模製層143可被設置以用於圍繞引線接合線131、231及231-1的長度的至少部分，並且用於覆蓋引線接合線509及531、以及引線接合線532-1及/或531-2的全部或是至少部分。以此種方式，引線接合線131、231及231-1的上方的末端可以延伸到模製層143的一上表面202之上。模製層143可以具有一接觸上表面405的下表面252，並且可以具有一相對此種下表面252的上表面202。上表面202可以是一只有SMT的表面、或是使得其之一部分是只有SMT的，例如是只有SMT的部分或區域510。只有SMT的區域510可以是與只有引線接合的區域508相對的，並且 可以對應於只有引線接合的區域508。
一或多個處於一面朝下的朝向的主動或被動微電子裝置511、512及/或412可被設置在上表面202上，以用於將其之接點耦接至引線接合線131、231及231-1的上方的末端。此耦接可以藉由一熱超音波或是回焊操作來加以執行。主動或被動微電子裝置511、512及/或512-1中的一或多個可以是一整合的被動裝置("IPD")，例如是用以提供一陣列的電阻器、電容器、耦接器、雙工器、或類似者以作為SMT被動裝置。此種封裝的裝置可以藉由焊料印刷("回焊")來加以耦接，其中所有此種封裝的裝置先前都已經在一比和回焊相關者為較少污染物的環境的無塵室中加以封裝。
在另一實施方式中，引線接合線531-1及531-2可以完全地被模製層143所覆蓋。應瞭解的是，藉由具有一只有SMT的表面202，SMT構件則不需要曝露到和引線接合佈線相關的加熱。在此例子中，被動微電子裝置412可以是位在積體電路晶粒503-1的中心；然而，在另一實施方式中，此種互連線可以從一積體電路晶粒的一中央位置加以偏置。
藉由分開SMT表面以及引線接合表面，一封裝或模組的平面的面積可以縮減。於是，對於平面的面積為有限的應用而言，如同在此所述的此種封裝或模組可加以利用。此外，相較於透過一PCB的繞線，此種模組或封裝可以使得一外部的電容器較接近一積體電路晶粒。再者，相較於晶片內部的電容及電阻，具有較大的電容器、較大的電阻器、或是其它外部的被動構件係表示在一晶片中可以使用較少的電容器以及較少的電阻器。同樣地，相較於透過一PCB來耦接至一積體電路晶粒的外部的電容器，一較低的IR下降以及一較低的自感可加以獲得。再者，和透過一PCB 的繞線相關的寄生值同樣可以藉由利用內嵌的引線接合線，例如是引線接合線131、231及231-1來加以避免。再者，對於一RF應用而言，在補償上的較小不匹配(例如是帶隙及/或濾波器不匹配)可以藉由具有利用內嵌的引線接合線的較短的距離來加以獲得。
圖15C是描繪又一範例的SiP 100的側視橫截面方塊圖。由於圖15C的SiP 100係類似於圖15B的SiP 100，因此為了清楚且非限制性的目的起見，大致只有差異才在以下用額外的細節來加以描述。在圖15C的範例實施方式中，一佔用一大的平面區域的VLSI晶粒503係說明性地被描繪。以此種方式，在此種VLSI晶粒503的上表面407上的焊墊541可被設置在其之一周邊附近，以用於與引線接合線531及/或509互連。在某些實施方式中，此種焊墊541可以從此種VLSI晶粒503的位在其中心的主動區域移開。因此，一外部的電容器透過位在周邊的焊墊541的耦接可以減小此種電容相關此種位在中心的主動區域電晶體及/或其它構件的影響。然而，藉由使得位在中心的焊墊541經由引線接合線231來互連接至一被動微電子裝置512，此種繞線的傳遞延遲以及對於週邊焊墊的寄生的影響可加以避免。
圖15D是描繪又一範例的SiP 100的側視橫截面方塊圖。由於圖15D的SiP 100係類似於圖15C的SiP 100，因此為了清楚且非限制性的目的起見，大致只有差異才在以下用額外的細節來加以描述。在圖15D的範例實施方式中，一甚至佔用一更大的平面區域的VLSI晶粒503係說明性地被描繪。在此例子中，在此種VLSI晶粒503的上表面407上的被設置在其之一周邊附近以用於與引線接合線531及/或509互連的焊墊541甚至可 以進一步從主動區域被移開。在此例子中，超過一個被動微電子裝置512係經由引線接合線231來耦接至位在中心的焊墊541，以降低繞線至其之週邊焊墊的IR下降、傳遞延遲及/或寄生的影響。
圖16A及16B是描繪範例的SiP 100的個別的側視橫截面方塊圖。由於圖16A及16B的SiP 100係類似於圖15B至15C的SiP 100，因此為了清楚的目的起見，大致只有差異才在以下用額外的細節來加以描述。在圖16A的範例實施方式中，電路平台400係被薄化以用於一低矮的應用。在圖16B的範例實施方式中，一可拆卸的電路平台400係被移除以用於一直接附接的應用，例如是附接至一導線架或是下一層級的組件或晶粒。
圖17A至17C是描繪範例的倒置的SiP 100的個別的側視橫截面方塊圖。由於圖17A至17C的SiP 100係相同或類似於先前在此所述的SiP 100，因此為了清楚且非限制性的目的起見，大致只有差異才被描述。
參考圖17A，球體501可以從電路平台400被移除，以用於配置在只有SMT的表面202上。因此，模製層143的一只有SMT的表面202可包含球體501至其之接觸墊502的耦接。球體501的厚度可以是大於一或多個耦接至表面202的例如是被動SMT微電子裝置512的SMT構件的厚度。可以附接至接觸墊502的引線接合線131及/或231的末端可以直接耦接至球體501。在此例子中，藉由使得可以是eBVATM線的內嵌的引線接合線231直接耦接在一處於一面朝下的朝向的積體電路晶粒503或503-1與一外部可接達的球體501之間，額外的ESD電路可以被加入到此種積體電路晶粒中。以此種方式，一被動SMT微電子裝置512可以至少部分地在下方 重疊一積體電路晶粒503或503-1，其中此種被動SMT微電子裝置512是處於一面朝上的朝向。
參考圖17B，圖17B的SiP 100係與圖17A的SiP 100相同的，除了電路平台400的表面505係被使用於利用一例如是先前分別參考耦接至表面405及407所敘述的黏著層402來耦接引線接合的積體電路晶粒503及503-1之外。再者，引線接合線509、531及531-1可被使用於相互連接在表面505之上的此種積體電路晶粒503及503-1，儘管例如先前是針對於表面405所敘述的。在此例子中，表面505可以是一只有引線接合的表面。
參考圖17C，圖17C的SiP 100係與圖17A的SiP 100相同的，除了電路平台400的表面505係被使用於利用覆晶的微凸塊413來耦接SMT積體電路晶粒502之外。再者，微凸塊413可被使用於耦接在表面505之上的SMT積體電路晶粒502，例如儘管先前是針對於表面405所敘述的。在此例子中，表面505可以是一只有SMT的表面。
在焊料上的引線接合
已經假設的是引線接合線係被引線接合到一例如是銅的導電金屬層之上。然而，如同在以下用額外的細節敘述的，引線接合線可以被引線接合到焊料之上。以此種方式，化學鎳(Ni)鈀(Pd)浸金(Au)("ENEPIG")是一種例如是用於IC的用於基板製造的表面處理。然而，由於IC製造商對於覆晶的應用是拋棄不用ENEPIG基板，因此使得一基板具有銅與一有機表面保護("OSP")層的混合以及一ENEPIG處理是有問題的。以此種方式，如同在以下用額外的細節敘述的，一銅OSP係對於一疊層的表面是使用一墊上焊料("SOP")，其中例如是BVATM接腳的引線接合線係接合到此種焊料之 上。
圖18A至18D是描繪引線接合墊以及覆晶的墊在同一基板600上的進展形成的側視方塊圖。基板600可以是一封裝基板、或是如上所述用於一SiP或其它微電子構件650的其它基板。以此種方式，具有如同在以下用額外的細節敘述的焊料的引線接合墊可被使用於上述的引線接合線，例如是球體接合至此種墊。
參考圖18A，基板600可以已經在其之一上表面605上沉積、電鍍、或者是形成一導電層603，例如是一層的銅或是其它導電的金屬的層。導電層603可被圖案化以用於在上表面605上提供引線接合墊601、以及覆晶或類似的小形狀因數的墊602。
一焊料遮罩604可加以沉積及圖案化。以此種方式，導電層603的一上表面616可以是在焊料遮罩604的一上表面615之下，並且焊料遮罩604的部分可以是位在墊601及602的相鄰的墊之間。以此種方式，焊料遮罩604可以具有用於接達引線接合墊601的間隙606、以及用於接達覆晶的墊602的較窄的間隙607。
參考圖18B，一焊料或是其它共晶層的焊料或其它共晶墊608及609可被印刷到墊601及602的上表面616之上。一引線接合墊601的一露出的上表面616的一表面積相對一位於其上的焊料墊608的一下表面617的一表面積的比例可以是實質小於一引線接合墊602的一露出的上表面616的一表面積相對一位於其上的焊料墊609的一下表面617的一表面積的比例。焊料墊608及609的每一個的一部分可以是高於焊料遮罩604的上表面615，並且焊料墊609的一部分可以重疊到上表面615之上。上表面615 是在上表面616之上、或是高於上表面616。
參考圖18C，在焊料墊608及609的回焊之後，其之焊料可能會展開，並且一個量的助焊劑可能會消除。以此種方式，一焊料墊608可以展開在原本對應至其的引線接合墊601的一露出的表面區域之上。以此種方式，焊料墊608在回焊之後的上表面611可以是在焊料遮罩層604的上表面615之下、或是低於該上表面615。然而，焊料墊609在回焊之後的上表面613可以是在焊料遮罩層604的上表面615之上，並且可以重疊該上表面615。選配的是，在回焊之後，焊料墊609可以為了平坦化而加以整平。
參考圖18D，例如是引線接合線131的引線接合線可以例如是球體、針腳、或者是其它方式而被接合至焊料墊608。以此種方式，沿著焊料墊608的上表面611的焊料可以附著到引線接合線131的銅、鈀或是其它材料。一覆晶的IC晶粒649可以使得例如是微凸塊的覆晶的接點648分別耦接至焊料墊609。
儘管前述內容係描述根據本發明的一或多個特點的範例實施例，但是根據本發明的該一或多個特點的其它及進一步的實施例可以在不脫離本發明的範疇下而被設計出，該範疇係藉由以下的申請專利範圍以及其等同物來加以決定。申請專利範圍所列的步驟並不意指該些步驟的任何順序。商標則是其個別的擁有者之財產權。
100‧‧‧SiP(多個微電子裝置的封裝)
131‧‧‧引線接合線
143‧‧‧模製層
202‧‧‧上表面
231‧‧‧引線接合線
252‧‧‧最下面的表面
400‧‧‧電路平台
402‧‧‧黏著層
405‧‧‧上表面
407‧‧‧上表面
413‧‧‧互連(微凸塊)
501‧‧‧互連(球體)
502‧‧‧SMT積體電路晶粒
503‧‧‧引線接合的積體電路晶粒
505‧‧‧下表面
507‧‧‧間隙區域
508‧‧‧只有引線接合的區域
509‧‧‧只有SMT的區域
510‧‧‧只有SMT的區域
512‧‧‧被動微電子裝置
531‧‧‧引線接合線

Claims (23)

  1. 一種垂直整合的微電子封裝，其係包括：一電路平台，其係具有一上表面以及一與其之該上表面相對的下表面，該電路平台的該上表面係具有一只有引線接合的表面區域；一第一微電子裝置，其係在該只有引線接合的表面區域中耦接至該電路平台的該上表面；第一引線接合線，其係耦接至該第一微電子裝置的一上表面，而且從該第一微電子裝置的該上表面延伸離開；一第二微電子裝置，其係在一只有表面安裝的區域中處於一面朝下的朝向來耦接至該些第一引線接合線的上方的末端，該第二微電子裝置係位在該第一微電子裝置之上而且至少部分地重疊該第一微電子裝置；第二引線接合線，其係在該只有引線接合的表面區域中耦接至該電路平台的該上表面，並且耦接至該第一微電子裝置的該上表面；一保護層，其係被設置在該電路平台以及該第一微電子裝置之上，該保護層係具有一下表面以及一與其之該下表面相對的上表面，其中該保護層的該下表面係接觸該電路平台的該上表面，該保護層的該上表面係具有該只有表面安裝的區域；以及該保護層的該上表面係在該只有表面安裝的區域中具有被設置於其上的處於該面朝下的朝向的該第二微電子裝置，以用於耦接至該些第一引線接合線的該些上方的末端。
  2. 根據申請專利範圍第1項之垂直整合的微電子封裝，其進一步包括第三引線接合線，該些第三引線接合線係在該只有引線接合的表面區域中耦 接至該電路平台的該上表面，而且從該電路平台的該上表面延伸離開，其中該些第三引線接合線的上方的末端係在該只有表面安裝的區域中耦接至處於該面朝下的朝向的該第二微電子裝置。
  3. 根據申請專利範圍第2項之垂直整合的微電子封裝，其中該保護層係被設置以用於圍繞該些第一引線接合線以及該些第三引線接合線的長度的至少部分，並且用於覆蓋該些第二引線接合線。
  4. 根據申請專利範圍第2項之垂直整合的微電子封裝，其中該只有表面安裝的區域的至少一部分係對應於該只有引線接合的表面區域。
  5. 根據申請專利範圍第2項之垂直整合的微電子封裝，其進一步包括：一第三微電子裝置，其係在該只有引線接合的表面區域中處於一面朝上的朝向來耦接至該電路平台的該上表面，其係在兩者之間的一間隙下相鄰該第一微電子裝置；以及該些第三引線接合線以及該些第二引線接合線的下方的末端係在該第一微電子裝置以及該第三微電子裝置之間耦接至該電路平台的該上表面。
  6. 根據申請專利範圍第5項之垂直整合的微電子封裝，其進一步包括：一第四微電子裝置，其係在該只有引線接合的表面區域中處於該面朝上的朝向來耦接至該電路平台的該上表面；以及第四引線接合線係將該第一微電子裝置的該上表面與該第四微電子裝置的該上表面相互連接。
  7. 根據申請專利範圍第1項之垂直整合的微電子封裝，其中該第二微電子裝置是一被動微電子裝置。
  8. 根據申請專利範圍第1項之垂直整合的微電子封裝，其中該第二微電 子裝置係包含一具有0.1或更大微法拉的電容器。
  9. 根據申請專利範圍第1項之垂直整合的微電子封裝，其中該第二微電子裝置係為了一具有1或更高GHz的頻率響應而包含一耦接至該第一微電子裝置的電容器。
  10. 根據申請專利範圍第1項之垂直整合的微電子封裝，其中該第二微電子裝置是一主動微電子裝置。
  11. 根據申請專利範圍第1項之垂直整合的微電子封裝，其中該些第二引線接合線的每一個係具有大約一毫微亨利或更小的自感。
  12. 一種倒置的垂直整合的微電子封裝，其係包括：一電路平台，其係具有一上表面以及一與其之該上表面相對的下表面，該電路平台的該下表面係具有一只有引線接合的表面區域；一第一微電子裝置，其係在該只有引線接合的表面區域中耦接至該電路平台的該下表面；第一引線接合線，其係耦接至該第一微電子裝置的一下表面，而且從該第一微電子裝置的該下表面延伸離開；一第二微電子裝置，其係在一只有表面安裝的區域中處於一面朝上的朝向來耦接至該些第一引線接合線的下方的末端，該第二微電子裝置係位在該第一微電子裝置之下而且至少部分地在下方重疊該第一微電子裝置；第二引線接合線，其係在該只有引線接合的表面區域中耦接至該電路平台的該下表面，而且從該電路平台的該下表面延伸離開，並且耦接至該第一微電子裝置的該下表面；一保護層，其係被設置在該電路平台以及該第一微電子裝置之下，該 保護層係具有一下表面以及一與其之該下表面相對的上表面，其中該保護層的該上表面係接觸該電路平台的該下表面，該保護層的該下表面係具有該只有表面安裝的區域；以及該保護層的該下表面係在該只有表面安裝的區域中具有被設置於其上的處於該面朝上的朝向的該第二微電子裝置，以用於耦接至該些第一引線接合線的該些下方的末端。
  13. 根據申請專利範圍第12項之倒置的垂直整合的微電子封裝，其進一步包括第三引線接合線，該些第三引線接合線係在該只有引線接合的表面區域中耦接至該電路平台的該下表面，而且從該電路平台的該下表面延伸離開，其中該些第三引線接合線的下方的末端係在該只有表面安裝的區域中耦接至處於該面朝上的朝向的該第二微電子裝置。
  14. 根據申請專利範圍第13項之倒置的垂直整合的微電子封裝，其中該保護層係被設置以用於圍繞該些第一引線接合線以及該些第三引線接合線的長度的至少部分，並且用於覆蓋該些第二引線接合線。
  15. 根據申請專利範圍第13項之倒置的垂直整合的微電子封裝，其中：該保護層係被設置以覆蓋該第一微電子裝置的該下表面；該保護層的該上表面係接觸該電路平台的該下表面；以及互連係在該只有表面安裝的區域中，在該保護層的該下表面上耦接至該些第一引線接合線以及該些第三引線接合線的下方的末端。
  16. 根據申請專利範圍第13項之倒置的垂直整合的微電子封裝，其進一步包括：一第三微電子裝置，其係在該只有引線接合的表面區域中處於一面朝 下的朝向來耦接至該電路平台的該下表面，其係在兩者之間的一間隙下相鄰該第一微電子裝置；以及該些第三引線接合線以及該些第二引線接合線的下方的末端係在該第一微電子裝置以及該第三微電子裝置之間耦接至該電路平台的該下表面。
  17. 根據申請專利範圍第16項之倒置的垂直整合的微電子封裝，其進一步包括：一第四微電子裝置，其係在該只有引線接合的表面區域中處於該面朝下的朝向來耦接至該電路平台的該下表面；以及第四引線接合線係將該第一微電子裝置的該下表面與該第四微電子裝置的該下表面相互連接。
  18. 根據申請專利範圍第12項之倒置的垂直整合的微電子封裝，其中該第二微電子裝置是一被動微電子裝置。
  19. 根據申請專利範圍第12項之倒置的垂直整合的微電子封裝，其中該第二微電子裝置係包含一具有0.1或更大微法拉的電容器。
  20. 根據申請專利範圍第12項之倒置的垂直整合的微電子封裝，其中該第二微電子裝置係為了一具有1或更高GHz的頻率響應而包含一耦接至該第一微電子裝置的電容器。
  21. 根據申請專利範圍第12項之倒置的垂直整合的微電子封裝，其中該些第二引線接合線的每一個係具有大約一毫微亨利或更小的自感。
  22. 根據申請專利範圍第12項之倒置的垂直整合的微電子封裝，其中該第二微電子裝置是一主動微電子裝置。
  23. 一種微電子構件，其係包括： 一基板，其係具有一第一上表面；一導電層，其係被設置在該第一上表面上，其係包含分別具有第一上表面以及第二上表面的引線接合墊以及覆晶的墊；一焊料遮罩，其係被設置在介於該些引線接合墊以及該些覆晶的墊之間的該第一上表面上，該焊料遮罩係具有一被設置在該些第一上表面以及該些第二上表面之上的第二上表面；一共晶層，其係被設置在該些第一上表面以及該些第二上表面上；以及引線接合線，其係分別接合至該些引線接合墊。
TW105141581A 2015-12-30 2016-12-15 用於具有分離的表面安裝及引線接合安裝表面的垂直整合之嵌入式引線接合線 TW201735287A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201562273145P 2015-12-30 2015-12-30
US14/997,774 US9984992B2 (en) 2015-12-30 2016-01-18 Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces

Publications (1)

Publication Number Publication Date
TW201735287A true TW201735287A (zh) 2017-10-01

Family

ID=59225822

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105141581A TW201735287A (zh) 2015-12-30 2016-12-15 用於具有分離的表面安裝及引線接合安裝表面的垂直整合之嵌入式引線接合線

Country Status (6)

Country Link
US (2) US9984992B2 (zh)
EP (1) EP3398207A4 (zh)
KR (1) KR102436803B1 (zh)
CN (1) CN108369942B (zh)
TW (1) TW201735287A (zh)
WO (1) WO2017116981A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12009314B2 (en) 2022-08-11 2024-06-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of compartment shielding using bond wires

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10483250B2 (en) * 2015-11-04 2019-11-19 Intel Corporation Three-dimensional small form factor system in package architecture
WO2017130421A1 (ja) * 2016-01-31 2017-08-03 新電元工業株式会社 半導体モジュール
US20180019194A1 (en) * 2016-07-14 2018-01-18 Semtech Corporation Low Parasitic Surface Mount Circuit Over Wirebond IC
US11158595B2 (en) * 2017-07-07 2021-10-26 Texas Instruments Incorporated Embedded die package multichip module
US10103038B1 (en) 2017-08-24 2018-10-16 Micron Technology, Inc. Thrumold post package with reverse build up hybrid additive structure
US20190067248A1 (en) * 2017-08-24 2019-02-28 Micron Technology, Inc. Semiconductor device having laterally offset stacked semiconductor dies
US10304697B2 (en) * 2017-10-05 2019-05-28 Amkor Technology, Inc. Electronic device with top side pin array and manufacturing method thereof
CN108511400B (zh) * 2018-03-16 2023-10-03 盛合晶微半导体(江阴)有限公司 天线的封装结构及封装方法
US10854951B2 (en) * 2018-03-16 2020-12-01 Sj Semiconductor (Jiangyin) Corporation Antenna package structure and antenna packaging method
US10886594B2 (en) * 2018-03-16 2021-01-05 Sj Semiconductor (Jiangyin) Corporation Packaging structure and packaging method for antenna
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
US11127689B2 (en) 2018-06-01 2021-09-21 Qorvo Us, Inc. Segmented shielding using wirebonds
US10593647B2 (en) * 2018-06-27 2020-03-17 Powertech Technology Inc. Package structure and manufacturing method thereof
US11219144B2 (en) 2018-06-28 2022-01-04 Qorvo Us, Inc. Electromagnetic shields for sub-modules
US10867955B2 (en) * 2018-09-27 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure having adhesive layer surrounded dam structure
US11114363B2 (en) 2018-12-20 2021-09-07 Qorvo Us, Inc. Electronic package arrangements and related methods
KR20200118720A (ko) 2019-04-08 2020-10-16 삼성전자주식회사 이미지 센서 및 이를 포함하는 시스템
US11515282B2 (en) * 2019-05-21 2022-11-29 Qorvo Us, Inc. Electromagnetic shields with bonding wires for sub-modules
CN113270388A (zh) * 2020-02-14 2021-08-17 达发科技(苏州)有限公司 集成电路封装结构
CN111554649A (zh) * 2020-05-14 2020-08-18 甬矽电子(宁波)股份有限公司 半导体封装结构和半导体封装结构制作方法
JP2022033633A (ja) * 2020-08-17 2022-03-02 キオクシア株式会社 半導体装置
NL2027022B1 (en) * 2020-12-01 2022-07-06 Ampleon Netherlands Bv Electronic package and device comprising the same
US11973010B2 (en) 2020-12-04 2024-04-30 Richtek Technology Corporation Chip packaging method and chip package unit
CN113056098B (zh) * 2021-02-10 2022-09-23 华为数字能源技术有限公司 电子元件封装体、电子元件组装结构及电子设备

Family Cites Families (801)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2230663A (en) 1940-01-18 1941-02-04 Alden Milton Electric contact and wire assembly mechanism
DE1439262B2 (de) 1963-07-23 1972-03-30 Siemens AG, 1000 Berlin u. 8000 München Verfahren zum kontaktieren von halbleiterbauelementen durch thermokompression
US3358897A (en) 1964-03-31 1967-12-19 Tempress Res Co Electric lead wire bonding tools
US3430835A (en) 1966-06-07 1969-03-04 Westinghouse Electric Corp Wire bonding apparatus for microelectronic components
US3623649A (en) 1969-06-09 1971-11-30 Gen Motors Corp Wedge bonding tool for the attachment of semiconductor leads
DE2119567C2 (de) 1970-05-05 1983-07-14 International Computers Ltd., London Elektrische Verbindungsvorrichtung und Verfahren zu ihrer Herstellung
DE2228703A1 (de) 1972-06-13 1974-01-10 Licentia Gmbh Verfahren zum herstellen einer vorgegebenen lotschichtstaerke bei der fertigung von halbleiterbauelementen
JPS5150661A (zh) 1974-10-30 1976-05-04 Hitachi Ltd
US4072816A (en) 1976-12-13 1978-02-07 International Business Machines Corporation Integrated circuit package
US4067104A (en) 1977-02-24 1978-01-10 Rockwell International Corporation Method of fabricating an array of flexible metallic interconnects for coupling microelectronics components
US4213556A (en) 1978-10-02 1980-07-22 General Motors Corporation Method and apparatus to detect automatic wire bonder failure
US4327860A (en) 1980-01-03 1982-05-04 Kulicke And Soffa Ind. Inc. Method of making slack free wire interconnections
US4422568A (en) 1981-01-12 1983-12-27 Kulicke And Soffa Industries, Inc. Method of making constant bonding wire tail lengths
US4437604A (en) 1982-03-15 1984-03-20 Kulicke & Soffa Industries, Inc. Method of making fine wire interconnections
JPS59189069A (ja) 1983-04-12 1984-10-26 Alps Electric Co Ltd 電気部品の端子のハンダ塗布装置
JPS61125062A (ja) 1984-11-22 1986-06-12 Hitachi Ltd ピン取付け方法およびピン取付け装置
US4667267A (en) 1985-01-22 1987-05-19 Rogers Corporation Decoupling capacitor for pin grid array package
US4604644A (en) 1985-01-28 1986-08-05 International Business Machines Corporation Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making
US4642889A (en) 1985-04-29 1987-02-17 Amp Incorporated Compliant interconnection and method therefor
JPS61269345A (ja) 1985-05-24 1986-11-28 Hitachi Ltd 半導体装置
US5917707A (en) 1993-11-16 1999-06-29 Formfactor, Inc. Flexible contact structure with an electrically conductive shell
US5476211A (en) 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
US4924353A (en) 1985-12-20 1990-05-08 Hughes Aircraft Company Connector system for coupling to an integrated circuit chip
US4716049A (en) 1985-12-20 1987-12-29 Hughes Aircraft Company Compressive pedestal for microminiature connections
JPS62158338A (ja) 1985-12-28 1987-07-14 Tanaka Denshi Kogyo Kk 半導体装置
US4793814A (en) 1986-07-21 1988-12-27 Rogers Corporation Electrical circuit board interconnect
US4695870A (en) 1986-03-27 1987-09-22 Hughes Aircraft Company Inverted chip carrier
JPS62226307A (ja) 1986-03-28 1987-10-05 Toshiba Corp ロボツト装置
US4771930A (en) 1986-06-30 1988-09-20 Kulicke And Soffa Industries Inc. Apparatus for supplying uniform tail lengths
JPS6397941A (ja) 1986-10-14 1988-04-28 Fuji Photo Film Co Ltd 感光材料
US4955523A (en) 1986-12-17 1990-09-11 Raychem Corporation Interconnection of electronic components
DE3703694A1 (de) 1987-02-06 1988-08-18 Dynapert Delvotec Gmbh Ball-bondverfahren und vorrichtung zur durchfuehrung derselben
KR970003915B1 (ko) 1987-06-24 1997-03-22 미다 가쓰시게 반도체 기억장치 및 그것을 사용한 반도체 메모리 모듈
US5138438A (en) 1987-06-24 1992-08-11 Akita Electronics Co. Ltd. Lead connections means for stacked tab packaged IC chips
JP2642359B2 (ja) 1987-09-11 1997-08-20 株式会社日立製作所 半導体装置
JPS6412769A (en) 1987-07-07 1989-01-17 Sony Corp Correction circuit for image distortion
US4804132A (en) 1987-08-28 1989-02-14 Difrancesco Louis Method for cold bonding
US4867267A (en) 1987-10-14 1989-09-19 Industrial Research Products, Inc. Hearing aid transducer
JPH01118364A (ja) 1987-10-30 1989-05-10 Fujitsu Ltd 予備半田ディップ方法
US4845354A (en) 1988-03-08 1989-07-04 International Business Machines Corporation Process control for laser wire bonding
JPH01313969A (ja) 1988-06-13 1989-12-19 Hitachi Ltd 半導体装置
US4998885A (en) 1989-10-27 1991-03-12 International Business Machines Corporation Elastomeric area array interposer
US5077598A (en) 1989-11-08 1991-12-31 Hewlett-Packard Company Strain relief flip-chip integrated circuit assembly with test fixturing
US5095187A (en) 1989-12-20 1992-03-10 Raychem Corporation Weakening wire supplied through a wire bonder
AU645283B2 (en) 1990-01-23 1994-01-13 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device
CA2034700A1 (en) 1990-01-23 1991-07-24 Masanori Nishiguchi Substrate for packaging a semiconductor device
US5948533A (en) 1990-02-09 1999-09-07 Ormet Corporation Vertically interconnected electronic assemblies and compositions useful therefor
US5376403A (en) 1990-02-09 1994-12-27 Capote; Miguel A. Electrically conductive compositions and methods for the preparation and use thereof
US5083697A (en) 1990-02-14 1992-01-28 Difrancesco Louis Particle-enhanced joining of metal surfaces
US4975079A (en) 1990-02-23 1990-12-04 International Business Machines Corp. Connector assembly for chip testing
US4999472A (en) 1990-03-12 1991-03-12 Neinast James E Electric arc system for ablating a surface coating
US5241456A (en) 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5067382A (en) 1990-11-02 1991-11-26 Cray Computer Corporation Method and apparatus for notching a lead wire attached to an IC chip to facilitate severing the wire
KR940001149B1 (ko) 1991-04-16 1994-02-14 삼성전자 주식회사 반도체 장치의 칩 본딩 방법
JPH04346436A (ja) 1991-05-24 1992-12-02 Fujitsu Ltd バンプ製造方法とバンプ製造装置
US5316788A (en) 1991-07-26 1994-05-31 International Business Machines Corporation Applying solder to high density substrates
US5203075A (en) 1991-08-12 1993-04-20 Inernational Business Machines Method of bonding flexible circuit to cicuitized substrate to provide electrical connection therebetween using different solders
US5133495A (en) 1991-08-12 1992-07-28 International Business Machines Corporation Method of bonding flexible circuit to circuitized substrate to provide electrical connection therebetween
WO1993004375A1 (en) 1991-08-23 1993-03-04 Nchip, Inc. Burn-in technologies for unpackaged integrated circuits
US5220489A (en) 1991-10-11 1993-06-15 Motorola, Inc. Multicomponent integrated circuit package
US5238173A (en) 1991-12-04 1993-08-24 Kaijo Corporation Wire bonding misattachment detection apparatus and that detection method in a wire bonder
JP2931936B2 (ja) 1992-01-17 1999-08-09 株式会社日立製作所 半導体装置用リードフレームの製造方法及び半導体装置用リードフレーム並びに樹脂封止型半導体装置
US5241454A (en) 1992-01-22 1993-08-31 International Business Machines Corporation Mutlilayered flexible circuit package
US5831836A (en) 1992-01-30 1998-11-03 Lsi Logic Power plane for semiconductor device
US5222014A (en) 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5438224A (en) 1992-04-23 1995-08-01 Motorola, Inc. Integrated circuit package having a face-to-face IC chip arrangement
US5494667A (en) 1992-06-04 1996-02-27 Kabushiki Kaisha Hayahibara Topically applied hair restorer containing pine extract
JP3151219B2 (ja) 1992-07-24 2001-04-03 テツセラ，インコーポレイテッド 取り外し自在のリード支持体を備えた半導体接続構成体およびその製造方法
US5977618A (en) 1992-07-24 1999-11-02 Tessera, Inc. Semiconductor connection components and methods with releasable lead support
US6054756A (en) 1992-07-24 2000-04-25 Tessera, Inc. Connection components with frangible leads and bus
US5371654A (en) 1992-10-19 1994-12-06 International Business Machines Corporation Three dimensional high performance interconnection package
US6295729B1 (en) 1992-10-19 2001-10-02 International Business Machines Corporation Angled flying lead wire bonding process
US20050062492A1 (en) 2001-08-03 2005-03-24 Beaman Brian Samuel High density integrated circuit apparatus, test probe and methods of use thereof
JP2716336B2 (ja) 1993-03-10 1998-02-18 日本電気株式会社 集積回路装置
JPH06268101A (ja) 1993-03-17 1994-09-22 Hitachi Ltd 半導体装置及びその製造方法、電子装置、リ−ドフレ−ム並びに実装基板
US5340771A (en) 1993-03-18 1994-08-23 Lsi Logic Corporation Techniques for providing high I/O count connections to semiconductor dies
US5811982A (en) 1995-11-27 1998-09-22 International Business Machines Corporation High density cantilevered probe for electronic devices
US7368924B2 (en) 1993-04-30 2008-05-06 International Business Machines Corporation Probe structure having a plurality of discrete insulated probe tips projecting from a support surface, apparatus for use thereof and methods of fabrication thereof
US20030048108A1 (en) 1993-04-30 2003-03-13 Beaman Brian Samuel Structural design and processes to control probe position accuracy in a wafer test probe assembly
JPH06333931A (ja) 1993-05-20 1994-12-02 Nippondenso Co Ltd 半導体装置における微細電極の製造方法
JP2981385B2 (ja) 1993-09-06 1999-11-22 シャープ株式会社 チップ部品型ｌｅｄの構造及びその製造方法
US5346118A (en) 1993-09-28 1994-09-13 At&T Bell Laboratories Surface mount solder assembly of leadless integrated circuit packages to substrates
US6741085B1 (en) 1993-11-16 2004-05-25 Formfactor, Inc. Contact carriers (tiles) for populating larger substrates with spring contacts
US6835898B2 (en) 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
US5455390A (en) 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
KR100437437B1 (ko) 1994-03-18 2004-06-25 히다치 가세고교 가부시끼가이샤 반도체 패키지의 제조법 및 반도체 패키지
US5578869A (en) 1994-03-29 1996-11-26 Olin Corporation Components for housing an integrated circuit device
US5802699A (en) 1994-06-07 1998-09-08 Tessera, Inc. Methods of assembling microelectronic assembly with socket for engaging bump leads
US5615824A (en) 1994-06-07 1997-04-01 Tessera, Inc. Soldering with resilient contacts
JPH07335783A (ja) 1994-06-13 1995-12-22 Fujitsu Ltd 半導体装置及び半導体装置ユニット
US5468995A (en) 1994-07-05 1995-11-21 Motorola, Inc. Semiconductor device having compliant columnar electrical connections
US5688716A (en) 1994-07-07 1997-11-18 Tessera, Inc. Fan-out semiconductor chip assembly
US5518964A (en) 1994-07-07 1996-05-21 Tessera, Inc. Microelectronic mounting with multiple lead deformation and bonding
US5989936A (en) 1994-07-07 1999-11-23 Tessera, Inc. Microelectronic assembly fabrication with terminal formation from a conductive layer
US6177636B1 (en) 1994-12-29 2001-01-23 Tessera, Inc. Connection components with posts
US6117694A (en) 1994-07-07 2000-09-12 Tessera, Inc. Flexible lead structures and methods of making same
US6828668B2 (en) 1994-07-07 2004-12-07 Tessera, Inc. Flexible lead structures and methods of making same
US5656550A (en) 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US5659952A (en) 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
US5541567A (en) 1994-10-17 1996-07-30 International Business Machines Corporation Coaxial vias in an electronic substrate
US5495667A (en) 1994-11-07 1996-03-05 Micron Technology, Inc. Method for forming contact pins for semiconductor dice and interconnects
KR100394205B1 (ko) 1994-11-15 2003-08-06 폼팩터, 인크. 시험된 반도체 장치 및 시험된 반도체 장치의 제조방법
US6826827B1 (en) 1994-12-29 2004-12-07 Tessera, Inc. Forming conductive posts by selective removal of conductive material
US5736074A (en) 1995-06-30 1998-04-07 Micro Fab Technologies, Inc. Manufacture of coated spheres
US5971253A (en) 1995-07-31 1999-10-26 Tessera, Inc. Microelectronic component mounting with deformable shell terminals
US5872051A (en) 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US5886412A (en) 1995-08-16 1999-03-23 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device
US5874781A (en) 1995-08-16 1999-02-23 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US5810609A (en) 1995-08-28 1998-09-22 Tessera, Inc. Socket for engaging bump leads on a microelectronic device and methods therefor
US5766987A (en) 1995-09-22 1998-06-16 Tessera, Inc. Microelectronic encapsulation methods and equipment
US6211572B1 (en) 1995-10-31 2001-04-03 Tessera, Inc. Semiconductor chip package with fan-in leads
JP3332308B2 (ja) 1995-11-07 2002-10-07 新光電気工業株式会社 半導体装置及びその製造方法
JPH09134934A (ja) 1995-11-07 1997-05-20 Sumitomo Metal Ind Ltd 半導体パッケージ及び半導体装置
US5718361A (en) 1995-11-21 1998-02-17 International Business Machines Corporation Apparatus and method for forming mold for metallic material
US5731709A (en) 1996-01-26 1998-03-24 Motorola, Inc. Method for testing a ball grid array semiconductor device and a device for such testing
US7166495B2 (en) 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
US5994152A (en) 1996-02-21 1999-11-30 Formfactor, Inc. Fabricating interconnects and tips using sacrificial substrates
JP3146345B2 (ja) 1996-03-11 2001-03-12 アムコー テクノロジー コリア インコーポレーティド バンプチップスケール半導体パッケージのバンプ形成方法
US6000126A (en) 1996-03-29 1999-12-14 General Dynamics Information Systems, Inc. Method and apparatus for connecting area grid arrays to printed wire board
US6821821B2 (en) 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
DE19618227A1 (de) 1996-05-07 1997-11-13 Herbert Streckfus Gmbh Verfahren und Vorrichtung zum Verlöten von elektronischen Bauelementen auf einer Leiterplatte
KR100186333B1 (ko) 1996-06-20 1999-03-20 문정환 칩 사이즈 반도체 패키지 및 그 제조방법
JPH10135220A (ja) 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd バンプ形成方法
KR100377033B1 (ko) 1996-10-29 2003-03-26 트러시 테크날러지스 엘엘시 Ｉｃ 및 그 제조방법
JPH10135221A (ja) 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd バンプ形成方法
US6492719B2 (en) 1999-07-30 2002-12-10 Hitachi, Ltd. Semiconductor device
US5976913A (en) 1996-12-12 1999-11-02 Tessera, Inc. Microelectronic mounting with multiple lead deformation using restraining straps
US6121676A (en) 1996-12-13 2000-09-19 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6054337A (en) 1996-12-13 2000-04-25 Tessera, Inc. Method of making a compliant multichip package
US6225688B1 (en) 1997-12-11 2001-05-01 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6133072A (en) 1996-12-13 2000-10-17 Tessera, Inc. Microelectronic connector with planar elastomer sockets
US5736785A (en) 1996-12-20 1998-04-07 Industrial Technology Research Institute Semiconductor package for improving the capability of spreading heat
JP3400279B2 (ja) 1997-01-13 2003-04-28 株式会社新川 バンプ形成方法
US5898991A (en) 1997-01-16 1999-05-04 International Business Machines Corporation Methods of fabrication of coaxial vias and magnetic devices
US5839191A (en) 1997-01-24 1998-11-24 Unisys Corporation Vibrating template method of placing solder balls on the I/O pads of an integrated circuit package
EP1030369B1 (en) 1997-08-19 2007-12-12 Hitachi, Ltd. Multichip module structure and method for manufacturing the same
CA2213590C (en) 1997-08-21 2006-11-07 Keith C. Carroll Flexible circuit connector and method of making same
JP3859318B2 (ja) 1997-08-29 2006-12-20 シチズン電子株式会社 電子回路のパッケージ方法
US6525414B2 (en) 1997-09-16 2003-02-25 Matsushita Electric Industrial Co., Ltd. Semiconductor device including a wiring board and semiconductor elements mounted thereon
JP3937265B2 (ja) 1997-09-29 2007-06-27 エルピーダメモリ株式会社 半導体装置
JP3262531B2 (ja) 1997-10-02 2002-03-04 インターナショナル・ビジネス・マシーンズ・コーポレーション 曲げられたフライング・リード・ワイヤ・ボンデイング・プロセス
JP2978861B2 (ja) 1997-10-28 1999-11-15 九州日本電気株式会社 モールドｂｇａ型半導体装置及びその製造方法
US6038136A (en) 1997-10-29 2000-03-14 Hestia Technologies, Inc. Chip package with molded underfill
JP3393800B2 (ja) 1997-11-05 2003-04-07 新光電気工業株式会社 半導体装置の製造方法
JPH11219984A (ja) 1997-11-06 1999-08-10 Sharp Corp 半導体装置パッケージおよびその製造方法ならびにそのための回路基板
US6222136B1 (en) 1997-11-12 2001-04-24 International Business Machines Corporation Printed circuit board with continuous connective bumps
US6038133A (en) 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
US6002168A (en) 1997-11-25 1999-12-14 Tessera, Inc. Microelectronic component with rigid interposer
JPH11163022A (ja) 1997-11-28 1999-06-18 Sony Corp 半導体装置、その製造方法及び電子機器
US6124546A (en) 1997-12-03 2000-09-26 Advanced Micro Devices, Inc. Integrated circuit chip package and method of making the same
US6260264B1 (en) 1997-12-08 2001-07-17 3M Innovative Properties Company Methods for making z-axis electrical connections
US6052287A (en) 1997-12-09 2000-04-18 Sandia Corporation Silicon ball grid array chip carrier
US5973391A (en) 1997-12-11 1999-10-26 Read-Rite Corporation Interposer with embedded circuitry and method for using the same to package microelectronic units
JPH11220082A (ja) 1998-02-03 1999-08-10 Oki Electric Ind Co Ltd 半導体装置
JP3536650B2 (ja) 1998-02-27 2004-06-14 富士ゼロックス株式会社 バンプ形成方法および装置
JPH11260856A (ja) 1998-03-11 1999-09-24 Matsushita Electron Corp 半導体装置及びその製造方法並びに半導体装置の実装構造
US5933713A (en) 1998-04-06 1999-08-03 Micron Technology, Inc. Method of forming overmolded chip scale package and resulting product
US6222276B1 (en) 1998-04-07 2001-04-24 International Business Machines Corporation Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
KR100260997B1 (ko) 1998-04-08 2000-07-01 마이클 디. 오브라이언 반도체패키지
US6329224B1 (en) 1998-04-28 2001-12-11 Tessera, Inc. Encapsulation of microelectronic assemblies
US6180881B1 (en) 1998-05-05 2001-01-30 Harlan Ruben Isaak Chip stack and method of making same
JPH11330134A (ja) 1998-05-12 1999-11-30 Hitachi Ltd ワイヤボンディング方法およびその装置並びに半導体装置
KR100266693B1 (ko) 1998-05-30 2000-09-15 김영환 적층가능한 비지에이 반도체 칩 패키지 및 그 제조방법
US5977640A (en) 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
KR100265563B1 (ko) 1998-06-29 2000-09-15 김영환 볼 그리드 어레이 패키지 및 그의 제조 방법
US6414391B1 (en) 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
US6164523A (en) 1998-07-01 2000-12-26 Semiconductor Components Industries, Llc Electronic component and method of manufacture
US6399426B1 (en) 1998-07-21 2002-06-04 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US5854507A (en) 1998-07-21 1998-12-29 Hewlett-Packard Company Multiple chip assembly
US6515355B1 (en) 1998-09-02 2003-02-04 Micron Technology, Inc. Passivation layer for packaged integrated circuits
JP2000091383A (ja) 1998-09-07 2000-03-31 Ngk Spark Plug Co Ltd 配線基板
US6194250B1 (en) 1998-09-14 2001-02-27 Motorola, Inc. Low-profile microelectronic package
US6158647A (en) 1998-09-29 2000-12-12 Micron Technology, Inc. Concave face wire bond capillary
US6684007B2 (en) 1998-10-09 2004-01-27 Fujitsu Limited Optical coupling structures and the fabrication processes
JP2000311915A (ja) 1998-10-14 2000-11-07 Texas Instr Inc <Ti> 半導体デバイス及びボンディング方法
JP3407275B2 (ja) 1998-10-28 2003-05-19 インターナショナル・ビジネス・マシーンズ・コーポレーション バンプ及びその形成方法
US6332270B2 (en) 1998-11-23 2001-12-25 International Business Machines Corporation Method of making high density integral test probe
US6255126B1 (en) 1998-12-02 2001-07-03 Formfactor, Inc. Lithographic contact elements
US6926796B1 (en) 1999-01-29 2005-08-09 Matsushita Electric Industrial Co., Ltd. Electronic parts mounting method and device therefor
US6206273B1 (en) 1999-02-17 2001-03-27 International Business Machines Corporation Structures and processes to create a desired probetip contact geometry on a wafer test probe
KR100319609B1 (ko) 1999-03-09 2002-01-05 김영환 와이어 어래이드 칩 사이즈 패키지 및 그 제조방법
US6177729B1 (en) 1999-04-03 2001-01-23 International Business Machines Corporation Rolling ball connector
US6211574B1 (en) 1999-04-16 2001-04-03 Advanced Semiconductor Engineering Inc. Semiconductor package with wire protection and method therefor
JP2000323516A (ja) 1999-05-14 2000-11-24 Fujitsu Ltd 配線基板の製造方法及び配線基板及び半導体装置
US6258625B1 (en) 1999-05-18 2001-07-10 International Business Machines Corporation Method of interconnecting electronic components using a plurality of conductive studs
US6376769B1 (en) 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
JP3398721B2 (ja) 1999-05-20 2003-04-21 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ及びその製造方法
US6238949B1 (en) 1999-06-18 2001-05-29 National Semiconductor Corporation Method and apparatus for forming a plastic chip on chip package module
JP4367730B2 (ja) 1999-06-25 2009-11-18 株式会社エンプラス Ｉｃソケット及び該ｉｃソケットのバネ手段
US6228687B1 (en) 1999-06-28 2001-05-08 Micron Technology, Inc. Wafer-level package and methods of fabricating
TW417839U (en) 1999-07-30 2001-01-01 Shen Ming Tung Stacked memory module structure and multi-layered stacked memory module structure using the same
JP5333337B2 (ja) 1999-08-12 2013-11-06 富士通セミコンダクター株式会社 半導体装置の製造方法
JP4526651B2 (ja) 1999-08-12 2010-08-18 富士通セミコンダクター株式会社 半導体装置
US6168965B1 (en) 1999-08-12 2001-01-02 Tower Semiconductor Ltd. Method for making backside illuminated image sensor
US6319764B1 (en) 1999-08-25 2001-11-20 Micron Technology, Inc. Method of forming haze-free BST films
EP1139705B1 (en) 1999-09-02 2006-11-22 Ibiden Co., Ltd. Printed wiring board and method of producing the same
US6867499B1 (en) 1999-09-30 2005-03-15 Skyworks Solutions, Inc. Semiconductor packaging
JP3513444B2 (ja) 1999-10-20 2004-03-31 株式会社新川 ピン状ワイヤ等の形成方法
JP2001127246A (ja) 1999-10-29 2001-05-11 Fujitsu Ltd 半導体装置
US6362525B1 (en) 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
JP3619410B2 (ja) 1999-11-18 2005-02-09 株式会社ルネサステクノロジ バンプ形成方法およびそのシステム
JP3798597B2 (ja) 1999-11-30 2006-07-19 富士通株式会社 半導体装置
JP3566156B2 (ja) 1999-12-02 2004-09-15 株式会社新川 ピン状ワイヤ等の形成方法
KR100426494B1 (ko) 1999-12-20 2004-04-13 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이것의 제조방법
US6790757B1 (en) 1999-12-20 2004-09-14 Agere Systems Inc. Wire bonding method for copper interconnects in semiconductor devices
KR20010061849A (ko) 1999-12-29 2001-07-07 박종섭 웨이퍼 레벨 패키지
JP2001196407A (ja) 2000-01-14 2001-07-19 Seiko Instruments Inc 半導体装置および半導体装置の形成方法
US6710454B1 (en) 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
JP2001319992A (ja) 2000-02-28 2001-11-16 Shinko Electric Ind Co Ltd 配線基板、半導体装置及びそれらの製造方法
JP2001339011A (ja) 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
JP3980807B2 (ja) 2000-03-27 2007-09-26 株式会社東芝 半導体装置及び半導体モジュール
JP2001274196A (ja) 2000-03-28 2001-10-05 Rohm Co Ltd 半導体装置
US6581276B2 (en) 2000-04-04 2003-06-24 Amerasia International Technology, Inc. Fine-pitch flexible connector, and method for making same
KR100583491B1 (ko) 2000-04-07 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조방법
US6578754B1 (en) 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6531335B1 (en) 2000-04-28 2003-03-11 Micron Technology, Inc. Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods
JP2001326236A (ja) 2000-05-12 2001-11-22 Nec Kyushu Ltd 半導体装置の製造方法
JP2001326304A (ja) 2000-05-15 2001-11-22 Toshiba Corp 半導体装置及びその製造方法
US6522018B1 (en) 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
US6647310B1 (en) 2000-05-30 2003-11-11 Advanced Micro Devices, Inc. Temperature control of an integrated circuit
US6717245B1 (en) 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6395199B1 (en) 2000-06-07 2002-05-28 Graftech Inc. Process for providing increased conductivity to a material
US6560117B2 (en) 2000-06-28 2003-05-06 Micron Technology, Inc. Packaged microelectronic die assemblies and methods of manufacture
US6525413B1 (en) 2000-07-12 2003-02-25 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US6476583B2 (en) 2000-07-21 2002-11-05 Jomahip, Llc Automatic battery charging system for a battery back-up DC power supply
JP2002050871A (ja) 2000-08-02 2002-02-15 Casio Comput Co Ltd ビルドアップ回路基板およびその製造方法
SE517086C2 (sv) 2000-08-08 2002-04-09 Ericsson Telefon Ab L M Förfarande för säkring av lodkulor och eventuella komponenter, vilka är fästa på en och samma sida av ett substrat
US20020020898A1 (en) 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6462575B1 (en) 2000-08-28 2002-10-08 Micron Technology, Inc. Method and system for wafer level testing and burning-in semiconductor components
JP2002076250A (ja) 2000-08-29 2002-03-15 Nec Corp 半導体装置
US6614103B1 (en) 2000-09-01 2003-09-02 General Electric Company Plastic packaging of LED arrays
JP3874062B2 (ja) 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
US6507104B2 (en) 2000-09-07 2003-01-14 Siliconware Precision Industries Co., Ltd. Semiconductor package with embedded heat-dissipating device
US7009297B1 (en) 2000-10-13 2006-03-07 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal particle
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
JP4505983B2 (ja) 2000-12-01 2010-07-21 日本電気株式会社 半導体装置
JP3798620B2 (ja) 2000-12-04 2006-07-19 富士通株式会社 半導体装置の製造方法
US6734539B2 (en) 2000-12-27 2004-05-11 Lucent Technologies Inc. Stacked module package
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
KR100393102B1 (ko) 2000-12-29 2003-07-31 앰코 테크놀로지 코리아 주식회사 스택형 반도체패키지
AUPR244801A0 (en) 2001-01-10 2001-02-01 Silverbrook Research Pty Ltd A method and apparatus (WSM01)
US6388322B1 (en) 2001-01-17 2002-05-14 Aralight, Inc. Article comprising a mechanically compliant bump
US6653170B1 (en) 2001-02-06 2003-11-25 Charles W. C. Lin Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit
US6472743B2 (en) 2001-02-22 2002-10-29 Siliconware Precision Industries, Co., Ltd. Semiconductor package with heat dissipating structure
KR100401020B1 (ko) 2001-03-09 2003-10-08 앰코 테크놀로지 코리아 주식회사 반도체칩의 스택킹 구조 및 이를 이용한 반도체패키지
JP2002280414A (ja) 2001-03-22 2002-09-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2002289769A (ja) 2001-03-26 2002-10-04 Matsushita Electric Ind Co Ltd 積層型半導体装置およびその製造方法
SG108245A1 (en) 2001-03-30 2005-01-28 Micron Technology Inc Ball grid array interposer, packages and methods
US6874910B2 (en) 2001-04-12 2005-04-05 Matsushita Electric Works, Ltd. Light source device using LED, and method of producing same
US7115986B2 (en) 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
US6825552B2 (en) 2001-05-09 2004-11-30 Tessera, Inc. Connection components with anisotropic conductive material interconnection
TW544826B (en) 2001-05-18 2003-08-01 Nec Electronics Corp Flip-chip-type semiconductor device and manufacturing method thereof
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
US6900528B2 (en) 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package
US6754407B2 (en) 2001-06-26 2004-06-22 Intel Corporation Flip-chip package integrating optical and electrical devices and coupling to a waveguide on a board
US20030006494A1 (en) 2001-07-03 2003-01-09 Lee Sang Ho Thin profile stackable semiconductor package and method for manufacturing
US6486545B1 (en) 2001-07-26 2002-11-26 Amkor Technology, Inc. Pre-drilled ball grid array package
US6451626B1 (en) 2001-07-27 2002-09-17 Charles W.C. Lin Three-dimensional stacked semiconductor package
US6765287B1 (en) 2001-07-27 2004-07-20 Charles W. C. Lin Three-dimensional stacked semiconductor package
JP4023159B2 (ja) 2001-07-31 2007-12-19 ソニー株式会社 半導体装置の製造方法及び積層半導体装置の製造方法
US6550666B2 (en) 2001-08-21 2003-04-22 Advanpack Solutions Pte Ltd Method for forming a flip chip on leadframe semiconductor package
US7605479B2 (en) 2001-08-22 2009-10-20 Tessera, Inc. Stacked chip assembly with encapsulant layer
US7176506B2 (en) 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
US6864166B1 (en) 2001-08-29 2005-03-08 Micron Technology, Inc. Method of manufacturing wire bonded microelectronic device assemblies
SG117395A1 (en) 2001-08-29 2005-12-29 Micron Technology Inc Wire bonded microelectronic device assemblies and methods of manufacturing same
US6787926B2 (en) 2001-09-05 2004-09-07 Taiwan Semiconductor Manufacturing Co., Ltd Wire stitch bond on an integrated circuit bond pad and method of making the same
US20030057544A1 (en) 2001-09-13 2003-03-27 Nathan Richard J. Integrated assembly protocol
US6476506B1 (en) 2001-09-28 2002-11-05 Motorola, Inc. Packaged semiconductor with multiple rows of bond pads and method therefor
US6977440B2 (en) 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
DE10297316T5 (de) 2001-10-09 2004-12-09 Tessera, Inc., San Jose Gestapelte Baugruppen
JP2003122611A (ja) 2001-10-11 2003-04-25 Oki Electric Ind Co Ltd データ提供方法及びサーバ装置
JP4257771B2 (ja) 2001-10-16 2009-04-22 シンジーテック株式会社 導電性ブレード
JP3875077B2 (ja) 2001-11-16 2007-01-31 富士通株式会社 電子デバイス及びデバイス接続方法
US20030094666A1 (en) 2001-11-16 2003-05-22 R-Tec Corporation Interposer
JP2003174124A (ja) 2001-12-04 2003-06-20 Sainekkusu:Kk 半導体装置の外部電極形成方法
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
JP2003197668A (ja) 2001-12-10 2003-07-11 Senmao Koochii Kofun Yugenkoshi 半導体パッケージ用のボンディングワイヤ及びその製造方法
JP3507059B2 (ja) 2002-06-27 2004-03-15 沖電気工業株式会社 積層マルチチップパッケージ
JP2003197669A (ja) 2001-12-28 2003-07-11 Seiko Epson Corp ボンディング方法及びボンディング装置
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
TW548816B (en) 2002-01-23 2003-08-21 Via Tech Inc Formation method of conductor pillar
JP3935370B2 (ja) 2002-02-19 2007-06-20 セイコーエプソン株式会社 バンプ付き半導体素子の製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
SG115456A1 (en) 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
DE10209922A1 (de) 2002-03-07 2003-10-02 Infineon Technologies Ag Elektronisches Modul, Nutzen mit zu vereinzelnden elektronischen Modulen und Verfahren zu deren Herstellung
US6653723B2 (en) 2002-03-09 2003-11-25 Fujitsu Limited System for providing an open-cavity low profile encapsulated semiconductor package
KR100452819B1 (ko) 2002-03-18 2004-10-15 삼성전기주식회사 칩 패키지 및 그 제조방법
US6979230B2 (en) 2002-03-20 2005-12-27 Gabe Cherian Light socket
JP2003318327A (ja) 2002-04-22 2003-11-07 Mitsui Chemicals Inc プリント配線板および積層パッケージ
US7323767B2 (en) 2002-04-25 2008-01-29 Micron Technology, Inc. Standoffs for centralizing internals in packaging process
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US7078822B2 (en) 2002-06-25 2006-07-18 Intel Corporation Microelectronic device interconnects
US6906415B2 (en) 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
JP4601892B2 (ja) 2002-07-04 2010-12-22 ラムバス・インコーポレーテッド 半導体装置および半導体チップのバンプ製造方法
JP2004047702A (ja) 2002-07-11 2004-02-12 Toshiba Corp 半導体装置積層モジュール
US6756252B2 (en) 2002-07-17 2004-06-29 Texas Instrument Incorporated Multilayer laser trim interconnect method
US6987032B1 (en) 2002-07-19 2006-01-17 Asat Ltd. Ball grid array package and process for manufacturing same
TW549592U (en) 2002-08-16 2003-08-21 Via Tech Inc Integrated circuit package with a balanced-part structure
AU2003265417A1 (en) 2002-08-16 2004-03-03 Tessera, Inc. Microelectronic packages with self-aligning features
US6964881B2 (en) 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
JP3765778B2 (ja) 2002-08-29 2006-04-12 ローム株式会社 ワイヤボンディング用キャピラリ及びこれを用いたワイヤボンディング方法
JP2004095799A (ja) 2002-08-30 2004-03-25 Toshiba Corp 半導体装置およびその製造方法
US20040041757A1 (en) 2002-09-04 2004-03-04 Ming-Hsiang Yang Light emitting diode display module with high heat-dispersion and the substrate thereof
US7294928B2 (en) 2002-09-06 2007-11-13 Tessera, Inc. Components, methods and assemblies for stacked packages
US7246431B2 (en) 2002-09-06 2007-07-24 Tessera, Inc. Methods of making microelectronic packages including folded substrates
US7071547B2 (en) 2002-09-11 2006-07-04 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
US7229906B2 (en) 2002-09-19 2007-06-12 Kulicke And Soffa Industries, Inc. Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine
CN100380636C (zh) 2002-09-30 2008-04-09 先进互连技术有限公司 用于整体成型组件的热增强封装及其制造方法
US7045884B2 (en) 2002-10-04 2006-05-16 International Rectifier Corporation Semiconductor device package
US6906416B2 (en) 2002-10-08 2005-06-14 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package
US6989122B1 (en) 2002-10-17 2006-01-24 National Semiconductor Corporation Techniques for manufacturing flash-free contacts on a semiconductor package
TW567601B (en) 2002-10-18 2003-12-21 Siliconware Precision Industries Co Ltd Module device of stacked semiconductor package and method for fabricating the same
TWI221664B (en) 2002-11-07 2004-10-01 Via Tech Inc Structure of chip package and process thereof
JP2004172157A (ja) 2002-11-15 2004-06-17 Shinko Electric Ind Co Ltd 半導体パッケージおよびパッケージスタック半導体装置
US20050176233A1 (en) 2002-11-15 2005-08-11 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
JP2004172477A (ja) 2002-11-21 2004-06-17 Kaijo Corp ワイヤループ形状、そのワイヤループ形状を備えた半導体装置、ワイヤボンディング方法及び半導体製造装置
JP4464041B2 (ja) 2002-12-13 2010-05-19 キヤノン株式会社 柱状構造体、柱状構造体を有する電極、及びこれらの作製方法
JP2004200316A (ja) 2002-12-17 2004-07-15 Shinko Electric Ind Co Ltd 半導体装置
US20050161814A1 (en) 2002-12-27 2005-07-28 Fujitsu Limited Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus
KR100621991B1 (ko) 2003-01-03 2006-09-13 삼성전자주식회사 칩 스케일 적층 패키지
JP2004221257A (ja) 2003-01-14 2004-08-05 Seiko Epson Corp ワイヤボンディング方法及びワイヤボンディング装置
WO2004077525A2 (en) 2003-02-25 2004-09-10 Tessera, Inc. Ball grid array with bumps
TW583757B (en) 2003-02-26 2004-04-11 Advanced Semiconductor Eng A structure of a flip-chip package and a process thereof
US20040217471A1 (en) 2003-02-27 2004-11-04 Tessera, Inc. Component and assemblies with ends offset downwardly
JP3885747B2 (ja) 2003-03-13 2007-02-28 株式会社デンソー ワイヤボンディング方法
JP2004343030A (ja) 2003-03-31 2004-12-02 North:Kk 配線回路基板とその製造方法とその配線回路基板を備えた回路モジュール
JP2004319892A (ja) 2003-04-18 2004-11-11 Renesas Technology Corp 半導体装置の製造方法
JP2004327855A (ja) 2003-04-25 2004-11-18 Nec Electronics Corp 半導体装置およびその製造方法
JP4199588B2 (ja) 2003-04-25 2008-12-17 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路基板の製造方法、及び、この配線回路基板を用いた半導体集積回路装置の製造方法
DE10320646A1 (de) 2003-05-07 2004-09-16 Infineon Technologies Ag Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben
JP4145730B2 (ja) 2003-06-17 2008-09-03 松下電器産業株式会社 半導体内蔵モジュール
US20040262728A1 (en) 2003-06-30 2004-12-30 Sterrett Terry L. Modular device assemblies
KR100604821B1 (ko) 2003-06-30 2006-07-26 삼성전자주식회사 적층형 볼 그리드 어레이 패키지 및 그 제조방법
JP2005033141A (ja) 2003-07-11 2005-02-03 Sony Corp 半導体装置及びその製造方法、疑似ウェーハ及びその製造方法、並びに半導体装置の実装構造
US7227095B2 (en) 2003-08-06 2007-06-05 Micron Technology, Inc. Wire bonders and methods of wire-bonding
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
KR100546374B1 (ko) 2003-08-28 2006-01-26 삼성전자주식회사 센터 패드를 갖는 적층형 반도체 패키지 및 그 제조방법
JP2005093551A (ja) 2003-09-12 2005-04-07 Genusion:Kk 半導体装置のパッケージ構造およびパッケージ化方法
US7372151B1 (en) 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
JP3999720B2 (ja) 2003-09-16 2007-10-31 沖電気工業株式会社 半導体装置およびその製造方法
US7061096B2 (en) 2003-09-24 2006-06-13 Silicon Pipe, Inc. Multi-surface IC packaging structures and methods for their manufacture
WO2005031861A1 (en) 2003-09-26 2005-04-07 Tessera, Inc. Structure and method of making capped chips including a flowable conductive medium
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
US7495179B2 (en) * 2003-10-06 2009-02-24 Tessera, Inc. Components with posts and pads
JP4272968B2 (ja) 2003-10-16 2009-06-03 エルピーダメモリ株式会社 半導体装置および半導体チップ制御方法
JP4167965B2 (ja) 2003-11-07 2008-10-22 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路用部材の製造方法
KR100564585B1 (ko) 2003-11-13 2006-03-28 삼성전자주식회사 이중 스택된 ｂｇａ 패키지 및 다중 스택된 ｂｇａ 패키지
TWI227555B (en) 2003-11-17 2005-02-01 Advanced Semiconductor Eng Structure of chip package and the process thereof
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP2005183923A (ja) 2003-11-28 2005-07-07 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US7345361B2 (en) 2003-12-04 2008-03-18 Intel Corporation Stackable integrated circuit packaging
JP2005175019A (ja) 2003-12-08 2005-06-30 Sharp Corp 半導体装置及び積層型半導体装置
JP5197961B2 (ja) * 2003-12-17 2013-05-15 スタッツ・チップパック・インコーポレイテッド マルチチップパッケージモジュールおよびその製造方法
DE10360708B4 (de) 2003-12-19 2008-04-10 Infineon Technologies Ag Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben
JP4334996B2 (ja) 2003-12-24 2009-09-30 株式会社フジクラ 多層配線板用基材、両面配線板およびそれらの製造方法
US7495644B2 (en) 2003-12-26 2009-02-24 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing display device
JP3917133B2 (ja) 2003-12-26 2007-05-23 株式会社東芝 インターフェイスモジュール付ｌｓｉパッケージ及びそれに用いるインターポーザ、インターフェイスモジュール、接続モニタ回路、信号処理ｌｓｉ
US6900530B1 (en) 2003-12-29 2005-05-31 Ramtek Technology, Inc. Stacked IC
US6917098B1 (en) 2003-12-29 2005-07-12 Texas Instruments Incorporated Three-level leadframe for no-lead packages
US8207604B2 (en) 2003-12-30 2012-06-26 Tessera, Inc. Microelectronic package comprising offset conductive posts on compliant layer
US7709968B2 (en) 2003-12-30 2010-05-04 Tessera, Inc. Micro pin grid array with pin motion isolation
US7176043B2 (en) 2003-12-30 2007-02-13 Tessera, Inc. Microelectronic packages and methods therefor
JP2005203497A (ja) 2004-01-14 2005-07-28 Toshiba Corp 半導体装置およびその製造方法
US20050173807A1 (en) 2004-02-05 2005-08-11 Jianbai Zhu High density vertically stacked semiconductor device
US7198987B1 (en) 2004-03-04 2007-04-03 Skyworks Solutions, Inc. Overmolded semiconductor package with an integrated EMI and RFI shield
US8399972B2 (en) 2004-03-04 2013-03-19 Skyworks Solutions, Inc. Overmolded semiconductor package with a wirebond cage for EMI shielding
US7095105B2 (en) 2004-03-23 2006-08-22 Texas Instruments Incorporated Vertically stacked semiconductor device
JP4484035B2 (ja) 2004-04-06 2010-06-16 セイコーエプソン株式会社 半導体装置の製造方法
US8092734B2 (en) 2004-05-13 2012-01-10 Aptina Imaging Corporation Covers for microelectronic imagers and methods for wafer-level packaging of microelectronics imagers
US7629695B2 (en) 2004-05-20 2009-12-08 Kabushiki Kaisha Toshiba Stacked electronic component and manufacturing method thereof
US6962864B1 (en) 2004-05-26 2005-11-08 National Chung Cheng University Wire-bonding method for chips with copper interconnects by introducing a thin layer
US7233057B2 (en) 2004-05-28 2007-06-19 Nokia Corporation Integrated circuit package with optimized mold shape
TWI255022B (en) 2004-05-31 2006-05-11 Via Tech Inc Circuit carrier and manufacturing process thereof
US7453157B2 (en) 2004-06-25 2008-11-18 Tessera, Inc. Microelectronic packages and methods therefor
TWI250596B (en) 2004-07-23 2006-03-01 Ind Tech Res Inst Wafer-level chip scale packaging method
JP3956965B2 (ja) 2004-09-07 2007-08-08 日立エーアイシー株式会社 チップ部品型発光装置及びそのための配線基板
US7290448B2 (en) 2004-09-10 2007-11-06 Yamaha Corporation Physical quantity sensor, lead frame, and manufacturing method therefor
CN1755929B (zh) 2004-09-28 2010-08-18 飞思卡尔半导体（中国）有限公司 形成半导体封装及其结构的方法
JP4385329B2 (ja) 2004-10-08 2009-12-16 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
US7595548B2 (en) 2004-10-08 2009-09-29 Yamaha Corporation Physical quantity sensor and manufacturing method therefor
JP4671802B2 (ja) 2004-10-18 2011-04-20 富士通株式会社 めっき方法、半導体装置の製造方法及び回路基板の製造方法
US20060087013A1 (en) 2004-10-21 2006-04-27 Etron Technology, Inc. Stacked multiple integrated circuit die package assembly
US8646675B2 (en) 2004-11-02 2014-02-11 Hid Global Gmbh Laying apparatus, contact-making apparatus, movement system, laying and contact-making unit, production system, method for production and a transponder unit
US8525314B2 (en) 2004-11-03 2013-09-03 Tessera, Inc. Stacked packaging improvements
TW200631111A (en) 2004-11-04 2006-09-01 Koninkl Philips Electronics Nv Nanotube-based circuit connection approach
US7750483B1 (en) 2004-11-10 2010-07-06 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal
US7268421B1 (en) 2004-11-10 2007-09-11 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond
JP4917257B2 (ja) 2004-11-12 2012-04-18 浜松ホトニクス株式会社 レーザ加工方法
KR100674926B1 (ko) 2004-12-08 2007-01-26 삼성전자주식회사 메모리 카드 및 그 제조 방법
US7301770B2 (en) 2004-12-10 2007-11-27 International Business Machines Corporation Cooling apparatus, cooled electronic module, and methods of fabrication thereof employing thermally conductive, wire-bonded pin fins
JP4504798B2 (ja) 2004-12-16 2010-07-14 パナソニック株式会社 多段構成半導体モジュール
KR100843137B1 (ko) 2004-12-27 2008-07-02 삼성전자주식회사 반도체 소자 패키지
JP2006186086A (ja) 2004-12-27 2006-07-13 Itoo:Kk プリント基板のはんだ付け方法およびブリッジ防止用ガイド板
DE102005006333B4 (de) 2005-02-10 2007-10-18 Infineon Technologies Ag Halbleiterbauteil mit mehreren Bondanschlüssen und gebondeten Kontaktelementen unterschiedlicher Metallzusammensetzung und Verfahren zur Herstellung desselben
DE102005006995B4 (de) 2005-02-15 2008-01-24 Infineon Technologies Ag Halbleiterbauteil mit Kunstoffgehäuse und Außenanschlüssen sowie Verfahren zur Herstellung desselben
KR100867038B1 (ko) 2005-03-02 2008-11-04 삼성전기주식회사 커패시터 내장형 인쇄회로기판 및 그 제조방법
KR100630741B1 (ko) 2005-03-04 2006-10-02 삼성전자주식회사 다중 몰딩에 의한 적층형 반도체 패키지 및 그 제조방법
US7939934B2 (en) 2005-03-16 2011-05-10 Tessera, Inc. Microelectronic packages and methods therefor
US20060216868A1 (en) 2005-03-25 2006-09-28 Advanced Semiconductor Engineering Inc. Package structure and fabrication thereof
US7582963B2 (en) 2005-03-29 2009-09-01 Texas Instruments Incorporated Vertically integrated system-in-a-package
US7371676B2 (en) 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
US7815323B2 (en) 2005-05-04 2010-10-19 Lang-Mekra North America, Llc Mirror stabilizer arm connector assembly
TWI284394B (en) 2005-05-12 2007-07-21 Advanced Semiconductor Eng Lid used in package structure and the package structure of having the same
JP2006324553A (ja) 2005-05-20 2006-11-30 Renesas Technology Corp 半導体装置及びその製造方法
US7528474B2 (en) 2005-05-31 2009-05-05 Stats Chippac Ltd. Stacked semiconductor package assembly having hollowed substrate
US7216794B2 (en) 2005-06-09 2007-05-15 Texas Instruments Incorporated Bond capillary design for ribbon wire bonding
JP4322844B2 (ja) 2005-06-10 2009-09-02 シャープ株式会社 半導体装置および積層型半導体装置
WO2007004137A2 (en) 2005-07-01 2007-01-11 Koninklijke Philips Electronics N.V. Electronic device
TWI294757B (en) 2005-07-06 2008-03-11 Delta Electronics Inc Circuit board with a through hole wire, and forming method thereof
US7476608B2 (en) 2005-07-14 2009-01-13 Hewlett-Packard Development Company, L.P. Electrically connecting substrate with electrical device
JP4787559B2 (ja) 2005-07-26 2011-10-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7355289B2 (en) * 2005-07-29 2008-04-08 Freescale Semiconductor, Inc. Packaged integrated circuit with enhanced thermal dissipation
TWI263313B (en) 2005-08-15 2006-10-01 Phoenix Prec Technology Corp Stack structure of semiconductor component embedded in supporting board
SG130055A1 (en) 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
SG130066A1 (en) 2005-08-26 2007-03-20 Micron Technology Inc Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
JP5522561B2 (ja) 2005-08-31 2014-06-18 マイクロン テクノロジー， インク． マイクロ電子デバイスパッケージ、積重ね型マイクロ電子デバイスパッケージ、およびマイクロ電子デバイスを製造する方法
US7675152B2 (en) 2005-09-01 2010-03-09 Texas Instruments Incorporated Package-on-package semiconductor assembly
US7485969B2 (en) 2005-09-01 2009-02-03 Micron Technology, Inc. Stacked microelectronic devices and methods for manufacturing microelectronic devices
US20070080360A1 (en) 2005-10-06 2007-04-12 Url Mirsky Microelectronic interconnect substrate and packaging techniques
KR101241650B1 (ko) 2005-10-19 2013-03-08 엘지이노텍 주식회사 엘이디 패키지
US7504716B2 (en) 2005-10-26 2009-03-17 Texas Instruments Incorporated Structure and method of molded QFN device suitable for miniaturization, multiple rows and stacking
US8810031B2 (en) 2005-10-26 2014-08-19 Industrial Technology Research Institute Wafer-to-wafer stack with supporting pedestal
JP2007123595A (ja) 2005-10-28 2007-05-17 Nec Corp 半導体装置及びその実装構造
TW200733272A (en) 2005-11-01 2007-09-01 Koninkl Philips Electronics Nv Methods of packaging a semiconductor die and die package formed by the methods
JP4530975B2 (ja) 2005-11-14 2010-08-25 株式会社新川 ワイヤボンディング方法
JP2007142042A (ja) 2005-11-16 2007-06-07 Sharp Corp 半導体パッケージとその製造方法，半導体モジュール，および電子機器
US7344917B2 (en) 2005-11-30 2008-03-18 Freescale Semiconductor, Inc. Method for packaging a semiconductor device
US7307348B2 (en) 2005-12-07 2007-12-11 Micron Technology, Inc. Semiconductor components having through wire interconnects (TWI)
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
JP4530984B2 (ja) 2005-12-28 2010-08-25 株式会社新川 ワイヤボンディング装置、ボンディング制御プログラム及びボンディング方法
US7378726B2 (en) 2005-12-28 2008-05-27 Intel Corporation Stacked packages with interconnecting pins
JP2007194436A (ja) 2006-01-19 2007-08-02 Elpida Memory Inc 半導体パッケージ、導電性ポスト付き基板、積層型半導体装置、半導体パッケージの製造方法及び積層型半導体装置の製造方法
US20070190747A1 (en) 2006-01-23 2007-08-16 Tessera Technologies Hungary Kft. Wafer level packaging to lidded chips
JP2007201254A (ja) 2006-01-27 2007-08-09 Ibiden Co Ltd 半導体素子内蔵基板、半導体素子内蔵型多層回路基板
JP2007208159A (ja) 2006-02-06 2007-08-16 Hitachi Ltd 半導体装置
SG135074A1 (en) 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
TWI295115B (en) 2006-02-13 2008-03-21 Ind Tech Res Inst Encapsulation and methods thereof
JP2007234845A (ja) 2006-03-01 2007-09-13 Nec Corp 半導体装置
US7876180B2 (en) 2006-03-09 2011-01-25 Kyocera Corporation Waveguide forming apparatus, dielectric waveguide forming apparatus, pin structure, and high frequency circuit
US7759782B2 (en) 2006-04-07 2010-07-20 Tessera, Inc. Substrate for a microelectronic package and method of fabricating thereof
US7390700B2 (en) 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
JP4821849B2 (ja) 2006-04-10 2011-11-24 株式会社村田製作所 複合基板及び複合基板の製造方法
JP5598787B2 (ja) 2006-04-17 2014-10-01 マイクロンメモリジャパン株式会社 積層型半導体装置の製造方法
US7659612B2 (en) 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
US7242081B1 (en) 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
US7910385B2 (en) * 2006-05-12 2011-03-22 Micron Technology, Inc. Method of fabricating microelectronic devices
DE102006022360B4 (de) 2006-05-12 2009-07-09 Infineon Technologies Ag Abschirmvorrichtung
US7780064B2 (en) 2006-06-02 2010-08-24 Asm Technology Singapore Pte Ltd Wire bonding method for forming low-loop profiles
JP4961848B2 (ja) 2006-06-12 2012-06-27 日本電気株式会社 金属ポストを有する配線基板、半導体装置及び半導体装置モジュールの製造方法
US20070290325A1 (en) 2006-06-16 2007-12-20 Lite-On Semiconductor Corporation Surface mounting structure and packaging method thereof
US7967062B2 (en) 2006-06-16 2011-06-28 International Business Machines Corporation Thermally conductive composite interface, cooled electronic assemblies employing the same, and methods of fabrication thereof
TWM303516U (en) 2006-06-23 2006-12-21 Advanced Connectek Inc Card connector
TWM306727U (en) 2006-06-26 2007-02-21 Hon Hai Prec Ind Co Ltd Electrical card connector
WO2008014633A1 (en) 2006-06-29 2008-02-07 Intel Corporation Apparatus, system, and method for wireless connection in integrated circuit packages
KR100792352B1 (ko) 2006-07-06 2008-01-08 삼성전기주식회사 패키지 온 패키지의 바텀기판 및 그 제조방법
US7612638B2 (en) 2006-07-14 2009-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Waveguides in integrated circuits
SG139573A1 (en) 2006-07-17 2008-02-29 Micron Technology Inc Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods
KR100800478B1 (ko) 2006-07-18 2008-02-04 삼성전자주식회사 적층형 반도체 패키지 및 그의 제조방법
US20080023805A1 (en) 2006-07-26 2008-01-31 Texas Instruments Incorporated Array-Processed Stacked Semiconductor Packages
JP5132101B2 (ja) 2006-07-27 2013-01-30 新光電気工業株式会社 スタックパッケージ構造体及びその製造に用いる単体パッケージと、それらの製造方法
US8048479B2 (en) 2006-08-01 2011-11-01 Qimonda Ag Method for placing material onto a target board by means of a transfer board
JP2008039502A (ja) 2006-08-03 2008-02-21 Alps Electric Co Ltd 接触子およびその製造方法
US7486525B2 (en) 2006-08-04 2009-02-03 International Business Machines Corporation Temporary chip attach carrier
KR100809696B1 (ko) 2006-08-08 2008-03-06 삼성전자주식회사 사이즈가 상이한 복수의 반도체 칩이 적층된 멀티 칩패키지 및 그 제조방법
US20080042265A1 (en) 2006-08-15 2008-02-21 Merilo Leo A Chip scale module package in bga semiconductor package
US7425758B2 (en) 2006-08-28 2008-09-16 Micron Technology, Inc. Metal core foldover package structures
US7560360B2 (en) 2006-08-30 2009-07-14 International Business Machines Corporation Methods for enhancing trench capacitance and trench capacitor
KR20080020069A (ko) 2006-08-30 2008-03-05 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR100891516B1 (ko) 2006-08-31 2009-04-06 주식회사 하이닉스반도체 적층 가능한 에프비지에이 타입 반도체 패키지와 이를이용한 적층 패키지
US7683460B2 (en) 2006-09-22 2010-03-23 Infineon Technologies Ag Module with a shielding and/or heat dissipating element
KR100770934B1 (ko) 2006-09-26 2007-10-26 삼성전자주식회사 반도체 패키지와 그를 이용한 반도체 시스템 패키지
TWI336502B (en) 2006-09-27 2011-01-21 Advanced Semiconductor Eng Semiconductor package and semiconductor device and the method of making the same
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
TWI312561B (en) 2006-10-27 2009-07-21 Advanced Semiconductor Eng Structure of package on package and method for fabricating the same
KR100817073B1 (ko) 2006-11-03 2008-03-26 삼성전자주식회사 휨방지용 보강부재가 기판에 연결된 반도체 칩 스택 패키지
US8193034B2 (en) 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
US8174119B2 (en) 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
WO2008065896A1 (fr) 2006-11-28 2008-06-05 Kyushu Institute Of Technology Procédé de fabrication d'un dispositif semi-conducteur ayant une structure d'électrode à double face et dispositif semi-conducteur fabriqué par le procédé
US7659617B2 (en) 2006-11-30 2010-02-09 Tessera, Inc. Substrate for a flexible microelectronic assembly and a method of fabricating thereof
US7537962B2 (en) 2006-12-22 2009-05-26 Stats Chippac Ltd. Method of fabricating a shielded stacked integrated circuit package system
JP2008166439A (ja) 2006-12-27 2008-07-17 Spansion Llc 半導体装置およびその製造方法
US8598717B2 (en) 2006-12-27 2013-12-03 Spansion Llc Semiconductor device and method for manufacturing the same
KR100757345B1 (ko) 2006-12-29 2007-09-10 삼성전자주식회사 플립 칩 패키지 및 그의 제조 방법
SG163530A1 (en) 2006-12-29 2010-08-30 United Test & Assembly Ct Lt Copper wire bonding on organic solderability preservative materials
US20080156518A1 (en) 2007-01-03 2008-07-03 Tessera, Inc. Alignment and cutting of microelectronic substrates
TWI332702B (en) 2007-01-09 2010-11-01 Advanced Semiconductor Eng Stackable semiconductor package and the method for making the same
JP5347222B2 (ja) 2007-01-10 2013-11-20 富士通株式会社 半導体装置の製造方法
US7719122B2 (en) 2007-01-11 2010-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. System-in-package packaging for minimizing bond wire contamination and yield loss
KR100827667B1 (ko) 2007-01-16 2008-05-07 삼성전자주식회사 기판 내에 반도체 칩을 갖는 반도체 패키지 및 이를제조하는 방법
JP4823089B2 (ja) 2007-01-31 2011-11-24 株式会社東芝 積層型半導体装置の製造方法
KR101057368B1 (ko) 2007-01-31 2011-08-18 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치 및 그 제조 방법
US8685792B2 (en) 2007-03-03 2014-04-01 Stats Chippac Ltd. Integrated circuit package system with interposer
CN101675516B (zh) 2007-03-05 2012-06-20 数字光学欧洲有限公司 具有通过过孔连接到前侧触头的后侧触头的芯片
US20080217708A1 (en) 2007-03-09 2008-09-11 Skyworks Solutions, Inc. Integrated passive cap in a system-in-package
JP5010316B2 (ja) 2007-03-16 2012-08-29 日本電気株式会社 金属ポストを有する配線基板、半導体装置
US7517733B2 (en) 2007-03-22 2009-04-14 Stats Chippac, Ltd. Leadframe design for QFN package with top terminal leads
WO2008117488A1 (ja) 2007-03-23 2008-10-02 Sanyo Electric Co., Ltd 半導体装置およびその製造方法
US8198716B2 (en) 2007-03-26 2012-06-12 Intel Corporation Die backside wire bond technology for single or stacked die package
JPWO2008120755A1 (ja) 2007-03-30 2010-07-15 日本電気株式会社 機能素子内蔵回路基板及びその製造方法、並びに電子機器
JP4926787B2 (ja) 2007-03-30 2012-05-09 アオイ電子株式会社 半導体装置の製造方法
US20080246126A1 (en) 2007-04-04 2008-10-09 Freescale Semiconductor, Inc. Stacked and shielded die packages with interconnects
US7589394B2 (en) 2007-04-10 2009-09-15 Ibiden Co., Ltd. Interposer
JP5003260B2 (ja) 2007-04-13 2012-08-15 日本電気株式会社 半導体装置およびその製造方法
US7994622B2 (en) 2007-04-16 2011-08-09 Tessera, Inc. Microelectronic packages having cavities for receiving microelectric elements
KR20080094251A (ko) 2007-04-19 2008-10-23 삼성전자주식회사 웨이퍼 레벨 패키지 및 그 제조방법
JP5601751B2 (ja) 2007-04-26 2014-10-08 スパンション エルエルシー 半導体装置
US20080280393A1 (en) 2007-05-09 2008-11-13 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for forming package structures
US20080284045A1 (en) 2007-05-18 2008-11-20 Texas Instruments Incorporated Method for Fabricating Array-Molded Package-On-Package
TWI371809B (en) 2007-06-04 2012-09-01 Advanced Semiconductor Eng Wafer structure and method for fabricating the same
US7872335B2 (en) 2007-06-08 2011-01-18 Broadcom Corporation Lead frame-BGA package with enhanced thermal performance and I/O counts
JP2008306128A (ja) 2007-06-11 2008-12-18 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
KR100865125B1 (ko) 2007-06-12 2008-10-24 삼성전기주식회사 반도체 패키지 및 그 제조방법
US7576415B2 (en) 2007-06-15 2009-08-18 Advanced Semiconductor Engineering, Inc. EMI shielded semiconductor package
US20080308305A1 (en) 2007-06-15 2008-12-18 Ngk Spark Plug Co., Ltd. Wiring substrate with reinforcing member
US7944034B2 (en) 2007-06-22 2011-05-17 Texas Instruments Incorporated Array molded package-on-package having redistribution lines
JP5179787B2 (ja) 2007-06-22 2013-04-10 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
US7911805B2 (en) 2007-06-29 2011-03-22 Tessera, Inc. Multilayer wiring element having pin interface
SG148901A1 (en) 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
KR20090007120A (ko) 2007-07-13 2009-01-16 삼성전자주식회사 봉지부를 통하여 재배선을 달성하는 웨이퍼 레벨 적층형패키지 및 그 제조방법
US7781877B2 (en) 2007-08-07 2010-08-24 Micron Technology, Inc. Packaged integrated circuit devices with through-body conductive vias, and methods of making same
JP2009044110A (ja) 2007-08-13 2009-02-26 Elpida Memory Inc 半導体装置及びその製造方法
SG150396A1 (en) 2007-08-16 2009-03-30 Micron Technology Inc Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
KR101329355B1 (ko) 2007-08-31 2013-11-20 삼성전자주식회사 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치
KR101365621B1 (ko) 2007-09-04 2014-02-24 서울반도체 주식회사 열 방출 슬러그들을 갖는 발광 다이오드 패키지
JP2009064966A (ja) 2007-09-06 2009-03-26 Shinko Electric Ind Co Ltd 多層配線基板及びその製造方法ならびに半導体装置
US7808439B2 (en) 2007-09-07 2010-10-05 University Of Tennessee Reserch Foundation Substrate integrated waveguide antenna array
US9330945B2 (en) 2007-09-18 2016-05-03 Stats Chippac Ltd. Integrated circuit package system with multi-chip module
US8039960B2 (en) 2007-09-21 2011-10-18 Stats Chippac, Ltd. Solder bump with inner core pillar in semiconductor package
KR100902128B1 (ko) 2007-09-28 2009-06-09 삼성전기주식회사 방열 인쇄회로기판 및 반도체 칩 패키지
EP2206145A4 (en) 2007-09-28 2012-03-28 Tessera Inc FLIP-CHIP CONNECTION WITH DOUBLE POSTS
JP2009088254A (ja) 2007-09-28 2009-04-23 Toshiba Corp 電子部品パッケージ及び電子部品パッケージの製造方法
KR20090033605A (ko) * 2007-10-01 2009-04-06 삼성전자주식회사 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US20090091009A1 (en) 2007-10-03 2009-04-09 Corisis David J Stackable integrated circuit package
US8008183B2 (en) 2007-10-04 2011-08-30 Texas Instruments Incorporated Dual capillary IC wirebonding
US7834464B2 (en) 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
TWI389220B (zh) 2007-10-22 2013-03-11 矽品精密工業股份有限公司 半導體封裝件及其製法
FR2923081B1 (fr) 2007-10-26 2009-12-11 3D Plus Procede d'interconnexion verticale de modules electroniques 3d par des vias.
GB0721957D0 (en) 2007-11-08 2007-12-19 Photonstar Led Ltd Ultra high thermal performance packaging for optoelectronics devices
JP2009123863A (ja) 2007-11-14 2009-06-04 Tessera Interconnect Materials Inc バンプ構造形成方法及びバンプ構造
WO2009067556A2 (en) 2007-11-19 2009-05-28 Nexxus Lighting, Inc. Apparatus and methods for thermal management of light emitting diodes
US20090127686A1 (en) 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
JP2009135398A (ja) 2007-11-29 2009-06-18 Ibiden Co Ltd 組合せ基板
KR100886100B1 (ko) 2007-11-29 2009-02-27 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US7902644B2 (en) 2007-12-07 2011-03-08 Stats Chippac Ltd. Integrated circuit package system for electromagnetic isolation
US7964956B1 (en) 2007-12-10 2011-06-21 Oracle America, Inc. Circuit packaging and connectivity
US7696631B2 (en) 2007-12-10 2010-04-13 International Business Machines Corporation Wire bonding personalization and discrete component attachment on wirebond pads
US8390117B2 (en) 2007-12-11 2013-03-05 Panasonic Corporation Semiconductor device and method of manufacturing the same
US7706144B2 (en) 2007-12-17 2010-04-27 Lynch Thomas W Heat dissipation system and related method
JP2009158593A (ja) 2007-12-25 2009-07-16 Tessera Interconnect Materials Inc バンプ構造およびその製造方法
US20090170241A1 (en) 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
US20090166873A1 (en) 2007-12-27 2009-07-02 Advanced Chip Engineering Technology Inc. Inter-connecting structure for semiconductor device package and method of the same
JP4989614B2 (ja) 2007-12-28 2012-08-01 サムソン エルイーディー カンパニーリミテッド． 高出力ｌｅｄパッケージの製造方法
WO2009096950A1 (en) 2008-01-30 2009-08-06 Kulicke And Soffa Industries, Inc. Wire loop and method of forming the wire loop
US20090194829A1 (en) 2008-01-31 2009-08-06 Shine Chung MEMS Packaging Including Integrated Circuit Dies
US8120186B2 (en) 2008-02-15 2012-02-21 Qimonda Ag Integrated circuit and method
US8258015B2 (en) 2008-02-22 2012-09-04 Stats Chippac Ltd. Integrated circuit package system with penetrable film adhesive
US7956456B2 (en) 2008-02-27 2011-06-07 Texas Instruments Incorporated Thermal interface material design for enhanced thermal performance and improved package structural integrity
US8018065B2 (en) 2008-02-28 2011-09-13 Atmel Corporation Wafer-level integrated circuit package with top and bottom side electrical connections
US7919871B2 (en) 2008-03-21 2011-04-05 Stats Chippac Ltd. Integrated circuit package system for stackable devices
KR101501739B1 (ko) 2008-03-21 2015-03-11 삼성전자주식회사 반도체 패키지 제조 방법
US8525214B2 (en) 2008-03-25 2013-09-03 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader with thermal via
US8072079B2 (en) 2008-03-27 2011-12-06 Stats Chippac, Ltd. Through hole vias at saw streets including protrusions or recesses for interconnection
CN101978490B (zh) 2008-03-31 2012-10-17 株式会社村田制作所 电子元器件组件及该电子元器件组件的制造方法
JP5043743B2 (ja) 2008-04-18 2012-10-10 ラピスセミコンダクタ株式会社 半導体装置の製造方法
US7741156B2 (en) 2008-05-27 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming through vias with reflowed conductive material
KR20090123680A (ko) 2008-05-28 2009-12-02 주식회사 하이닉스반도체 적층 반도체 패키지
US8093704B2 (en) 2008-06-03 2012-01-10 Intel Corporation Package on package using a bump-less build up layer (BBUL) package
US8021907B2 (en) 2008-06-09 2011-09-20 Stats Chippac, Ltd. Method and apparatus for thermally enhanced semiconductor package
CN102067310B (zh) 2008-06-16 2013-08-21 泰塞拉公司 带有边缘触头的晶片级芯片规模封装的堆叠及其制造方法
US7932170B1 (en) 2008-06-23 2011-04-26 Amkor Technology, Inc. Flip chip bump structure and fabrication method
DE102008048420A1 (de) 2008-06-27 2010-01-28 Qimonda Ag Chip-Anordnung und Verfahren zum Herstellen einer Chip-Anordnung
US7969009B2 (en) 2008-06-30 2011-06-28 Qualcomm Incorporated Through silicon via bridge interconnect
TWI473553B (zh) 2008-07-03 2015-02-11 Advanced Semiconductor Eng 晶片封裝結構
US7859033B2 (en) 2008-07-09 2010-12-28 Eastman Kodak Company Wafer level processing for backside illuminated sensors
JP5339800B2 (ja) 2008-07-10 2013-11-13 三菱電機株式会社 半導体装置の製造方法
TWI372453B (en) 2008-09-01 2012-09-11 Advanced Semiconductor Eng Copper bonding wire, wire bonding structure and method for processing and bonding a wire
TWI573201B (zh) 2008-07-18 2017-03-01 聯測總部私人有限公司 封裝結構性元件
US8923004B2 (en) * 2008-07-31 2014-12-30 Micron Technology, Inc. Microelectronic packages with small footprints and associated methods of manufacturing
WO2010014103A1 (en) 2008-07-31 2010-02-04 Skyworks Solutions, Inc. Semiconductor package with integrated interference shielding and method of manufacture therof
US8004093B2 (en) 2008-08-01 2011-08-23 Stats Chippac Ltd. Integrated circuit package stacking system
US7800810B2 (en) 2008-08-06 2010-09-21 Spatial Photonics, Inc. Packaging and testing of multiple MEMS devices on a wafer
TW201007924A (en) 2008-08-07 2010-02-16 Advanced Semiconductor Eng Chip package structure
US20100044860A1 (en) 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
KR100997793B1 (ko) 2008-09-01 2010-12-02 주식회사 하이닉스반도체 반도체 패키지 및 이의 제조 방법
KR20100033012A (ko) 2008-09-19 2010-03-29 주식회사 하이닉스반도체 반도체 패키지 및 이를 갖는 적층 반도체 패키지
US7842541B1 (en) 2008-09-24 2010-11-30 Amkor Technology, Inc. Ultra thin package and fabrication method
US8237257B2 (en) 2008-09-25 2012-08-07 King Dragon International Inc. Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same
US8063475B2 (en) 2008-09-26 2011-11-22 Stats Chippac Ltd. Semiconductor package system with through silicon via interposer
WO2010041630A1 (ja) 2008-10-10 2010-04-15 日本電気株式会社 半導体装置及びその製造方法
JP5185062B2 (ja) 2008-10-21 2013-04-17 パナソニック株式会社 積層型半導体装置及び電子機器
MY149251A (en) 2008-10-23 2013-07-31 Carsem M Sdn Bhd Wafer-level package using stud bump coated with solder
KR101461630B1 (ko) 2008-11-06 2014-11-20 삼성전자주식회사 실장 높이는 축소되나, 솔더 접합 신뢰도는 개선되는 웨이퍼 레벨 칩 온 칩 패키지와, 패키지 온 패키지 및 그 제조방법
TW201023308A (en) 2008-12-01 2010-06-16 Advanced Semiconductor Eng Package-on-package device, semiconductor package and method for manufacturing the same
KR101011863B1 (ko) 2008-12-02 2011-01-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
KR101015651B1 (ko) 2008-12-05 2011-02-22 삼성전기주식회사 칩 내장 인쇄회로기판 및 그 제조방법
JP2010135671A (ja) 2008-12-08 2010-06-17 Panasonic Corp 半導体装置及びその製造方法
US7642128B1 (en) 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US7898083B2 (en) 2008-12-17 2011-03-01 Texas Instruments Incorporated Method for low stress flip-chip assembly of fine-pitch semiconductor devices
US8012797B2 (en) 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
TWI499024B (zh) 2009-01-07 2015-09-01 Advanced Semiconductor Eng 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
JP2010199528A (ja) 2009-01-27 2010-09-09 Tatsuta System Electronics Kk ボンディングワイヤ
JP2010177597A (ja) 2009-01-30 2010-08-12 Sanyo Electric Co Ltd 半導体モジュールおよび携帯機器
US20100200981A1 (en) 2009-02-09 2010-08-12 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
US9142586B2 (en) 2009-02-24 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for backside illuminated image sensor
WO2010101163A1 (ja) 2009-03-04 2010-09-10 日本電気株式会社 機能素子内蔵基板及びそれを用いた電子デバイス
JP2010206007A (ja) 2009-03-04 2010-09-16 Nec Corp 半導体装置及びその製造方法
US8115283B1 (en) 2009-07-14 2012-02-14 Amkor Technology, Inc. Reversible top/bottom MEMS package
US8106498B2 (en) 2009-03-05 2012-01-31 Stats Chippac Ltd. Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof
DE102009001461A1 (de) 2009-03-11 2010-09-16 Robert Bosch Gmbh Verfahren zur Herstellung einer elektronischen Baugruppe
US8258010B2 (en) 2009-03-17 2012-09-04 Stats Chippac, Ltd. Making a semiconductor device having conductive through organic vias
US20100244276A1 (en) 2009-03-25 2010-09-30 Lsi Corporation Three-dimensional electronics package
US20110068478A1 (en) 2009-03-26 2011-03-24 Reza Argenty Pagaila Integrated circuit packaging system with package stacking and method of manufacture thereof
US8194411B2 (en) 2009-03-31 2012-06-05 Hong Kong Applied Science and Technology Research Institute Co. Ltd Electronic package with stacked modules with channels passing through metal layers of the modules
US8053814B2 (en) 2009-04-08 2011-11-08 International Business Machines Corporation On-chip embedded thermal antenna for chip cooling
JP2010251483A (ja) 2009-04-14 2010-11-04 Renesas Electronics Corp 半導体装置およびその製造方法
US8039316B2 (en) 2009-04-14 2011-10-18 Stats Chippac Ltd. Integrated circuit packaging system with stacked integrated circuit and heat spreader with openings and method of manufacture thereof
US20100289142A1 (en) 2009-05-15 2010-11-18 Il Kwon Shim Integrated circuit packaging system with coin bonded interconnects and method of manufacture thereof
US8020290B2 (en) 2009-06-14 2011-09-20 Jayna Sheats Processes for IC fabrication
TWI379367B (en) 2009-06-15 2012-12-11 Kun Yuan Technology Co Ltd Chip packaging method and structure thereof
US20120153444A1 (en) 2009-06-18 2012-06-21 Rohm Co., Ltd Semiconductor device
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
JP5214554B2 (ja) 2009-07-30 2013-06-19 ラピスセミコンダクタ株式会社 半導体チップ内蔵パッケージ及びその製造方法、並びに、パッケージ・オン・パッケージ型半導体装置及びその製造方法
US8183678B2 (en) 2009-08-04 2012-05-22 Amkor Technology Korea, Inc. Semiconductor device having an interposer
US20110209908A1 (en) 2009-08-06 2011-09-01 Advanced Chip Engineering Technology Inc. Conductor package structure and method of the same
KR101124102B1 (ko) 2009-08-24 2012-03-21 삼성전기주식회사 발광 소자 패키지용 기판 및 이를 포함하는 발광 소자 패키지
EP2290686A3 (en) 2009-08-28 2011-04-20 STMicroelectronics S.r.l. Method to perform electrical testing and assembly of electronic devices
US7923304B2 (en) 2009-09-10 2011-04-12 Stats Chippac Ltd. Integrated circuit packaging system with conductive pillars and method of manufacture thereof
US8264091B2 (en) 2009-09-21 2012-09-11 Stats Chippac Ltd. Integrated circuit packaging system with encapsulated via and method of manufacture thereof
US8008121B2 (en) 2009-11-04 2011-08-30 Stats Chippac, Ltd. Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
US8390108B2 (en) 2009-12-16 2013-03-05 Stats Chippac Ltd. Integrated circuit packaging system with stacking interconnect and method of manufacture thereof
US8169065B2 (en) 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
TW201123387A (en) 2009-12-25 2011-07-01 xiang-hua Wang Thermal-electric separated metal PCB with a chip carrier.
TWI392066B (zh) 2009-12-28 2013-04-01 矽品精密工業股份有限公司 封裝結構及其製法
US8987830B2 (en) * 2010-01-12 2015-03-24 Marvell World Trade Ltd. Attaching passive components to a semiconductor package
JP5550369B2 (ja) 2010-02-03 2014-07-16 新日鉄住金マテリアルズ株式会社 半導体用銅ボンディングワイヤとその接合構造
JP2011166051A (ja) 2010-02-15 2011-08-25 Panasonic Corp 半導体装置及び半導体装置の製造方法
US7990711B1 (en) 2010-02-24 2011-08-02 International Business Machines Corporation Double-face heat removal of vertically integrated chip-stacks utilizing combined symmetric silicon carrier fluid cavity and micro-channel cold plate
US9496152B2 (en) 2010-03-12 2016-11-15 STATS ChipPAC Pte. Ltd. Carrier system with multi-tier conductive posts and method of manufacture thereof
US7928552B1 (en) 2010-03-12 2011-04-19 Stats Chippac Ltd. Integrated circuit packaging system with multi-tier conductive interconnects and method of manufacture thereof
KR101667656B1 (ko) 2010-03-24 2016-10-20 삼성전자주식회사 패키지-온-패키지 형성방법
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
CN102214631A (zh) 2010-04-09 2011-10-12 飞思卡尔半导体公司 用于半导体装置的引线框
US8564141B2 (en) 2010-05-06 2013-10-22 SK Hynix Inc. Chip unit and stack package having the same
US8558392B2 (en) 2010-05-14 2013-10-15 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant
US8288854B2 (en) 2010-05-19 2012-10-16 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for making the same
US8217502B2 (en) 2010-06-08 2012-07-10 Stats Chippac Ltd. Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof
US20120001336A1 (en) 2010-07-02 2012-01-05 Texas Instruments Incorporated Corrosion-resistant copper-to-aluminum bonds
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
KR20120007839A (ko) 2010-07-15 2012-01-25 삼성전자주식회사 적층형 반도체 패키지의 제조방법
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
JP5713598B2 (ja) 2010-07-20 2015-05-07 新光電気工業株式会社 ソケット及びその製造方法
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
KR101683814B1 (ko) 2010-07-26 2016-12-08 삼성전자주식회사 관통 전극을 구비하는 반도체 장치
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8304900B2 (en) 2010-08-11 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with stacked lead and method of manufacture thereof
US8076184B1 (en) 2010-08-16 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die
US8518746B2 (en) 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
US8354297B2 (en) 2010-09-03 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die
US8080445B1 (en) 2010-09-07 2011-12-20 Stats Chippac, Ltd. Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers
US20120063090A1 (en) 2010-09-09 2012-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling mechanism for stacked die package and method of manufacturing the same
US8409922B2 (en) 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
KR20120028484A (ko) * 2010-09-15 2012-03-23 삼성전자주식회사 모바일 기기에 채용하기 적합한 복합형 반도체 장치
US8415704B2 (en) 2010-09-22 2013-04-09 Ut-Battelle, Llc Close-packed array of light emitting devices
US8349735B2 (en) 2010-09-22 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming conductive TSV with insulating annular ring
US9224647B2 (en) 2010-09-24 2015-12-29 Stats Chippac, Ltd. Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
JP5616739B2 (ja) 2010-10-01 2014-10-29 新日鉄住金マテリアルズ株式会社 複層銅ボンディングワイヤの接合構造
US20120080787A1 (en) 2010-10-05 2012-04-05 Qualcomm Incorporated Electronic Package and Method of Making an Electronic Package
CN102024782B (zh) 2010-10-12 2012-07-25 北京大学 三维垂直互联结构及其制作方法
US8618646B2 (en) 2010-10-12 2013-12-31 Headway Technologies, Inc. Layered chip package and method of manufacturing same
JP2012104790A (ja) 2010-10-12 2012-05-31 Elpida Memory Inc 半導体装置
JP5591653B2 (ja) 2010-10-27 2014-09-17 東和精工株式会社 ラベル剥離機
US8263435B2 (en) 2010-10-28 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias
US8697492B2 (en) 2010-11-02 2014-04-15 Tessera, Inc. No flow underfill
US8525318B1 (en) 2010-11-10 2013-09-03 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
JPWO2012067177A1 (ja) 2010-11-17 2014-05-12 株式会社フジクラ 配線板及びその製造方法
KR20120056052A (ko) * 2010-11-24 2012-06-01 삼성전자주식회사 반도체 패키지
US8502387B2 (en) 2010-12-09 2013-08-06 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnection and method of manufacture thereof
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US8736065B2 (en) 2010-12-22 2014-05-27 Intel Corporation Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same
US8772817B2 (en) 2010-12-22 2014-07-08 Cree, Inc. Electronic device submounts including substrates with thermally conductive vias
KR101215271B1 (ko) 2010-12-29 2012-12-26 앰코 테크놀로지 코리아 주식회사 반도체 패키지 구조물 및 반도체 패키지 구조물의 제조 방법
US20120184116A1 (en) 2011-01-18 2012-07-19 Tyco Electronics Corporation Interposer
US8766436B2 (en) 2011-03-01 2014-07-01 Lsi Corporation Moisture barrier for a wire bond
US8508045B2 (en) 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
US8841765B2 (en) 2011-04-22 2014-09-23 Tessera, Inc. Multi-chip module with stacked face-down connected dies
US9508622B2 (en) 2011-04-28 2016-11-29 Freescale Semiconductor, Inc. Method for protecting copper wire bonds on aluminum pads of a semiconductor device from corrosion
US8476115B2 (en) 2011-05-03 2013-07-02 Stats Chippac, Ltd. Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive material
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US8633059B2 (en) 2011-05-11 2014-01-21 Stats Chippac Ltd. Integrated circuit packaging system with interconnect and method of manufacture thereof
US8669646B2 (en) 2011-05-31 2014-03-11 Broadcom Corporation Apparatus and method for grounding an IC package lid for EMI reduction
US9128123B2 (en) 2011-06-03 2015-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer test structures and methods
US9117811B2 (en) 2011-06-13 2015-08-25 Tessera, Inc. Flip chip assembly and process with sintering material on metal bumps
US9006031B2 (en) 2011-06-23 2015-04-14 Stats Chippac, Ltd. Semiconductor device and method of forming EWLB package with standoff conductive layer over encapsulant bumps
KR20130007049A (ko) 2011-06-28 2013-01-18 삼성전자주식회사 쓰루 실리콘 비아를 이용한 패키지 온 패키지
US9449941B2 (en) 2011-07-07 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Connecting function chips to a package to form package-on-package
US8476770B2 (en) 2011-07-07 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for forming through vias
US8816505B2 (en) 2011-07-29 2014-08-26 Tessera, Inc. Low stress vias
US8487421B2 (en) 2011-08-01 2013-07-16 Tessera, Inc. Microelectronic package with stacked microelectronic elements and method for manufacture thereof
US8937309B2 (en) 2011-08-08 2015-01-20 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US20130037929A1 (en) 2011-08-09 2013-02-14 Kay S. Essig Stackable wafer level packages and related methods
US20130040423A1 (en) 2011-08-10 2013-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of Multi-Chip Wafer Level Packaging
US8988895B2 (en) 2011-08-23 2015-03-24 Tessera, Inc. Interconnection elements with encased interconnects
KR101800440B1 (ko) 2011-08-31 2017-11-23 삼성전자주식회사 다수의 반도체 칩들을 가진 반도체 패키지 및 그 형성 방법
US20130049218A1 (en) 2011-08-31 2013-02-28 Zhiwei Gong Semiconductor device packaging having pre-encapsulation through via formation
US8816404B2 (en) 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
US9177832B2 (en) 2011-09-16 2015-11-03 Stats Chippac, Ltd. Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect
KR101900423B1 (ko) 2011-09-19 2018-09-21 삼성전자주식회사 반도체 메모리 장치
KR20140085497A (ko) * 2011-10-03 2014-07-07 인벤사스 코포레이션 직교 윈도가 있는 멀티-다이 와이어본드 어셈블리를 위한 스터브 최소화
KR101906408B1 (ko) 2011-10-04 2018-10-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US20130087915A1 (en) 2011-10-10 2013-04-11 Conexant Systems, Inc. Copper Stud Bump Wafer Level Package
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US9105552B2 (en) 2011-10-31 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
KR101297015B1 (ko) 2011-11-03 2013-08-14 주식회사 네패스 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법, 이에 의한 반도체 패키지 및 패키지 온 패키지
US9196588B2 (en) 2011-11-04 2015-11-24 Invensas Corporation EMI shield
US8916781B2 (en) 2011-11-15 2014-12-23 Invensas Corporation Cavities containing multi-wiring structures and devices
US8552556B1 (en) 2011-11-22 2013-10-08 Amkor Technology, Inc. Wafer level fan out package
US8912651B2 (en) 2011-11-30 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure including stud bulbs and method
TWI464031B (zh) 2011-12-14 2014-12-11 Univ Yuan Ze 抑制柯肯達爾孔洞形成於銲料與銅銲墊之間的方法
KR101924388B1 (ko) 2011-12-30 2018-12-04 삼성전자주식회사 재배선 구조를 갖는 반도체 패키지
US8680684B2 (en) 2012-01-09 2014-03-25 Invensas Corporation Stackable microelectronic package structures
US9258922B2 (en) 2012-01-18 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. PoP structures including through-assembly via modules
US8686570B2 (en) 2012-01-20 2014-04-01 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-dimensional integrated circuit structures and methods of forming the same
KR20130090143A (ko) 2012-02-03 2013-08-13 삼성전자주식회사 패키지-온-패키지 타입의 반도체 패키지 및 그 제조방법
US8742576B2 (en) 2012-02-15 2014-06-03 Oracle International Corporation Maintaining alignment in a multi-chip module using a compressible structure
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
DE102012203293B4 (de) 2012-03-02 2021-12-02 Robert Bosch Gmbh Halbleitermodul mit integriertem Wellenleiter für Radarsignale
US20130234317A1 (en) 2012-03-09 2013-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Packaged Semiconductor Devices
US9082763B2 (en) 2012-03-15 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Joint structure for substrates and methods of forming
US9842798B2 (en) 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
KR20130111780A (ko) 2012-04-02 2013-10-11 삼성전자주식회사 Ｅｍｉ 차폐부를 갖는 반도체 장치
US9405064B2 (en) 2012-04-04 2016-08-02 Texas Instruments Incorporated Microstrip line of different widths, ground planes of different distances
US8922005B2 (en) 2012-04-11 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package on package devices with reversed stud bump through via interconnections
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US8978247B2 (en) 2012-05-22 2015-03-17 Invensas Corporation TSV fabrication using a removable handling structure
US9171790B2 (en) 2012-05-30 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US8948712B2 (en) 2012-05-31 2015-02-03 Skyworks Solutions, Inc. Via density and placement in radio frequency shielding applications
US20130323409A1 (en) 2012-05-31 2013-12-05 Skyworks Solutions, Inc. Systems and methods for controlling electromagnetic interference for integrated circuit modules
US8981559B2 (en) 2012-06-25 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US8742597B2 (en) 2012-06-29 2014-06-03 Intel Corporation Package substrates with multiple dice
US8653626B2 (en) 2012-07-18 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures including a capacitor and methods of forming the same
US10115671B2 (en) 2012-08-03 2018-10-30 Snaptrack, Inc. Incorporation of passives and fine pitch through via for package on package
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8642393B1 (en) 2012-08-08 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of forming same
US8828860B2 (en) 2012-08-30 2014-09-09 International Business Machines Corporation Double solder bumps on substrates for low temperature flip chip bonding
US9443797B2 (en) 2012-09-14 2016-09-13 STATS ChipPAC Pte. Ltd. Semiconductor device having wire studs as vertical interconnect in FO-WLP
US8963339B2 (en) 2012-10-08 2015-02-24 Qualcomm Incorporated Stacked multi-chip integrated circuit package
US8975726B2 (en) 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
KR101419597B1 (ko) 2012-11-06 2014-07-14 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9418971B2 (en) 2012-11-08 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure including a thermal isolation material and method of forming the same
US9412661B2 (en) 2012-11-21 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming package-on-package structure
US9401338B2 (en) 2012-11-29 2016-07-26 Freescale Semiconductor, Inc. Electronic devices with embedded die interconnect structures, and methods of manufacture thereof
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US20140175657A1 (en) 2012-12-21 2014-06-26 Mihir A. Oka Methods to improve laser mark contrast on die backside film in embedded die packages
US8729714B1 (en) 2012-12-31 2014-05-20 Intel Mobile Communications GmbH Flip-chip wafer level package and methods thereof
US9378982B2 (en) 2013-01-31 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
US8940630B2 (en) 2013-02-01 2015-01-27 Invensas Corporation Method of making wire bond vias and microelectronic package having wire bond vias
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US8907500B2 (en) 2013-02-04 2014-12-09 Invensas Corporation Multi-die wirebond packages with elongated windows
US20140225248A1 (en) 2013-02-13 2014-08-14 Qualcomm Incorporated Power distribution and thermal solution for direct stacked integrated circuits
US9209081B2 (en) 2013-02-21 2015-12-08 Freescale Semiconductor, Inc. Semiconductor grid array package
US20140239490A1 (en) 2013-02-26 2014-08-28 Unimicron Technology Corporation Packaging substrate and fabrication method thereof
US20140239479A1 (en) 2013-02-26 2014-08-28 Paul R Start Microelectronic package including an encapsulated heat spreader
US9461025B2 (en) 2013-03-12 2016-10-04 Taiwan Semiconductor Manfacturing Company, Ltd. Electric magnetic shielding structure in packages
US9299670B2 (en) 2013-03-14 2016-03-29 Freescale Semiconductor, Inc. Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
US9788466B2 (en) 2013-04-16 2017-10-10 Skyworks Solutions, Inc. Apparatus and methods related to ground paths implemented with surface mount devices
KR20140126598A (ko) 2013-04-23 2014-10-31 삼성전자주식회사 반도체 패키지 및 그 제조 방법
DE112013003153T5 (de) 2013-06-28 2015-05-13 Intel IP Corporation Mikroelektromechanisches System (MEMS) auf anwendungspezifischer integrierter Schaltung (ASIC)
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
KR102161173B1 (ko) 2013-08-29 2020-09-29 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9012263B1 (en) 2013-10-31 2015-04-21 Freescale Semiconductor, Inc. Method for treating a bond pad of a package substrate
US9379078B2 (en) 2013-11-07 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. 3D die stacking structure with fine pitches
KR101631934B1 (ko) 2013-11-13 2016-06-21 앰코 테크놀로지 코리아 주식회사 반도체 패키지 구조물 및 그 제작 방법
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9653442B2 (en) 2014-01-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and methods of forming same
US9224709B2 (en) 2014-02-13 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including an embedded surface mount device and method of forming the same
US9362161B2 (en) 2014-03-20 2016-06-07 Stats Chippac, Ltd. Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
US9318452B2 (en) 2014-03-21 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9437459B2 (en) 2014-05-01 2016-09-06 Freescale Semiconductor, Inc. Aluminum clad copper structure of an electronic component package and a method of making an electronic component package with an aluminum clad copper structure
TWI529892B (zh) * 2014-05-09 2016-04-11 精材科技股份有限公司 晶片封裝體及其製造方法
US20150340305A1 (en) 2014-05-20 2015-11-26 Freescale Semiconductor, Inc. Stacked die package with redistribution layer
US10325876B2 (en) 2014-06-25 2019-06-18 Nxp Usa, Inc. Surface finish for wirebonding
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
KR101640341B1 (ko) 2015-02-04 2016-07-15 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US10490528B2 (en) * 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12009314B2 (en) 2022-08-11 2024-06-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of compartment shielding using bond wires

Also Published As

Publication number Publication date
WO2017116981A1 (en) 2017-07-06
US20170194281A1 (en) 2017-07-06
EP3398207A4 (en) 2019-06-19
KR102436803B1 (ko) 2022-08-25
US10325877B2 (en) 2019-06-18
US20180240773A1 (en) 2018-08-23
US9984992B2 (en) 2018-05-29
CN108369942A (zh) 2018-08-03
KR20180089457A (ko) 2018-08-08
EP3398207A1 (en) 2018-11-07
CN108369942B (zh) 2019-12-03

Similar Documents

Publication Publication Date Title
US11810867B2 (en) Wire bond wires for interference shielding
US10325877B2 (en) Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
KR102562518B1 (ko) 매립형 와이어 본드 와이어
US9818679B2 (en) Semiconductor device
US11869829B2 (en) Semiconductor device with through-mold via
KR100855887B1 (ko) 스택형 반도체 패키지 및 그 스택 방법
US10008534B2 (en) Microelectronic package with horizontal and vertical interconnections