JP2003197668A - 半導体パッケージ用のボンディングワイヤ及びその製造方法 - Google Patents

半導体パッケージ用のボンディングワイヤ及びその製造方法

Info

Publication number
JP2003197668A
JP2003197668A JP2001376095A JP2001376095A JP2003197668A JP 2003197668 A JP2003197668 A JP 2003197668A JP 2001376095 A JP2001376095 A JP 2001376095A JP 2001376095 A JP2001376095 A JP 2001376095A JP 2003197668 A JP2003197668 A JP 2003197668A
Authority
JP
Japan
Prior art keywords
gold
core wire
wire
semiconductor package
bonding wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001376095A
Other languages
English (en)
Inventor
Pen Teien Riao
ペン ティエン リアオ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SENMAO KOOCHII KOFUN YUGENKOSH
SENMAO KOOCHII KOFUN YUGENKOSHI
Original Assignee
SENMAO KOOCHII KOFUN YUGENKOSH
SENMAO KOOCHII KOFUN YUGENKOSHI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SENMAO KOOCHII KOFUN YUGENKOSH, SENMAO KOOCHII KOFUN YUGENKOSHI filed Critical SENMAO KOOCHII KOFUN YUGENKOSH
Priority to JP2001376095A priority Critical patent/JP2003197668A/ja
Publication of JP2003197668A publication Critical patent/JP2003197668A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/431—Pre-treatment of the preform connector
    • H01L2224/4312—Applying permanent coating, e.g. in-situ coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/432—Mechanical processes
    • H01L2224/4321—Pulling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/438—Post-treatment of the connector
    • H01L2224/4382—Applying permanent coating, e.g. in-situ coating
    • H01L2224/43825—Plating, e.g. electroplating, electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45164—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00015—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/012—Semiconductor purity grades
    • H01L2924/01204—4N purity grades, i.e. 99.99%
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/2075—Diameter ranges larger or equal to 1 micron less than 10 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20751—Diameter ranges larger or equal to 10 microns less than 20 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20753—Diameter ranges larger or equal to 30 microns less than 40 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20754—Diameter ranges larger or equal to 40 microns less than 50 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20755—Diameter ranges larger or equal to 50 microns less than 60 microns

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal Extraction Processes (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【課題】 信号伝達の品質を保持することができるのみ
ならず、金製のものより価格もかなり安価になる半導体
パッケージ用のボンディングワイヤ及びその製造方法を
提供しようとする。 【解決手段】 本発明の半導体パッケージ用のボンディ
ングワイヤは、金以外の金属からなる芯線と前記芯線表
面の金メッキ層とを備えてなるように構成する。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明はボンディングワイヤ
及びその製造方法に関し、特に、半導体パッケージ用の
ボンディングワイヤ及びその製造方法に関する。
【０００２】
【従来の技術】従来から、半導体デバイスにおける信号
伝達の品質を保証するために、半導体パッケージ用のボ
ンディングワイヤとしては、一般的に、金を使用してい
る。しかし、金ワイヤは値段が非常に高いので、コスト
上に問題がある。
【０００３】
【発明が解決しようとする課題】上記問題点に鑑み、本
発明は、信号伝達の品質を保持することができるのみな
らず、金製のものより価格もかなり安価になる半導体パ
ッケージ用のボンディングワイヤ及びその製造方法を提
供することを目的とする。
【０００４】
【課題を解決するための手段】前記目的を達成するため
に、本発明は、まず、第１の視点からみれば、金以外の
金属からなる芯線と前記芯線表面の金メッキ層とを備え
てなることを特徴とする半導体パッケージ用のボンディ
ングワイヤを提供し、さらに詳しく言えば、延性のある
金以外の金属からなる芯線の表面に金メッキ層を被覆形
成したものを引き伸ばしてなることを特徴とする半導体
パッケージ用のボンディングワイヤを提供する。本発明
は、そして、第２の視点からみれば、延性のある金以外
の金属線材を引き伸ばして直径３００μｍ〜５００μｍ
の芯線を形成する芯線延伸成形工程と、前記延伸成形し
てなる芯線の表面に金被覆層をメッキする金メッキ工程
と、前記金メッキをした芯線を再度引き伸ばして、直径
１μｍ〜５０μｍの金メッキ線を形成する２次延伸成形
工程とを備えてなることを特徴とする半導体パッケージ
用のボンディングワイヤの製造方法を提供する。
【０００５】
【発明の実施の形態】以下、本発明を実施の形態に基づ
いて具体的に説明するが、本発明はこの例だけに限定さ
れるものではない。
【０００６】本発明の前記半導体パッケージ用のボンデ
ィングワイヤの製造方法は次の通りである。 一、芯線延伸成形工程：図１における工程１のように、
予めて用意した金以外の延性がある金属線材、例えば銀
又はパラジウム製の線材を引き伸ばして直径３００μｍ
〜５００μｍの芯線を形成する。 二、金メッキ工程：図１に示すように、前記工程１に引
き続く工程２であるが、図２を参照すると、主として下
記８ステップを含む。 （一） 脱脂ステップ：図２におけるステップ２１のよ
うに、アルカリ電解脱脂剤によって、前記延伸成形して
なる芯線の表面からオイルステーン等を除去する。 （二） １次リンスステップ：図２におけるステップ２
２のように、加圧水で前記芯線の表面から電解脱脂剤な
どを洗い落とす。 （三） 酸洗いステップ：図２におけるステップ２３の
ように、酸洗剤で前記芯線の表面を活性化させる。 （四） ２次リンスステップ：図２におけるステップ２
４のように、加圧水で前記芯線表面の酸洗剤を洗い落と
す。前記４ステップは、芯線表面のメッキ付着性を向上
させるためである。 （五） メッキステップ：図２におけるステップ２５の
ように、金材で、前記４ステップを通して処理した芯線
の表面に純度９９．９９％以上、厚さ２．５μｍ〜２５
μｍの金被覆層をメッキする。 （六） ３次リンスステップ：図２におけるステップ２
６のように、加圧水で前記金メッキをした芯線の表面を
洗浄する。 （七） シール処理ステップ：図２におけるステップ２
７のように、酸化防止のため、前記洗浄した芯線の表面
にシーラントなどの防錆材を塗布する。 （八） 乾燥ステップ：図２におけるステップ２８のよ
うに、前記シーラントを塗布した芯線を乾燥する。前記
２工程を施してなる芯線は、図３に示す３０のように、
３１は直径３００μｍ〜５００μｍの芯線であり、３２
は前記芯線３１の表面に被覆した金メッキ層である。 三、２次延伸成形工程：図１に返って参照すると、工程
２の金メッキに続く工程３のように、前記金メッキ工程
を施した芯線を再度引き伸ばして、金メッキ層を厚さ
０．０１２５μｍ〜２．５μｍに、且つ、金メッキ線の
直径を１μｍ〜５０μｍに形成させる。 四、仕様チェック工程：前記金メッキ線の仕様を検査す
る。即ち、図４に示すように、金以外の金属からなる芯
線４１と前記芯線表面の金メッキ層４２とを備えてなる
直径１μｍ〜５０μｍの金メッキ線４０であって、半導
体パッケージ用のボンディングワイヤとして使われるも
のである。
【０００７】
【発明の効果】上記から分かるように、本発明の半導体
パッケージ用のボンディングワイヤ及びその製造方法は
下記のような利点及び効果がある。 一、金より値段が低い金属を主体としたので、製造コス
トを大幅に軽減させることができる。実証により、従来
の半導体パッケージ用のボンディングワイヤより約３５
％の製造コストを減らすことができる。 二、銀又はパラジウムからなる芯線も信号伝達の良いも
のである上、金メッキを施したので、信号伝達の品質は
全金線に殆ど劣らない。 三、メッキ工程は、直径が割に大きい芯線３０を用いる
ので、メッキ工程中における芯線の破断を避けることが
できる。
【０００８】本発明は、上記のように、添付図面を参照
しながら好ましい実施形態に関連して充分に記載されて
いるが、この技術の熟練した人々にとっては種々の変形
や修正は明白である。そのような変形や修正は、添付し
た請求の範囲による本発明の範囲から外れない限りにお
いて、その中に含めれると理解されるべきである。
【図面の簡単な説明】
【図１】本発明の半導体パッケージ用のボンディングワ
イヤの製造方法例の工程順を示すフローチャートであ
る。
【図２】前記図１の製造方法例における工程２のステッ
プ順を示すフローチャートである。
【図３】前記工程２を施した芯線例の断面図である。
【図４】前記製造方法例の半導体パッケージ用のボンデ
ィングワイヤ製品例の断面図である。
【符号の説明】
３０…工程２を施した後の芯線（メッキ済み） ３１…芯線 ３２…金メッキ層 ４０…半導体パッケージ用のボンディングワイヤとして
の金メッキ線製品 ４１…芯線 ４２…金メッキ層
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 4E096 EA01 EA13 EA26 4K024 AA11 AB01 BA01 BB12 BC03 DA03 DA04 GA07 5F044 FF02 FF04 FF10

Claims (5)

    【特許請求の範囲】
  1. 【請求項１】 金以外の金属からなる芯線と前記芯線表
    面の金メッキ層とを備えてなることを特徴とする半導体
    パッケージ用のボンディングワイヤ。
  2. 【請求項２】 延性のある金以外の金属からなる芯線の
    表面に金メッキ層を被覆形成したものを引き伸ばしてな
    ることを特徴とする半導体パッケージ用のボンディング
    ワイヤ。
  3. 【請求項３】 前記金以外の金属として銀またはパラジ
    ウムを使用したことを特徴とする請求項１または２に記
    載の半導体パッケージ用のボンディングワイヤ。
  4. 【請求項４】 延性のある金以外の金属線材を引き伸ば
    して直径３００μｍ〜５００μｍの芯線を形成する芯線
    延伸成形工程と、 前記延伸成形してなる芯線の表面に金被覆層をメッキす
    る金メッキ工程と、 前記金メッキをした芯線を再度引き伸ばして、直径１μ
    ｍ〜５０μｍの金メッキ線を形成する２次延伸成形工程
    と、 を備えてなることを特徴とする半導体パッケージ用のボ
    ンディングワイヤの製造方法。
  5. 【請求項５】 前記金メッキ工程では、前記金被覆層の
    厚さを２．５μｍ〜２５μｍになさしめ、且つ、前記２
    次延伸成形工程では、前記金被覆層の厚さを０．０１２
    ５μｍ〜２．５μｍになさしめることを特徴とする請求
    項４に記載の半導体パッケージ用のボンディングワイヤ
    の製造方法。
JP2001376095A 2001-12-10 2001-12-10 半導体パッケージ用のボンディングワイヤ及びその製造方法 Pending JP2003197668A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001376095A JP2003197668A (ja) 2001-12-10 2001-12-10 半導体パッケージ用のボンディングワイヤ及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001376095A JP2003197668A (ja) 2001-12-10 2001-12-10 半導体パッケージ用のボンディングワイヤ及びその製造方法

Publications (1)

Publication Number Publication Date
JP2003197668A true JP2003197668A (ja) 2003-07-11

Family

ID=27590748

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001376095A Pending JP2003197668A (ja) 2001-12-10 2001-12-10 半導体パッケージ用のボンディングワイヤ及びその製造方法

Country Status (1)

Country Link
JP (1) JP2003197668A (ja)

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007123597A (ja) * 2005-10-28 2007-05-17 Nippon Steel Materials Co Ltd 半導体装置用ボンディングワイヤ
JP2012134534A (ja) * 2006-05-25 2012-07-12 Taiwan Semiconductor Manufacturing Co Ltd 複合ボンドワイヤ用の方法及びシステム
JP2018525519A (ja) * 2015-07-13 2018-09-06 ヘレウス ドイチェラント ゲーエムベーハー ウント カンパニー カーゲー 第２の金属から作製されたシース層を有する、第１の金属から作製されたワイヤを製造する方法
US10128216B2 (en) 2010-07-19 2018-11-13 Tessera, Inc. Stackable molded microelectronic packages
KR101921156B1 (ko) * 2011-11-29 2018-11-22 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US10170412B2 (en) 2012-05-22 2019-01-01 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10290613B2 (en) 2013-11-22 2019-05-14 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10297582B2 (en) 2012-08-03 2019-05-21 Invensas Corporation BVA interposer
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US10325877B2 (en) 2015-12-30 2019-06-18 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US10460958B2 (en) 2013-08-07 2019-10-29 Invensas Corporation Method of manufacturing embedded packaging with preformed vias
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10529636B2 (en) 2014-01-17 2020-01-07 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10559537B2 (en) 2015-10-12 2020-02-11 Invensas Corporation Wire bond wires for interference shielding
US10593643B2 (en) 2011-05-03 2020-03-17 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10658302B2 (en) 2016-07-29 2020-05-19 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10756049B2 (en) 2011-10-17 2020-08-25 Invensas Corporation Package-on-package assembly with wire bond vias
US10806036B2 (en) 2015-03-05 2020-10-13 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips

Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4722671B2 (ja) * 2005-10-28 2011-07-13 新日鉄マテリアルズ株式会社 半導体装置用ボンディングワイヤ
JP2007123597A (ja) * 2005-10-28 2007-05-17 Nippon Steel Materials Co Ltd 半導体装置用ボンディングワイヤ
JP2012134534A (ja) * 2006-05-25 2012-07-12 Taiwan Semiconductor Manufacturing Co Ltd 複合ボンドワイヤ用の方法及びシステム
US10128216B2 (en) 2010-07-19 2018-11-13 Tessera, Inc. Stackable molded microelectronic packages
US10593643B2 (en) 2011-05-03 2020-03-17 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US11424211B2 (en) 2011-05-03 2022-08-23 Tessera Llc Package-on-package assembly with wire bonds to encapsulation surface
US10756049B2 (en) 2011-10-17 2020-08-25 Invensas Corporation Package-on-package assembly with wire bond vias
US11735563B2 (en) 2011-10-17 2023-08-22 Invensas Llc Package-on-package assembly with wire bond vias
US11189595B2 (en) 2011-10-17 2021-11-30 Invensas Corporation Package-on-package assembly with wire bond vias
KR101921156B1 (ko) * 2011-11-29 2018-11-22 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US10170412B2 (en) 2012-05-22 2019-01-01 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US10510659B2 (en) 2012-05-22 2019-12-17 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US10297582B2 (en) 2012-08-03 2019-05-21 Invensas Corporation BVA interposer
US10460958B2 (en) 2013-08-07 2019-10-29 Invensas Corporation Method of manufacturing embedded packaging with preformed vias
USRE49987E1 (en) 2013-11-22 2024-05-28 Invensas Llc Multiple plated via arrays of different wire heights on a same substrate
US10629567B2 (en) 2013-11-22 2020-04-21 Invensas Corporation Multiple plated via arrays of different wire heights on same substrate
US10290613B2 (en) 2013-11-22 2019-05-14 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US11404338B2 (en) 2014-01-17 2022-08-02 Invensas Corporation Fine pitch bva using reconstituted wafer with area array accessible for testing
US10529636B2 (en) 2014-01-17 2020-01-07 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US11990382B2 (en) 2014-01-17 2024-05-21 Adeia Semiconductor Technologies Llc Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US10806036B2 (en) 2015-03-05 2020-10-13 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
JP2018525519A (ja) * 2015-07-13 2018-09-06 ヘレウス ドイチェラント ゲーエムベーハー ウント カンパニー カーゲー 第２の金属から作製されたシース層を有する、第１の金属から作製されたワイヤを製造する方法
US10559537B2 (en) 2015-10-12 2020-02-11 Invensas Corporation Wire bond wires for interference shielding
US11462483B2 (en) 2015-10-12 2022-10-04 Invensas Llc Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10325877B2 (en) 2015-12-30 2019-06-18 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10658302B2 (en) 2016-07-29 2020-05-19 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor

Similar Documents

Publication Publication Date Title
JP2003197668A (ja) 半導体パッケージ用のボンディングワイヤ及びその製造方法
TW454281B (en) Method and apparatus for enabling conventional wire bonding to copper-based bond pad features
KR100371567B1 (ko) Ａｇ 선도금을 이용한 반도체 패키지용 리드프레임
JP2002076226A (ja) リードフレームとその製造方法
US20040195696A1 (en) Integrated circuit die having a copper contact and method therefor
JPH11181593A (ja) 銅被覆アルミニウム線の製造方法
US6261436B1 (en) Fabrication method for gold bonding wire
JPS62288634A (ja) ゴム物品補強用スチ−ルワイヤ−およびスチ−ルコ−ドの製造方法
JP4670931B2 (ja) リードフレーム
JP5109881B2 (ja) 銅ボンディングワイヤ
JPH10163401A (ja) リードフレーム、半導体パッケージ及び半導体パッケージの製造方法
KR100947921B1 (ko) 연성인쇄회로기판의 고연성 Ａｕ 표면처리 도금방법
US20160204003A1 (en) Method of forming asper-silver on a lead frame
JPH11121673A (ja) リードフレーム
US6711925B2 (en) Process for manufacturing a conductive wire suitable for use in semiconductor packages
TW200901422A (en) Pre-plated leadframe having enhanced encapsulation adhesion
JP2007088211A (ja) リードフレーム及びその製造方法
JP5299411B2 (ja) リードフレームの製造方法
JP2003059963A (ja) パッケージ及び高周波伝送用金ワイヤとその製造方法
JPH03124091A (ja) 厚膜印刷基板の製造方法
TW504826B (en) Manufacturing method of semiconductor package wire
JP2001144133A (ja) パッケージ用金ワイヤの製造方法およびそのパッケージ用金ワイヤ
JPS6218744A (ja) リ−ドフレ−ム
JPH0368788A (ja) リードフレーム用銅条の製造方法
JP2005340474A (ja) リードフレームとその製造方法

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040518

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20041019