JP2012134534A - 複合ボンドワイヤ用の方法及びシステム - Google Patents

複合ボンドワイヤ用の方法及びシステム Download PDF

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Publication number
JP2012134534A
JP2012134534A JP2012045206A JP2012045206A JP2012134534A JP 2012134534 A JP2012134534 A JP 2012134534A JP 2012045206 A JP2012045206 A JP 2012045206A JP 2012045206 A JP2012045206 A JP 2012045206A JP 2012134534 A JP2012134534 A JP 2012134534A
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bond wire
wire
conductivity
conductive material
mixture
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JP2012045206A
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JP5709783B2 (ja
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Wyland Chris
ワイランド クリス
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C1/00Making non-ferrous alloys
    • C22C1/10Alloys containing non-metals
    • C22C1/1036Alloys containing non-metals starting from a melt
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B22CASTING; POWDER METALLURGY
    • B22FWORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
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Abstract

【課題】集積回路用のボンドワイヤを提示する。
【解決手段】集積回路内で使用する複合ボンドワイヤ110を生産するため、導電材料を溶解し、100ミクロン未満の粒度の粒子材料と混合して混合物を生成する。この混合物を用いて複合ボンドワイヤ110を作製する。内部コア、及びこの内部コアより高い導電率を有する外層を有する複合ワイヤも提供される。この外層は、交流信号を搬送するための動作周波数における表皮深度よりも厚く設計する。
【選択図】図1

Description

本発明は一般に集積回路(IC)のパッケージ化に関するものであり、特に半導体デバイス用のボンドワイヤの実現に関するものである。
電子産業は、半導体技術の進歩に継続的に依存して、より高機能のデバイスをより小さい面積で実現している。多くの応用にとって、より高機能のデバイスを実現することは、非常に多数の電子デバイスを単一のシリコンウエハー内に集積することを必要とする。シリコンウエハーの所定面積あたりの電子デバイス数が増加するとともに、製造プロセスがより困難になる。
多くの分野における種々の応用に伴い、多種多様な半導体デバイスが製造されている。こうしたシリコンベースの半導体デバイスは、p型MOS(PMOS)、n型MOS(NMOS)ならびに相補型(コンプリメンタリ)MOS(CMOS)トランジスタのような金属酸化膜半導体電界効果トランジスタ(MOSFET)、バイポーラトランジスタ、またはBiCMOSトランジスタを含むことが多い。こうしたMOSFETデバイスは、導電ゲートとシリコン状物質との間に絶縁材料を含み、従って、これらデバイスは一般にIGFET(絶縁ゲートFET)と称される。
これらの半導体デバイスは一般に半導体基板を含み、この半導体基板上に多数の能動素子が形成されている。所定の能動素子の特定構造は、デバイスの種類間で異なり得る。例えば、MOSトランジスタでは、能動素子は一般に、ソース及びドレイン領域、及びソース/ドレイン領域間の電流を調整するゲート電極を含む。
さらに、こうしたデバイスは、多数のウエハー製造プロセスにおいて生産されるデジタルまたはアナログデバイス、例えばCMOS、BiCMOS、バイポーラ等とすることができる。基板は、シリコン、ガリウムヒ素(GaAs)、または基板上に超小型電子回路を構成するのに適した他の基板とすることができる。
製造プロセスを施された後に、シリコンウエハーは所定数のデバイスを有する。これらのデバイスをテストし、機能デバイスを収集してパッケージ化する。
複合ICデバイスのパッケージ化は、これらのデバイスの最終的な性能にますます影響を与える。多くのパッケージは基板を含み、この基板上に、パッドランドによって包囲された所定のダイ取り付け領域上にデバイスダイが実装されている。デバイスダイ自体は、ダイ取り付け領域を包囲するそれぞれのパッドランドからそれぞれのボンディングパッドに取り付けたボンドワイヤを介した当該デバイスダイの外界への接続を促進するためのボンディングパッドを有する。パッドランドは、基板内に規定した導電トレース(導線)を通して外部接点に接続される。一部のパッケージの種類では、適切なモールド化合物内へのカプセル化によって、組み立てたデバイスを環境被害から保護する
デバイスの複雑性が増すと共に、ワイヤボンドの数が何百にも達する。こうした複雑な製品は、ラップトップコンピュータ、個人用携帯端末(PDA)、無線電話機、自動車用電子制御モジュール等を含む。
基板をパッケージ化するためのICデバイスのワイヤボンディングに使用される材料は、貴金属または他の高価な材料であることが多い。例えば、ワイヤボンディングに用いられる一般的な材料は、金、アルミニウム、銅、パラジウム合金、白金及び銀を含む。金は、それ自体を極めて適したものにする多数の性質、例えば導電率、耐食性、及び可鍛性を有する。特に、金の可鍛性は、ユーザがこの金属を、ICデバイスに使用される非常に微細なボンドワイヤのような微細な形状に成形し展伸することを可能にする。これに加えて、金は種々のICデバイスに良好に結合される。
複雑な電子製品の需要が増加すると共に、ワイヤボンディング材料の消費も増加する。量に加え、電子産業及び他の産業において増加する需要に世界的に限られた供給量が結び付くことにより、材料のコストは否応なしに上昇する。
本発明の種々の態様は、上述した問題に応え、これらの問題を克服する方法でボンドワイヤを実現する方法及び装置に指向したものである。
1つの好適例によれば、本発明は、複合ボンドワイヤの内側部分及び導電材料の外層を有する複合ボンドワイヤに指向している。外層の電気抵抗は内側部分の電気抵抗よりも低い。
他の好適例によれば、本発明は、集積回路に適した複合ボンドワイヤを生産するために用いる方法に指向している。導電材料を溶解しセラミック材料と混合して、この導電材料とセラミック材料との混合物を生成する。この混合物を用いて複合ボンドワイヤを生成する。
以上の本発明の概要は、本発明の各実施例、あるいはすべての実現を記述することを意図していない。本発明の利点及び実現は、本発明のより完全な理解と共に、以下の詳細な説明及び請求項を図面と共に参照することによって明らかになり理解される。
以下の本発明の種々の実施例の詳細な説明を図面と関連して考慮すれば、本発明をより完全に理解することができる。
図1A〜1Cは、本発明の実施例によるボンドワイヤを用いた集積回路の実現を示す図である。 本発明の実施例によるボンドワイヤの断面を示す図である。 本発明の実施例による、ボンドワイヤを生産する方法を示すフローチャートである。
本発明は種々の変更及び代案の形式が可能であり、その詳細を例として図面に示し詳細に説明する。しかし、その意図は、本発明を説明する特定実施例に限定することではない。逆に、その意図は、請求項に記載の範囲内に入る全ての変更、等価物、及び代替物を網羅することにある。
本発明は、ボンドワイヤを含む種々の集積回路及び方法に適用可能であるものと確信される。本発明は必ずしもこうした応用に限定されず、本発明の種々の態様の理解は、こうした環境における例の説明を通して最良に得られる。
本発明の実施例によれば、高い導電率を有する材料とより低い導電率を有するサブミクロン粒子との混合物で構成される1つ以上の複合ボンドワイヤを用いて集積回路デバイスを構成する。
本発明の他の実施例は、複合ボンドワイヤを構成する方法を含む。低い導電率を有する第1材料を用いてボンドワイヤを作製する。このボンドワイヤを、高い導電率を有する第2材料の層で被覆する。この層の厚さは、このボンドワイヤを通して伝送される信号の想定周波数によって決まる。
特定実施例では、上記第2層の厚さが、ボンドワイヤの表皮効果または表皮深度の計算値に相当する。増加する周波数における導電体の挙動は表皮効果として記述される。表皮効果は、導体の実効抵抗を電流の周波数と共に増加させる。
以下の例では、無限の厚さの平面導体における電流密度Jが、表面からの深さδとともに指数関数的に次式のように減少する:
ここに、dは表皮深度と称する定数である。これは導体の表面下の深さとして定義され、この深さにおける電流は表面(JS)における電流の1/e(約0.37)倍である。これは次式のように計算することができる:
ここに、
ρ=導体の抵抗
ω=電流の角周波数=2π×周波数
μ=導体の絶対透磁率
である。
フラットスラブ(dよりずっと厚い)の交流電流に対する抵抗は、本質的に厚さdの平板の直流電流に対する抵抗に等しい。ワイヤのような長く薄い導体については、抵抗は、直流電流を搬送する厚さdの壁面を有する中空管の抵抗におよそ等しい。例えば、円形のワイヤについては、交流抵抗はおよそ次式のようになる。
ここに、
L=導体の長さ
D=導体の直径
である。上記の最終的な近似は、D>>dの場合に正確である。
抵抗が周波数f(ヘルツ)において10%だけ増加する円形断面のワイヤの直径DW(mm)についての簡便な公式(F.E.Termanによる)は、次式である:
以下、銅線について、種々の周波数における概略的な表皮深度を表1に示す。
従って、所定断面積のワイヤについては、周波数が増加するほど、ワイヤ表面からより小さい距離に電流が生じる。表皮効果を用いれば、周波数が増加すると共に、ワイヤの断面積のより小さい割合がボンドワイヤの実効抵抗に関係するので、金属ボンドワイヤの金属含有量を低減することが可能である。たとえば、100KHzで動作するように作製されたワイヤは、より低い導電率の材料の内部コアを包囲する約0.21mmの銅を用いて構成することができる。
高性能半導体素子のパッケージ化に使用され、金のような貴金属で構成されるボンドワイヤについては、本発明は、ボンドワイヤの金属含有量の低減に当たり有用であることが判明している。高周波数においては、所定の厚さのより高い導電率の金属によって包囲されたより低導電率の材料のコアを有するボンドワイヤを構成することが可能である。上記より高い導電率の金属の厚さは、高周波用途向けには比較的薄く、低周波用途向けには比較的厚くすることができる。
図面を参照すれば、図1に、本発明の実施例によるボンドワイヤを用いた集積回路を示す。図1Aは、ダイ108、基板112、及び複合ボンドワイヤ110を示す。ボンドワイヤ110の種々の実施例を、図1B及び図1Cにより詳細に示す。
ダイ108は基板112上に実装され、ボンドワイヤ110を用いて基板上のパッドに電気接続されている。図1Aに示す集積回路装置は、ボンドワイヤを用いて集積回路の種々の構成部品を電気接続する多数の可能な集積回路設計の一例に過ぎない。ワイヤボンドを用いた他の集積回路の例は、スタックト(積層)ダイ構成及びダイダウン構成を含む。ボンドワイヤ110は本明細書の種々の教示に整合する。
図1Bに、ボンドワイヤ110の実現の一例を示す。ボンドワイヤの内側部分114は、低い導電率を有するのに対し、外側部分116は高い導電率を有する。内側部分及び外側部分の導電率及び厚さは、特定用途に対応する。高周波信号に限定した用途向けには、外側部分は比較的薄く、内側部分はごくわずかしか、あるいは全く導電性を有しないことができる。低周波信号に限定した用途向けには、外側部分はより厚く、内側部分はごくわずかしか、あるいは全く導電性を有しないままにすることができる。高周波数に対して低導電率を必要とし、かつ直流電流に対してより低い導電率を必要とする用途向けには、外側部分は比較的薄く、内側部分は十分な直流導電性を有する。内側部分及び外側部分の厚さ及び導電率の他の種々の組合せが考えられる。具体例では、上記外層の厚さが、用途において想定されるボンドワイヤの表皮深度によって決まる。
ボンドワイヤの内側部分の特性(例えば導電率及びフレキシビリティ(可撓性))は、異なる方法を用いて制御することができる。第1の方法は、所望の特性を示す材料を選択するステップ、及びこの材料で内側部分を形成するステップを含む。従って(銅、アルミニウム、ニッケル、及び銀のような)導電材料並びに(セラミックのような)絶縁材料を用いて内側部分を形成することができる。ボンドワイヤの外側部分は、信号周波数及び導電率の要求によって決まる応用の電気的要求を満たす材料で形成する。
第2の方法は、低導電率材料を高導電率材料と混合するステップを含む。この混合物はボンドワイヤの内側部分を形成する。具体例では、この低導電率材料がサブミクロン・セラミック粒子であり、この高導電率材料が金のような金属である。外側部分は、純粋な高コスト材料の形態、または(内側部分に比べて)低導電率材料に対する高導電率材料の比率を増加させた混合物のいずれかで形成する。サブミクロン・セラミック粒子の例は、酸化物、炭化物、ホウ化物または窒化物のような材料を含む。セラミック粒子の他の具体例は、アルミナ(酸化アルミニウム)、ベリリア(酸化ベリリウム)またはステアタイト(凍石)を含む。あるいはまた、導電性のサブミクロン粒子を用いることができる。
図1Cに、ボンドワイヤ110の実現の他一例を示す。ボンドワイヤ110は、導電材料118及びサブミクロン粒子120を用いて形成される。一例では、上記サブミクロン粒子は、理想的な電気特性以下の低コスト材料から成る。サブミクロン粒子の高密度は、ボンドワイヤ中の導電材料118の総体積を低減し、従ってボンドワイヤのコストを低減することができる。しかし、サブミクロン粒子の密度が増加すると共にボンドワイヤの導電率が低下するので、ボンドワイヤ110中のサブミクロン粒子の密度はボンドワイヤの導電率にも影響する。従って、ボンドワイヤのコストをボンドワイヤの所望の導電率と釣り合わせることが有利である。例えば、導電材料118を金とし、サブミクロン粒子120を溶融した金と混合したセラミック粉末とすることができる。特定用途では、金は、この用途の最小導電率の要求を上回るが、それでも最も費用効果的な材料である。特定量のセラミック粉末を金中に混合することにとって、最小導電率の要求を維持しつつ特定の厚さのボンドワイヤ中の金の量を低減することができ、これによりボンドワイヤのコストを低減することができる。
他の実施例では、図1Cのボンドワイヤを高導電率の層で被覆して、高周波信号に対するワイヤの導電率を増加させることができる。この層は、高周波信号の表皮深度の関数とすることができる。さらに、ワイヤ内側部分中のサブミクロン粒子の密度は、ボンドワイヤの低周波信号の要求または直流の要求の関数とすることができる。
図2に、本発明の他の実施例を示す。図2は、表皮深度202及び204で構成した層を含む複数の層206〜210を有するボンドワイヤの断面を示す。ボンドワイヤ200は3つの異なる層を有するように示しているが、層の数は用途に応じて変化させることができる。層210は、第1表皮深度202用に構成した高導電率の層である。この表皮深度は高周波数ω1に対応する。層208は、層210よりも低い導電率、及び表皮深度204を有する層である。表皮深度204は第2周波数ω2に対応する。層206は、導電性でも最小の導電率を有する層であり、ω2よりも低い周波数及び直流の要求に対して選択する。こうした多層化は特に有用である、というのは、高周波信号は、多くの高周波信号用の精密なタイムマージンのために低周波信号よりも低い導電率を必要とすることが多く、そして一部の応用は、異なる信号周波数を同一ボンドワイヤ上で使用するからである。
図3に、本発明の例の実施例によるボンドワイヤを生産する方法を示す。ブロック302に示すように第1導電材料を溶融する。例えば、融点を超えて加熱することによってこの材料を溶融する。ブロック304に示すように、溶融した材料中にサブミクロン粒子を導入する。サブミクロン粒子の密度は、最終的なボンドワイヤに要求される電気特性及び物理特性を評価することで決定することができる。セラミック粒子の具体例は市販のセラミック粉末を含む。これら粒子は一般に、比較的低コストで入手可能であり、多くの金属を溶融するために必要な高熱で破壊されない。
ブロック306に示すように、結果的な混合物をワイヤに形成する。ワイヤを形成する具体例では、混合物を所望の線径まで「展伸」または「延伸」するが、他のワイヤ形成技術も考えられる。そしてブロック308に示すように、随意的に、1つ以上の高導電率材料の層でワイヤを被覆(コーティング)する。このように追加的な層を構成して、より厳しい電気特性(例えば高周波数に対する導電率)を満足することができる。この最終層を追加した後に、ブロック310に示すように、このボンドワイヤを集積回路内で使用する。
図面に示して上述した種々の実施例は、例として提供するに過ぎず、本発明を限定するものと解釈すべきではない。以上の説明及び図示に基づき、当業者は、本明細書に図示及び記載した好適な実施例及び応用に厳格に従わない種々の変形及び変更を本発明に加え得ることを容易に認識する。例えば、金属及びセラミックのボンドワイヤ以外の応用は、同様の方法を用いた実現に従うことができる。こうした変形及び変更は、請求項に記載の本発明の範囲から逸脱しない

Claims (7)

  1. 集積回路内で使用される複合ボンドワイヤを生産する方法において、
    導電材料を溶解するステップと、
    100ミクロン未満の粒度の粒子材料を前記導電材料と混合して混合物を生成するステップと、
    前記混合物から前記複合ボンドワイヤを作製するステップと
    を備えていることを特徴とする方法。
  2. 請求項1に記載の方法において、さらに、前記複合ボンドワイヤの外側に外側導電材料の層を加えるステップを備えていることを特徴とする方法。
  3. 請求項2に記載の方法において、前記外側導電材料は、前記集積回路が使用する信号周波数によって決まる表皮深度より大きい厚さを有することを特徴とする方法。
  4. 請求項1に記載の方法において、前記導電材料が金属であることを特徴とする方法。
  5. 請求項2に記載の方法において、前記外側導電材料が金であることを特徴とする方法。
  6. 請求項1に記載の方法において、前記混合物から前記複合ボンドワイヤを作製するステップが、前記混合物を所望の厚さに展伸することを含むことを特徴とする方法。
  7. 請求項1に記載の方法において、前記100ミクロン未満の粒度の粒子材料がセラミックであることを特徴とする方法。
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