TW504826B - Manufacturing method of semiconductor package wire - Google Patents

Manufacturing method of semiconductor package wire Download PDF

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Publication number
TW504826B
TW504826B TW090123067A TW90123067A TW504826B TW 504826 B TW504826 B TW 504826B TW 090123067 A TW090123067 A TW 090123067A TW 90123067 A TW90123067 A TW 90123067A TW 504826 B TW504826 B TW 504826B
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Taiwan
Prior art keywords
wire
gold
core wire
semiconductor package
heart
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TW090123067A
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Chinese (zh)
Inventor
Ben-Tian Liau
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Asep Tec Co Ltd
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Priority to TW090123067A priority Critical patent/TW504826B/en
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Publication of TW504826B publication Critical patent/TW504826B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

The present invention provides a manufacturing method of semiconductor package wire. The method comprises the following steps: (1) preparing at least a wire rod; (2) proceeding a first drawing and pulling process to obtain a core wire; (3) proceeding a plating operation to obtain a gold-plated core wire; (4) proceeding a second drawing and pulling process to obtain a very fine core wire; (5) examining the very fine core wire to obtain a conductive wire of semiconductor package which comprises a wire core using the extendable and non-pure gold material, and a gold plated layer uniformly adhered to the surface of the wire core and having an appropriate thickness.

Description

C7 D7 五、創作説明（) "" ^ 【創作領域】 、本I月疋有關於一種半導體（例如1C、LED等等）的 封衣導線，特別是指一種^^線材成本低廉，且訊號導 通率良好之造方法。 【習知技藝說明】 、_矣的種半導體封裝導線為了得到高品質的訊號導 通率，因此，該封裝導線整體均是以純金為材質而製成。 隹y忒封I導線藉由純金的材料特性，可讓半導體於運 作時獲得優良的訊號導通率，但，純金的材料成本高昂， 浚此不僅造成業者整體成本無法有效地降低，更導致業 者的競爭力大幅下降。 【創作概要】 因此，本發明之目的，即在於提供一種复^材料成 本低廉，且具有高品質訊號導通率之半導體封赉荽綠夕1 - 於是，本I日月線之製造方法，該方法 包含以下步驟：一、準備至少一盤元··該盤元是以具延展 性之非純金金屬為材質。二、進行第一道抽拉處理：使該 盤元經過至少一模座，進而使該盤元成型為一具有一第一 線徑的心線。三、進行電鍍作業：對該心線進行電鍍，使 名心線表面均勻鍍上一金質鍍層而成為一鍍金心線。四、 進行第一道抽拉處理：使該鏡金心線經過至少一模座，進 而使該鐘金心線成型為一具有一第二線徑的極細心線。 五、對該極細心線進行檢驗··若該極細心線通過檢驗，該 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐) $ 3頁 , 裝 、一=口..................線. f讀先閲讀背面之逄意事喟再填窝本頁〕 504826 C7 _…―— _D7_ 五、創作説明（2 ) 極細心線即為一可使用於半導體封裝的半導體封裝導線。 且，該半導體封裝導線包含一以具延展性之非純金金屬為 材質的線心’及一均勻地附著於該線心表面且具有適當厚 度的金質鍍層。 【圖式之簡單說明】 本發明之其他特徵及優點，在以下配合參考圖式之較 佳貫施例的洋細說明中’將可清楚的明白，在圖式中： 第一圖是本發明一較佳實施例的製造流程圖； 第二圖是該較佳實施例之一電鍍作業的流程圖； 第三圖是該較佳實施例之一鍍金心線的橫斷面剖視 圖；及 第四圖是該較佳實施例之一製成品的橫斷面剖視圖。 【較佳實施例之詳細說明】 參閱苐一、二、三圖，本發明的一較佳實施例，包含 以下步驟： - . 一、 準備一盤元：該盤元（圖未示）是以具延展性之 非純金金屬為材質，在本實施例中，該盤元可為一純銀線 或一純把線’藉以節省材料成本，且根據試驗結果，此兩 種線材均具有良好的訊號導通率、金屬延展性，且對電鍍 金屬具有良好的附著性。 二、 進行第一道抽拉處理：使該盤元經過至少一模座 (圖未示），進而使該盤元縮減線徑至預定尺寸，而成型為 一具有一第一線徑的心線1 〇，該心線1 〇的第一線徑的大 小範圍為300μηι〜500/zm。 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 第4頁 ------------------------------...........#------------- (請先閲讀背面之注意事項再填寫本頁) 504826 C7 _ _D7_ 五、創作説明（3 ) 二、進行電鍍作業··對該心線1 〇進行電鑛，該電鍍作 業包括以下步驟： (一）、驗性脫脂處理：以驗性電解脫脂劑，去除該 心線10表面的油污、雜質。 (一） 、第一道水洗處理：利用高壓清水喷灑該心線 1 0 ’以將該心線1 〇表面洗淨。 (二） 、酸性活化處理：以酸性藥水對該心線1 0表面 作活化處理。 (四） 、第二道水洗處理：再利用高壓清水喷灑該心 線10 ’將該心線10表面洗淨，藉上述處理步驟，可使該 心線10表面對電鍍金屬產生良好的附著性。 (五） 、鍍金處理··對該心線10進行電鍍，使該心線 10表面均勻鍍上一具有適當厚度，且含有純度99.99%以 上之純金的金質鍍層20，而使該心線1 0成為一鍍金心線 30 ° . (六） 、第三道水洗處理：利用高壓清水喷灑該鍍金 心線3 0 ’將該鍍金心線3 0表面洗淨，以使該鐘金心線3 0 表面光滑潔淨，進而使該鍍金心線3 0可具有良好的訊號導 通率及延展性。 (七） 、封孔後處理··對該鍍金心線3 0表面使用封孔 劑，以防止該鍍金心線30氧化。 (八） 、烘乾：將該鍍金心線3 〇表面烘乾。如此，藉 由上述步驟，以使該鍍金心線3 0具有耐腐蝕性及高訊號導 通率之穩定性。 本紙張尺度適用中國國家標準（CNS) A4規格（210 X 297公釐） 第5頁 (請先閱讀背面之注意事項再填寫本頁) 訂丨 -線丨 C7 一' D7 五、創作説明(4 ) — "一"— — 四、進行第二道抽拉處理：參閱第四圖，使該錢金心 線3〇經過至少一模座（圖未示），進而使該錢金心線3〇 成型為-具有一第二線徑的極細心線4〇，該極細心線仂 的第二線徑的大小範圍為1/zm〜2m。。 ▲五、對該極細心線40進行檢驗：檢驗該極細心線4〇 的訊號導通率、機械特性、線握，及雜質含量等等，若該 極細心線40通過檢驗，該極細心線4〇即為一可使用於半 導體封裝的半導體封裝導線。 多閱第四圖，依上述步驟製成，而可使用於半導體封 裝的該極細心線40包含一以具延展性之純銀或純鈀為材質 的線心41，及一均勻地附著於該線心41表面，且具有適當 厚度並含有純度99.99%以上之純金的金質鍍層42。 經由以上的說明，可再將本發明的優點歸納如下： 一、本發明之該極細心線4〇的線心4 1是以純銀或純鈀 為材質，而只在該線心41的表面電鍍該金質鍍層42，因此， 本發明可有效降低業者的材料成本，根據發明人之成本與 效率估算，本發明與習知的封裝導線相比較，約可降低35 %的整體生產成本，故，本發明可大幅提高業者的競爭力。 一、 本發明之該極細心線4〇的線心4 1是以純銀或純鈀 為材質，根據試驗結果可知純銀或純鈀均具有良好的訊號 ‘通率’且找線心4 1表面又鍍有近純金，而具高訊號導通 率的該金質鍍層42，故，本發明可具有高品質的訊號導通 率 〇 二、 本發明是以線徑較粗的該心線1 0進行電鍍，如此， 本紙張尺度適用中國國家標準（CNS) A4規格（21〇χ297公釐） 第6頁 ………·_#··· (請先閲讀背面之注意事項再填寫本頁) 訂丨 #_ 五、創作説明（5 不僅可避免該心線10於電錢時斷裂，且可提高生產效率。 歸納上述’本發明之^農之盤造方法，不 僅材料成本低廉，且具有高品質的訊號導通率，故 確實能達到發明之目的。 惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明申請專利 粑圍及創作說明書内容所作之簡單的等效變化與修飾，皆 仍屬本發明專利涵蓋之範圍内。 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 第7頁 (請先閲讀背面之注意事項再填寫本頁) 504826 C7 D7 五、創作説明（6【元件標號對照 本發明圖式中之元件標號： 1 0…心線 3 0…鑛金心線 4 0…極細心線 4 1…線心 20…金質鍍層 42…金質鐘層 ί:赫-----------------、可------------ (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS) Α4規格（210X297公釐） 第8頁C7 D7 V. Creative Instructions () " " ^ [Creative Field] This month, there is a coating wire for a semiconductor (such as 1C, LED, etc.), especially a ^^ wire with low cost, and The method of good signal continuity. [Description of Knowing Skills] In order to obtain high-quality signal continuity, the semiconductor package leads of _ 矣 are made of pure gold as a whole. The material characteristics of I 藉藉 I wire can make semiconductors obtain excellent signal continuity during operation. However, the material cost of pure gold is high, which not only causes the overall cost of the industry to be not effectively reduced, but also leads to the Competitiveness has dropped significantly. [Creation summary] Therefore, an object of the present invention is to provide a semiconductor package with low material cost and high-quality signal conductivity. It includes the following steps: 1. Prepare at least one disk element. The disk element is made of ductile non-pure gold metal. 2. Perform the first drawing process: pass the disk element through at least one die seat, and then form the disk element into a heart wire with a first wire diameter. 3. Perform electroplating operation: electroplating the core wire so that the surface of the famous core wire is evenly plated with a gold plating layer to become a gold-plated core wire. 4. Perform the first drawing process: pass the mirror golden core wire through at least one die seat, and then form the bell golden core wire into an extremely fine core wire with a second wire diameter. V. Examination of the extremely careful line ... If the extremely careful line passes the inspection, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) $ 3 pages, installed, one = mouth .... .............. line. F read the meanings on the back and then fill in this page] 504826 C7 _… ―— _D7_ V. Creation Instructions (2) Very careful lines It is a semiconductor package lead that can be used in a semiconductor package. In addition, the semiconductor package lead includes a core 'made of ductile non-pure gold metal and a gold plating layer uniformly attached to the surface of the core and having a proper thickness. [Brief description of the drawings] Other features and advantages of the present invention will be clearly understood in the following detailed description of the preferred embodiments with reference to the drawings. In the drawings: The first drawing is the present invention The manufacturing flowchart of a preferred embodiment; the second figure is a flowchart of an electroplating operation in one of the preferred embodiments; the third figure is a cross-sectional sectional view of a gold-plated core wire in one of the preferred embodiments; and the fourth Figure is a cross-sectional view of a manufactured product according to one of the preferred embodiments. [Detailed description of the preferred embodiment] Referring to Figures 1, 2, and 3, a preferred embodiment of the present invention includes the following steps:-1. Prepare a disk element: the disk element (not shown) is The malleable non-pure gold metal is used as the material. In this embodiment, the disk element can be a pure silver wire or a pure wire to save material costs, and according to the test results, these two wires have good signal conduction. Rate, metal ductility, and good adhesion to electroplated metal. 2. Perform the first drawing process: pass the disk element through at least one die seat (not shown), and then reduce the diameter of the disk element to a predetermined size, and form a core wire with a first diameter The size of the first wire diameter of the heart wire 10 is 300 μm to 500 / zm. This paper size applies to China National Standard (CNS) A4 (210X297 mm) Page 4 ------------------------------ ........... # ------------- (Please read the notes on the back before filling out this page) 504826 C7 _ _D7_ V. Creation Instructions (3) 2 3. Perform electroplating operation. The electroconcentration of the core wire 10 is performed. The electroplating operation includes the following steps: (1) Validation degreasing treatment: Use an electrolytic degreasing agent to remove oil stains and impurities on the surface of the core wire 10. (1) The first water-washing treatment: spray the heart line 10 'with high pressure water to clean the surface of the heart line 10. (B), acid activation treatment: acidic potion on the surface of the heart line 10 for activation treatment. (4) The second water washing treatment: spray the core wire 10 with high pressure water to clean the surface of the core wire 10, and the surface of the core wire 10 can have good adhesion to the electroplated metal by the above processing steps. . (5) Gold-plating treatment ... The core wire 10 is electroplated so that the surface of the core wire 10 is evenly plated with a gold plating layer 20 having a proper thickness and containing pure gold with a purity of 99.99% or more, so that the core wire 1 0 becomes a gold-plated core wire 30 °. (6) The third water washing treatment: spray the gold-plated core wire 3 0 with high pressure water to clean the surface of the gold-plated core wire 30 to make the surface of the gold-plated core wire 3 0 It is smooth and clean, so that the gold-plated core wire 30 can have good signal continuity and ductility. (VII) Post-sealing treatment ... A sealing agent is applied to the surface of the gold-plated core wire 30 to prevent the gold-plated core wire 30 from oxidizing. (8) Drying: The surface of the gold-plated core wire 30 is dried. In this way, through the above steps, the gold-plated core wire 30 is made to have corrosion resistance and high signal conductivity stability. This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) Page 5 (Please read the precautions on the back before filling in this page) Order 丨 -line 丨 C7 I 'D7 V. Creation Instructions (4 ) — &Quot; 一 " —-Fourth, perform the second drawing process: refer to the fourth picture, and pass the money golden heart line 30 through at least one die seat (not shown), and then make the money golden heart line 30 is formed into a very fine wire 40 having a second wire diameter, and the size of the second wire diameter of the very fine wire 仂 ranges from 1 / zm to 2m. . ▲ Fifth, check the extremely careful line 40: check the signal continuity, mechanical characteristics, wire grip, and impurity content of the extremely fine line 40. If the extremely fine line 40 passes the test, the extremely fine line 4 〇 is a semiconductor package lead that can be used for semiconductor packaging. Read the fourth figure and make it according to the above steps. The ultra-fine wire 40 for semiconductor packaging can include a core 41 made of pure silver or palladium with ductility, and a uniformly attached wire. The surface of the core 41 has a gold plating layer 42 having a suitable thickness and containing pure gold with a purity of 99.99% or more. Through the above description, the advantages of the present invention can be summarized as follows: 1. The core 41 of the ultra-fine wire 40 of the present invention is made of pure silver or pure palladium, and only the surface of the core 41 is electroplated. The gold plating layer 42, therefore, the present invention can effectively reduce the material cost of the industry. According to the cost and efficiency estimates of the inventor, the present invention can reduce the overall production cost by about 35% compared with the conventional packaging wire. The invention can greatly improve the competitiveness of the industry. 1. The core 41 of the ultra-fine wire 40 of the present invention is made of pure silver or pure palladium. According to the test results, it can be known that pure silver or pure palladium has a good signal 'through rate', and the surface of the core 4 1 is found again. The gold plating layer 42 is plated with near pure gold and has a high signal conductivity. Therefore, the present invention can have a high-quality signal conductivity. Second, the present invention is electroplated with the thicker core wire 10, In this way, this paper size applies the Chinese National Standard (CNS) A4 specification (21 × 297 mm) Page 6 ... …… __ # ··· (Please read the precautions on the back before filling this page) Order 丨 #_ V. Creation instructions (5 can not only prevent the core wire 10 from breaking when it is used for electricity, but also improve production efficiency. In summary, the above-mentioned method of making agricultural products in the present invention not only has low material costs, but also has high-quality signal conduction. Rate, so it can indeed achieve the purpose of the invention. However, the above are only the preferred embodiments of the present invention. When the scope of the implementation of the present invention cannot be limited in this way, that is, anyone who applies for a patent enclosure and creation specification according to the present invention Simple equivalent of content Changes and modifications are still covered by the patent of the present invention. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) Page 7 (Please read the precautions on the back before filling this page) 504826 C7 D7 V. Creation instructions (6 [component numbers are compared with the component numbers in the drawings of the present invention: 1 0… heart line 3 0… mine gold heart line 4 0… very fine line 4 1… line core 20… gold plating 42… Gold clock layer: He -----------------, may ------------ (Please read the precautions on the back before filling in this page ) This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) Page 8

Claims (1)

504826 本紙張尺度適用中國國家標準（〇^〉Α4規格（210X297公釐） C8 D8 六、申請專利範圍 I 一種半導體封裝導線之製造方法，包含以下步驟： 一、 準備至少一盤元：該盤元是以具延展性之非純 金金屬為材質； 二、 進行第一道抽拉處理：使該盤元經過至少一模 座，進而使該盤元成型為-具有一第一線徑的心線； 一進行電鍍作業^對該心線進行電鍍，使該心線 表面均勻鍍上一具有適當厚度的金質鍍層而成為一鍍金 心線； 四、 進行第二道抽拉處理：使該鍍金心線經過至少 一模座，進而使該鍍金心線成型為一具有一第二線徑的 極細心線； 五、 對該極細心線進行檢驗：若該極細心線通過檢 驗，该極細心線即為一可使用於半導體封裝的半導體封 裝導線。 2. 依據申請專利範、圍第1項所述之半導體封裝導線之製造 方法’其中，該盤元是為純銀線。 3. 依據申請專利範圍第丨項所述之半導體封裝導線之製造 方法’其中，該盤元是為純鈀線。 4·依據申請專利範圍第1項所述之半導體封裝導線之製造 方法，其中，該心線的第一線徑為300 # m〜5〇〇# m。 5·依據申請專利範圍第1項所述之半導體封裝導線之製造 方法’其中’該金質鍍層含有純度99·99%以上的純金。 6·依據申請專利範圍第丨項所述之半導體封裝導線之製造 方法，其中’步驟三的電鍍作業更包括以下步驟： 第9 (請先閲讀背面之注意事項再填寫本頁) .訂· :線丨 504826 申請專刺範圍 -、鹼性脫脂處理：以鹼性電解脫脂劑 線表面的油污、雜質； 二、第一道水洗處理：利用高壓清水喷灑該心線， 線表面洗淨； 酸性活化處理··以酸性筚 注#水對該心線表面作活 Α8 Β8 C8 D8 去除該心 以將該心 二 、 化處理； 四、 苐一道水洗處理：利用；t；殿、主 不J用冋壓清水喷灑該心線， 以將該心線表面洗淨； 五、 鑛金處理··對該心線進行電鍍，使該心線表面 均勻鑛上该金質鍍層而成為該鍍金心線； ’、第一迢水洗處理··利用高壓清水喷灑該鍍金心 線，以將該鍍金心線表面洗淨； 七、 封孔後處理：對該鍍金心線使用封孔劑，以防 止該鍍金心線氧化； 八、 烘乾 '將該鍍金心線烘乾。 - 7.依據申請專利範圍第丨項所述之半導體封裝導線之製造 方法’其中’該極細心線的第二線徑為1 # m〜200 // m。 8 ·依據申請專利範圍第丨項所述之半導體封裝導線之製造 方法’其中’步驟五的檢驗至少包括檢驗該極細 訊號導通率、機械特性，及線徑。 本紙張尺度適用中_家標準（CNS) M規格⑽幻97公董） (請先閲讀背面之注意事項再填寫本頁) •訂- 心線的 第10頁504826 This paper size is applicable to Chinese national standards (〇 ^> A4 size (210X297 mm) C8 D8 VI. Patent application scope I A method for manufacturing semiconductor package wires, including the following steps: 1. Prepare at least one disk element: the disk element It is made of ductile non-pure gold metal. 2. The first drawing process is performed: passing the disk element through at least one die seat, and then forming the disk element into a heart wire with a first wire diameter; A plating operation is performed. The core wire is electroplated, so that the surface of the core wire is evenly plated with a gold plating layer having an appropriate thickness to become a gold-plated core wire. Fourth, the second drawing process is performed: the gold-plated core wire After passing through at least one die seat, the gold-plated core wire is formed into a very fine wire with a second diameter; 5. Inspection of the very fine wire: If the very fine wire passes the test, the very fine wire is A semiconductor package wire that can be used for semiconductor packaging. 2. According to the method of manufacturing a semiconductor package wire described in the patent application, No. 1 item, wherein the disk element is pure 3. According to the method of manufacturing a semiconductor package lead described in item 丨 of the scope of the patent application, wherein the disk element is a pure palladium wire. 4. According to the method of manufacturing the semiconductor package lead described in item 1 of the scope of the patent application. Wherein, the first wire diameter of the core wire is 300 # m to 5〇〇 # m. 5. According to the method for manufacturing a semiconductor package lead described in item 1 of the scope of patent application 'wherein' the gold plating layer has a purity of 99 · More than 99% pure gold. 6 · According to the method for manufacturing semiconductor package leads described in item 丨 of the scope of patent application, the plating process of step 3 includes the following steps: Section 9 (Please read the precautions on the back before filling (This page). Order:: Line 504826 Application for special puncture range-, alkaline degreasing treatment: oil stains and impurities on the surface of alkaline electrolytic degreasing agent line; 2. The first water washing treatment: spray the heartline with high pressure water The surface of the thread is washed; acidic activation treatment ... The surface of the heart thread is activated with an acidic injection of #water. A8 B8 C8 D8 removes the heart to treat the heart; Use; t; the hall, the main body, spray the heart wire with pressurized clean water to clean the surface of the heart wire; 5. Mining gold treatment · The heart wire is electroplated to make the surface of the heart wire even The gold plating layer becomes the gold-plated core wire; ', the first 迢 water-washing treatment · The high-pressure water is used to spray the gold-plated core wire to clean the surface of the gold-plated core wire; 7. Post-sealing treatment: the gold plating The core wire uses a sealing agent to prevent the gold-plated core wire from being oxidized. 8. Drying 'Dry the gold-plated core wire.-7. According to the method of manufacturing a semiconductor package lead described in the item 丨 of the patent application' wherein ' The second wire diameter of this very fine line is 1 # m ~ 200 // m. 8 · According to the method for manufacturing semiconductor package leads described in item 丨 of the scope of the patent application, wherein the inspection of step five includes at least the inspection of the ultra-fine signal continuity, mechanical characteristics, and wire diameter. This paper size is applicable _ Home Standards (CNS) M Specification ⑽ 幻 97 公 董) (Please read the precautions on the back before filling this page) • Order-Heart Line Page 10
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