CN102163595B - 堆叠半导体封装 - Google Patents

堆叠半导体封装 Download PDF

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Publication number
CN102163595B
CN102163595B CN201110032607.4A CN201110032607A CN102163595B CN 102163595 B CN102163595 B CN 102163595B CN 201110032607 A CN201110032607 A CN 201110032607A CN 102163595 B CN102163595 B CN 102163595B
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sub
semiconductor chip
pad
stacked
connection pad
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CN102163595A (zh
Inventor
裵振浩
金基永
南宗铉
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

一种堆叠半导体封装，包括支撑半导体芯片模块的主基板，其中该半导体模块包括至少两个子半导体芯片模块，子半导体芯片模块每一个都具有其中埋设第一半导体芯片的子基板和堆叠在子基板上的至少两个第二半导体芯片。

Description

堆叠半导体封装
技术领域
本发明涉及半导体封装技术，特别是，涉及堆叠半导体封装。
背景技术
在半导体工业中，用于半导体装置的封装技术一直在不断发展，以满足小型化和高性能的要求。近来，已经开发了能够满足小型化、高性能和安装效率要求的各种堆叠半导体封装技术。
述语“堆叠”在半导体工业方法中是指垂直设置至少两个半导体芯片或者半导体封装的技术。在存储装置的情况下，通过采用堆叠技术，能够实现产品的存储容量大于通过通常半导体集成工艺可实现的容量，并且可以改善安装面积利用效率。
然而，为了制造堆叠半导体封装，半导体芯片应当逐个垂直设置。随着半导体芯片堆叠数量的增加，制造堆叠半导体封装所需时间加长，并且必要工艺数量增加。再者，如果在任何一个半导体制造工艺中发生失效，则对应的半导体封装被分类为不良品。因此，在堆叠半导体封装中，发生失效的可能性随着芯片/封装数量增加而增加。例如，如果要堆叠十六个芯片，则芯片附着工艺和引线接合工艺每一个都应当执行十六次。因此，加长了封装制造时间，而且，如果多个工艺中任何一个发生失效，则对应的半导体封装被分类为不良品。就是说，在堆叠半导体封装中，出现失效的可能性成为重要问题。
此外，因为所有堆叠的半导体芯片都应当与一个基板电连接，所以由于半导体芯片中结合焊盘的位置、半导体芯片在基板上的位置、控制器芯片的存在以及基板的面积方面的限制，可能难于或者基本上不可能设计基板。例如，基板的连接焊盘可能仅形成在半导体芯片的两侧，可能不能形成与控制器芯片电连接的连接焊盘。
而且，如果增加要堆叠的半导体芯片的数量，则用于电连接半导体芯片与基板的连接配线需要很长。在此情况下，如果增加连接配线的长度，则出现诸如连接配线间短路或者配线废料的缺陷的可能性增加。当完成封装制造后执行测试时，如果在一个半导体芯片中发生失效，则在封装中可能是良品的所有其它半导体芯片也需要被丢弃，导致半导体芯片良品的浪费以及生产时间的浪费。
发明内容
本发明的实施例涉及堆叠半导体封装，其具有能够缩短制造时间、减少工艺数量和减少失效发生的结构。
在本发明的一个实施例中，堆叠半导体封装包括半导体芯片模块和主基板，该半导体芯片模块包括至少两个子半导体芯片模块，该子半导体芯片模块每一个都具有子基板和至少两个半导体芯片，该子基板具有其上形成有第一子连接焊盘的第一表面和与第一表面背离的第二表面，并且在该子基板中埋设具有与第一子连接焊盘电连接的第一结合焊盘的第一半导体芯片，该至少两个半导体芯片堆叠在第一表面上并且每一个都具有与第一子连接焊盘电连接的第二结合焊盘，该主基板支撑半导体芯片模块，并且具有与各第一子连接焊盘电连接的主连接焊盘。
子基板可以包括：支撑层，附着到第一半导体芯片的第二表面，该第一半导体芯片的第二表面与第一半导体芯片的在其上设置第一结合焊盘的第一表面背离；凸块，形成在第一结合焊盘之上，并且电连接第一结合焊盘与第一子连接焊盘；绝缘层，覆盖支撑层的上表面以及第一半导体芯片，暴露凸块的上端，并且支撑第一子连接焊盘；阻焊剂，形成在绝缘层之上以暴露第一子连接焊盘。
第二半导体芯片可以堆叠为彼此偏移，从而暴露各第二结合焊盘。
堆叠半导体封装还可以包括将第一子连接焊盘和各第二结合焊盘彼此电连接的连接配线。
堆叠半导体封装还可以包括将第一子连接焊盘和主连接焊盘彼此电连接的连接配线。
堆叠半导体封装还可以包括：控制器芯片，附着到半导体芯片模块上，并且具有第三结合焊盘，该第三结合焊盘与构成半导体芯片模块的子半导体芯片模块中的任何一个子半导体芯片模块的第一子连接焊盘电连接。
堆叠半导体封装还可以包括将第三结合焊盘和第一子连接焊盘彼此电连接的连接配线。
包括在子半导体芯片模块中的至少一个子半导体芯片模块的子基板可以包括：第二子连接焊盘，形成在第一表面之上并且与主连接焊盘电连接；控制器芯片，在第一半导体芯片的一侧与第一半导体芯片一起埋设，并且具有与第二子连接焊盘电连接的第三结合焊盘。
包括控制器芯片的子基板可以包括：支撑层，附着到第一半导体芯片的第二表面，该第一半导体芯片的第二表面与第一半导体芯片的在其上设置有第一结合焊盘的第一表面背离；第一凸块，形成在第一结合焊盘之上并且电连接第一结合焊盘与第一子连接焊盘；第二凸块，形成在第三结合焊盘之上并且电连接第三结合焊盘与第二子连接焊盘；绝缘层，覆盖支撑层的上表面以及第一半导体芯片和控制器芯片，暴露第一和第二凸块的上端，并且支撑第一和第二子连接焊盘；阻焊剂，形成在绝缘层之上，以暴露第一和第二子连接焊盘。
堆叠半导体封装还可以包括将主连接焊盘和第二子连接焊盘彼此电连接的连接配线。
堆叠半导体封装还可以包括将第二子连接焊盘和第三结合焊盘彼此电连接的连接配线。
在本发明的另一个实施例中，堆叠半导体封装包括：主基板，具有在其上形成主连接焊盘的上表面和与上表面背离的下表面；至少两个第一半导体芯片，堆叠在该上表面之上，并且具有与主连接焊盘电连接的第一结合焊盘；至少一个子半导体芯片模块，堆叠在第一半导体芯片之上，该子半导体芯片模块具有子基板和至少两个第三半导体芯片，该子基板具有第一表面和与该第一表面背离的第二表面，子连接焊盘形成在第一表面上且与主连接焊盘电连接，并且在该子基板中埋设有第二半导体芯片，该第二半导体芯片具有与子连接焊盘电连接的第二结合焊盘，该至少两个第三半导体芯片堆叠在第一表面之上，并且具有与该子连接焊盘电连接的第三结合焊盘。
子基板可以包括：支撑层，附着到与该第二半导体芯片的在其上设置该第二结合焊盘的一个表面背离的该第二半导体芯片的另一个表面；凸块，形成在该第二结合焊盘之上，并且电连接该第二结合焊盘与该子连接焊盘；绝缘层，覆盖该支撑层的上表面以及该第二半导体芯片，暴露该凸块的上端，并且支撑该子连接焊盘；阻焊剂，形成在该绝缘层之上，以暴露该子连接焊盘。
第一半导体芯片可以堆叠为彼此偏移，从而暴露第一结合焊盘。
堆叠半导体封装还可以包括将主连接焊盘和第一结合焊盘彼此电连接的连接配线。
堆叠半导体封装还可以包括将子连接焊盘和主连接焊盘彼此电连接的连接配线。
第三半导体芯片可以堆叠为彼此偏移，从而暴露第三结合焊盘。
堆叠半导体封装还可以包括将子连接焊盘和各第三结合焊盘彼此电连接的连接配线。
附图说明
图1是示出根据本发明第一实施例的堆叠半导体封装的截面图。
图2是示出图1所示的子半导体芯片模块的结构的示意图。
图3是示出根据本发明第二实施例的堆叠半导体封装的截面图。
图4是示出根据本发明第三实施例的堆叠半导体封装的截面图。
图5A是示出在图4中带有子基板的子半导体芯片模块的结构的示意图，其中该子基板中没有埋设控制器芯片。
图5B是示出在图4中带有子基板的子半导体芯片模块的结构的示意图，其中该子基板中埋设有控制器芯片。
图6是示出根据本发明第四实施例的堆叠半导体封装的截面图。
具体实施方式
在下文，将参考附图详细描述本发明的具体实施例。
这里应当理解的是，附图不一定是按比例绘制的，并且在某些情况下比例可能被扩大，以便更加清晰地表示本发明的某些特征。
图1是示出根据本发明第一实施例的堆叠半导体封装的截面图，而图2是示出图1所示的子半导体芯片模块的结构的示意图。
参考图1，根据本发明第一实施例的堆叠半导体封装100包括半导体芯片模块110、主基板120和第一连接构件130。堆叠半导体封装100还可以包括包封构件140和外部连接端子150。
半导体芯片模块110包括至少两个子半导体芯片模块200。在本实施例中，半导体芯片模块110包括四个子半导体芯片模块200。
参考图2，每一个子半导体芯片模块200都包括其中埋设有第一半导体芯片211并且具有电连接到主基板120的子连接焊盘215的子基板210、堆叠在子基板210上的一个或多个第二半导体芯片220、第二连接构件230。
子基板210包括第一半导体芯片211、支撑层212、凸块213、绝缘层214、子连接焊盘215和阻焊剂216。
第一半导体芯片211具有第一表面211A以及与第一表面211A背离的第二表面211B。例如，第一表面211A可以是顶表面，并且第二表面211B可以是底表面。第一结合焊盘211C形成在第一半导体芯片211的第一表面211A上，并且第一半导体芯片211的第二表面211B通过粘合剂构件217附着到支撑层212。第一半导体芯片211包括位于其中的电路单元（未示出），并且第一结合焊盘211C用作电路单元连接外部的电接触。
凸块213形成在第一结合焊盘211C上。绝缘层214形成来覆盖支撑层212的上表面以及第一半导体芯片211，并且暴露凸块213的上端。子连接焊盘215形成在绝缘层214上，以与凸块213电连接，并且阻焊剂216形成在绝缘层214上，以暴露子连接焊盘215。
在本实施例中，子半导体芯片模块200包括堆叠在子基板210上的三个第二半导体芯片220。这三个第二半导体芯片220通过粘合剂构件240堆叠在子基板210上。每一个第二半导体芯片220都具有第一表面，例如，与子基板210背离的顶表面，以及具有第二表面，例如，与第一表面背离的底表面。第二结合焊盘220A形成在第二半导体芯片220的第一表面上。第二半导体芯片220包括位于其中的电路单元（未示出），并且第二结合焊盘220A用作电路单元连接外部的电接触。
第二半导体芯片220堆叠为彼此偏移，从而暴露第二结合焊盘220A。在本实施例中，第二半导体芯片220堆叠成台阶形状，从而暴露第二结合焊盘220A。
第二连接构件230将包括在不同第二半导体芯片220中的第二结合焊盘220A彼此电连接，并且与子连接焊盘215连接。第二连接构件230可以包括连接配线。
回过来参考图1，半导体芯片模块110具有这样的结构，其中如上所述构造的两个或多个子半导体芯片模块200通过粘合剂构件160彼此接合。在本实施例中，半导体芯片模块110包括四个子半导体芯片模块200。这四个子半导体芯片模块200堆叠为彼此偏移，从而暴露子连接焊盘215（如图2所示）。
半导体芯片模块110通过粘合剂构件160附着到主基板120，并且由主基板120支撑。
主基板120具有面对半导体芯片模块110的上表面120A和背离半导体芯片模块110的下表面120B。主连接焊盘121在半导体芯片模块110两侧形成在主基板120的上表面120A上，并且球焊垫122形成在主基板120的下表面120B上。诸如焊料球的外部连接端子150附着到球焊垫122。
第一连接构件130电连接子半导体芯片模块200的子连接焊盘215与主基板120的主连接焊盘121。第一连接构件130可以包括连接配线。
包封构件140密封主基板120的上表面120A以及半导体芯片模块110。
图3是示出根据本发明第二实施例的堆叠半导体封装的截面图。
根据本发明第二实施例的堆叠半导体封装具有这样的结构，其中控制器芯片170和第三连接构件180被添加至上面参考图1和2描述的根据本发明第一实施例的堆叠半导体封装中。因此，除了控制器芯片170和第三连接构件180外，根据本发明第二实施例的堆叠半导体封装与根据本发明第一实施例的堆叠半导体封装具有基本上相同的结构。因此，这里将省略相同部件的重复描述，并且相同的技术术语和相同的参考标号用于表示相同部件的元件。
参考图3，堆叠半导体封装100包括半导体芯片模块110、主基板120、第一连接构件130、控制器芯片170和第三连接构件180。堆叠半导体封装100还可以包括包封构件140和外部连接端子150。
半导体芯片模块110与上面参考图1和2描述的根据本发明第一实施例的堆叠半导体封装的半导体芯片模块具有基本上相同的结构。
控制器芯片170通过粘合剂构件190附着到半导体芯片模块110。控制器芯片170具有背离半导体芯片模块110的第一表面170A和面对半导体芯片模块110的第二表面170B。控制器芯片170的第二表面170B通过粘合剂构件190附着到半导体芯片模块110，并且第三结合焊盘171形成在控制器芯片170的第一表面170A上。
控制器芯片170包括位于其中的电路单元（未示出），并且第三结合焊盘171用作电路单元连接外部的电接触。
第三结合焊盘171通过第三连接构件180与半导体芯片模块110中包括的多个子半导体芯片模块200中任何一个子半导体芯片模块200的子连接焊盘215电连接。第三连接构件180包括连接配线。
图4是示出根据本发明第三实施例的堆叠半导体封装的截面图，图5A是示出在图4中带有子基板的子半导体芯片模块的结构的示意图，其中该子基板中没有埋设控制器芯片，而图5B是示出在图4中带有子基板的子半导体芯片模块的结构的示意图，其中该子基板中埋设有控制器芯片。
根据本发明第三实施例的堆叠半导体封装与上面参考图1和2描述的根据本发明第一实施例的堆叠半导体封装具有基本上相同的结构，除了子半导体芯片模块具有子基板，而子基板中埋设了控制器芯片之外。因此，这里将省略相同成分元件的重复描述，并且相同的技术术语和相同的参考标号用于表示相同部件的元件。
参考图4，堆叠半导体封装100包括半导体芯片模块110、主基板120和第一连接构件130。堆叠半导体封装100还可以包括包封构件140和外部连接端子150。
参考图4，半导体芯片模块110包括具有其中没有埋设控制器芯片的子基板210的至少一个子半导体芯片模块200以及具有其中埋设有控制器芯片的子基板210A的至少一个子半导体芯片模块200A。
参考图5A，具有其中没有埋设控制器芯片的子基板210的子半导体芯片模块200与图2所示的子半导体芯片模块200具有基本上相同的结构。从而，这里将省略相同部件的元件的重复描述。
参考图5B，具有其中埋设有控制器芯片218的子基板210A的子半导体芯片模块200A与图2所示的子半导体芯片模块200具有基本上相同的结构，除了子基板210A的结构外。因此，这里将省略相同部件的元件的重复描述。
具体地讲，子半导体芯片模块200A的子基板210A，其中埋设了控制器芯片218，包括第一半导体芯片211、支撑层212、第一和第二凸块213A和213B、绝缘层214、第一和第二子连接焊盘215A和215B、阻焊剂216以及控制器芯片218。
第一半导体芯片211具有第一表面211A以及与第一表面211A背离的第二表面211B。第一结合焊盘211C形成在第一半导体芯片211的第一表面211A上，并且第一半导体芯片211的第二表面211B通过粘合剂构件217附着到支撑层212。第一半导体芯片211包括电路单元（未示出），并且第一结合焊盘211C用作电路单元连接外部的电接触。
控制器芯片218以与第一半导体芯片211分开的方式通过粘合剂构件219附着到支撑层212。控制器芯片218具有背离支撑层212的第一表面218A和背离第一表面218A的第二表面218B。第三结合焊盘218C形成在控制器芯片218的第一表面218A上。
第一凸块213A形成在第一半导体芯片211的第一结合焊盘211A上，并且第二凸块213B形成在控制器芯片218的第三结合焊盘218C上。绝缘层214形成为覆盖支撑层212以及第一半导体芯片211和控制器芯片218，并且暴露第一和第二凸块213A和213B的上端。第一子连接焊盘215A形成在绝缘层214上以与第一凸块213A电连接，并且第二子连接焊盘215B形成在绝缘层214上以与第二凸块213B电连接。阻焊剂216形成在绝缘层214上以暴露第一和第二子连接焊盘215A和215B。
图6是示出根据本发明第四实施例的堆叠半导体封装的截面图。
根据本发明第四实施例的堆叠半导体封装100包括半导体芯片模块110、主基板120和第一连接构件130。堆叠半导体封装100还可以包括包封构件140和外部连接端子150。
半导体芯片模块110包括至少两个第四半导体芯片300以及堆叠在第四半导体芯片300上的一个或多个子半导体芯片模块200。在本实施例中，半导体芯片模块110包括四个第四半导体芯片300和三个子半导体芯片模块200，它们堆叠在主基板120上。
第四半导体芯片300通过粘合剂构件400堆叠在主基板120上。每一个第四半导体芯片300都具有背离主基板120的第一表面以及背离第一表面的第二表面。第四结合焊盘310形成在第四半导体芯片300的第一表面上。第四半导体芯片300包括位于其中的电路单元（未示出），并且第四结合焊盘310用作电路单元连接外部的电接触。
第四半导体芯片300堆叠为彼此偏移，从而暴露第四结合焊盘310。在本实施例中，第四半导体芯片300堆叠成台阶形状，从而暴露第四结合焊盘310。
第四连接构件500电连接第四结合焊盘310与主连接焊盘121。第四连接构件500可以包括连接配线。
子半导体芯片模块200通过粘合剂构件160堆叠在第四半导体芯片300上。
子半导体芯片模块200与上面参考图1和2描述的根据第一实施例的堆叠半导体封装具有基本上相同的结构。因此，这里将省略相同部件的元件的重复描述，并且相同的技术术语和相同的参考标号用于表示相同部件的元件。
由上面的描述可见，在本发明的实施例中，因为堆叠半导体封装不仅由芯片的单元构造，而且由子半导体芯片模块的单元构造，子半导体芯片模块的结构中堆叠了多个半导体芯片，所以制造堆叠半导体封装所需的时间可以缩短。再者，因为堆叠半导体封装可以仅采用通过测试分类为良品的子半导体芯片模块构造，所以能够减少发生由于存在于半导体芯片中的失效所导致的堆叠半导体封装中的失效或者在堆叠半导体芯片时所引起的失效。
本申请要求2010年2月5日提交的韩国专利申请号10-2010-10906的优先权，其全部内容通过引用结合于此。
尽管为了说明的目的已经描述了本发明的具体实施例，但是本领域的技术人员应当理解的是，在不脱离权利要求中所述的本发明的范围和精神的情况下，可以进行各种修改、附加和替代。

Claims (17)

1.一种堆叠半导体封装，包括：
半导体芯片模块，至少包括两个子半导体芯片模块，所述子半导体芯片模块每一个都具有子基板以及堆叠在所述子基板上的至少两个第二半导体芯片；以及
主基板，支撑所述半导体芯片模块，
其中，所述子基板包括：
支撑层；
第一半导体芯片，所述第一半导体芯片具有第一表面和与所述第一表面背离的第二表面，所述第一表面上设置有第一结合焊盘，所述第二表面附着到所述支撑层的上表面；
凸块，形成在所述第一结合焊盘之上；
绝缘层，覆盖所述支撑层的上表面以及所述第一半导体芯片，暴露所述凸块的上端；
第一子连接焊盘，形成在所述绝缘层上，并连接至所述凸块；
其中，第二半导体芯片的每一个具有与第一子连接焊盘连接的第二结合焊盘，以及所述主基板具有与相应的第一子连接焊盘连接的主连接焊盘，
其中，所述至少两个子半导体芯片模块彼此堆叠，使得上方的子半导体芯片模块的子基板附着在下方的子半导体芯片模块的最上部的第二半导体芯片上；
其中所述子基板还包括：
第二子连接焊盘，形成在所述第一表面之上并且与所述主连接焊盘电连接；以及
控制器芯片，形成在所述支撑层上，由所述绝缘层覆盖，并且具有与所述第二子连接焊盘电连接的第三结合焊盘。
2.根据权利要求1所述的堆叠半导体封装，其中所述子基板还包括：
阻焊剂，形成在所述绝缘层之上，以暴露所述第一子连接焊盘。
3.根据权利要求1所述的堆叠半导体封装，其中所述第二半导体芯片堆叠为彼此偏移，从而暴露各第二结合焊盘。
4.根据权利要求1所述的堆叠半导体封装，还包括将所述第一子连接焊盘和各第二结合焊盘彼此电连接的连接配线。
5.根据权利要求1所述的堆叠半导体封装，还包括将所述第一子连接焊盘和所述主连接焊盘彼此电连接的连接配线。
6.根据权利要求1所述的堆叠半导体封装，还包括：
控制器芯片，附着到所述半导体芯片模块上并且具有第三结合焊盘，所述第三结合焊盘与构成所述半导体芯片模块的子半导体芯片模块中任何一个子半导体芯片模块的所述第一子连接焊盘电连接。
7.根据权利要求6所述的堆叠半导体封装，其中所述第三结合焊盘和所述第一子连接焊盘通过连接配线彼此电连接。
8.根据权利要求1所述的堆叠半导体封装，其中包括所述控制器芯片的所述子基板还包括：
第二凸块，形成在所述第三结合焊盘之上并且电连接所述第三结合焊盘与所述第二子连接焊盘；以及
阻焊剂，形成在所述绝缘层之上，以暴露所述第一子连接焊盘和第二子连接焊盘。
9.根据权利要求1所述的堆叠半导体封装，还包括将所述主连接焊盘和所述第二子连接焊盘彼此电连接的连接配线。
10.根据权利要求1所述的堆叠半导体封装，还包括将所述第二子连接焊盘和所述第三结合焊盘彼此电连接的连接配线。
11.一种堆叠半导体封装，包括：
主基板，具有上表面和与所述上表面背离的下表面，在所述上表面上形成主连接焊盘；
至少两个第一半导体芯片，堆叠在所述上表面之上，并且具有与所述主连接焊盘电连接的第一结合焊盘；以及
至少一个子半导体芯片模块，堆叠在所述第一半导体芯片之上，
所述子半导体芯片模块具有子基板和至少两个第三半导体芯片，所述子基板具有第一表面和与所述第一表面背离的第二表面，子连接焊盘形成在所述第一表面上且与所述主连接焊盘电连接，并且在所述子基板中埋设有第二半导体芯片，所述第二半导体芯片具有与所述子连接焊盘电连接的第二结合焊盘，所述至少两个第三半导体芯片堆叠在所述第一表面之上，并且具有与所述子连接焊盘电连接的第三结合焊盘。
12.根据权利要求11所述的堆叠半导体封装，其中所述子基板包括：
支撑层，附着到与所述第二半导体芯片的在其上设置所述第二结合焊盘的一个表面背离的所述第二半导体芯片的另一个表面；
凸块，形成在所述第二结合焊盘之上并且电连接所述第二结合焊盘与所述子连接焊盘；
绝缘层，覆盖所述支撑层的上表面以及所述第二半导体芯片，暴露所述凸块的上端，并且支撑所述子连接焊盘；以及
阻焊剂，形成在所述绝缘层之上，以暴露所述子连接焊盘。
13.根据权利要求11所述的堆叠半导体封装，其中所述第一半导体芯片堆叠为彼此偏离，从而暴露所述第一结合焊盘。
14.根据权利要求11所述的堆叠半导体封装，还包括将所述主连接焊盘和所述第一结合焊盘彼此电连接的连接配线。
15.根据权利要求11所述的堆叠半导体封装，还包括将所述子连接焊盘和所述主连接焊盘彼此电连接的连接配线。
16.根据权利要求11所述的堆叠半导体封装，其中所述第三半导体芯片堆叠为彼此偏离，从而暴露所述第三结合焊盘。
17.根据权利要求11所述的堆叠半导体封装，还包括将所述子连接焊盘和各第三结合焊盘彼此电连接的连接配线。
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