CN105556648B - 集成电路封装衬底 - Google Patents

集成电路封装衬底 Download PDF

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Publication number
CN105556648B
CN105556648B CN201380079633.XA CN201380079633A CN105556648B CN 105556648 B CN105556648 B CN 105556648B CN 201380079633 A CN201380079633 A CN 201380079633A CN 105556648 B CN105556648 B CN 105556648B
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finishing layer
surface finishing
package substrate
tube core
electrical wiring
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CN105556648A (zh
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张青磊
S·M·洛茨
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Intel Corp
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Intel Corp
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
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    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31Coating with metals
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Abstract

本公开的实施例涉及用于双表面精整层封装衬底组件的技术和配置。在一个实施例中,方法包括:在封装衬底的第一侧上沉积第一层压层和在设置在封装衬底的第二侧上的一个或多个电触点上沉积第一表面精整层;从封装衬底的第一侧去除第一层压层;在封装衬底的第二侧上沉积第二层压层和在设置在封装衬底的第一侧上的一个或多个电触点上沉积第二表面精整层;以及从封装衬底的第二侧去除第二层压层。可描述其他实施例并且/或者要求它们的权利。

Description

集成电路封装衬底
技术领域
本公开的实施例一般涉及集成电路的领域,并且更具体地,涉及用于集成电路封装衬底的表面精整层(surface finishes)的技术和配置。
背景技术
管芯(诸如,处理器)的输入/输出密度持续增加。为了跟上增加的输入/输出密度,管芯所附连的封装衬底必须相应地缩放。在本领域的当前状态下,单个表面精整层被应用到封装衬底的管芯和焊盘侧两者。封装衬底的管芯侧是其上附连管芯的一侧,而封装衬底的焊盘侧附连至电路板。在应用之后单个精整层可横向生长、或扩张,从而如果焊盘过于紧密地位于一起可导致在衬底的管芯侧上的焊垫到焊垫桥接。作为结果,在管芯侧上的表面精整层的扩展限制了封装衬底的可缩放性。然而,可基于关于电路板连接要求的考虑确定在焊盘侧上的表面精整层组分。这些考虑不一定延伸到管芯侧连接要求;然而,在本领域的当前状态下,相同表面精整层被应用到封装衬底的管芯侧和焊盘侧两者。
附图简述
通过下列具体实施方式并结合所附附图,可容易地理解实施例。为了便于该描述,同样的参考标号指定同样的结构元件。在所附附图的图中以示例方式而不以限制方式说明实施例。
图1示意性地示出了根据一些实施例的示例集成电路(IC)组件的截面侧视图。
图2是根据本公开的实施例的利用双表面精整层的封装衬底制造过程的示例性流程图。
图3为根据本公开的实施例的示出了图2中描述的封装衬底制造过程中的阶段的所选操作的示例性截面图。
图4为根据本公开的实施例的利用具有双表面精整层的封装衬底的组装过程的示例性流程图。
图5示意性地示出了根据一些实施例的包括具有双表面精整层的封装衬底的计算设备。
详细描述
本公开的实施例描述了用于双表面精整层封装衬底组件的技术和配置。在以下描述中,将使用本领域技术人员所通常使用的术语来描述示例性实现的各个方面,以向其他本领域技术人员传达它们的工作的实质。然而,对本领域技术人员将显而易见的是,仅采用所描述方面中的一些也可实施本公开的实施例。为了说明的目的,陈述具体的数字、材料和配置以提供对示例性实现的全面理解。然而,本领域技术人员将可理解,没有这些特定细节也可实施本公开的实施例。在其他实例中,省略或简化已知特征以不模糊示例性实现。
在以下详细描述中,参照形成本说明书的一部分的附图,其中在全部附图中相同的标记指示相同的部件,并且在附图中以可实施本发明的主题的示例实施例的方式显示。应当理解,也可利用其它实施例,并且也可对其他实施例作出结构或逻辑的改变而不背离本公开的范围。因此,下列具体实施方式不应当被认为是限制意义的,并且实施例的范围由所附权利要求及其等效方案来定义。
为本公开之目的,短语“A和/或B”表示(A)、(B)或(A和B)。为本公开之目的,短语“A、B、和/或C”表示(A)、(B)、(C)、(A和B)、(A和C)、(B和C)或(A、B和C)。
说明书可使用基于视角的描述,诸如顶部/底部、内/外、上/下等等。这种描述仅用于便于讨论并且不旨在将本文所描述的实施例的应用限制在任何特定方向。
说明书可使用短语“在一实施例中”或“在诸实施例中”,其中每个可指相同或不同实施例中的一个或多个。此外,就本公开的多个实施例而言所使用的术语“包含”、“包括”、“具有”等是同义的。
本文可使用术语“与……耦合”及其派生词。“耦合”可表示以下一个或多个。“耦合”可表示两个或两个以上元件直接物理或电接触。然而,“耦合”还可表示两个或两个以上元件彼此间接接触,但仍彼此协作或交互,以及可表示一个或多个其他元件被耦合或连接在被认为彼此耦合的元件之间。术语“直接耦合”可表示两个或两个以上元件直接接触。
在各个实施例中,短语“在第二特征上形成、沉积或以其他方式设置的第一特征”,可表示第一特征被形成、沉积、或设置在第二特征之上,并且第一特征的至少一部分可与第二特征的至少一部分直接接触(例如,直接物理和/或电接触)或间接接触(在第一特征和第二特征之间具有一个或多个其他特征)。
如本文所使用的,术语“模块”可指执行一个或多个软件或固件程序的专用集成电路(ASIC)、电子电路、片上系统(SoC)、处理器(共享、专用或组)和/或存储器(共享、专用或组)、组合逻辑电路和/或提供所描述功能的其它合适的组件,或是上述部件的一部分,或包括上述部件。
图1示意性地示出了示例集成电路(IC)组件100的截面侧视图,示例集成电路组件100被配置成在嵌入在封装衬底104中的电布线(routing)特征上使用双表面精整层。在一些实施例中,IC组件100可包括一个或多个管芯(例如,管芯102a或102b),如可看到的,一个或多个管芯与封装衬底104电和/或物理耦合。如可看到的,封装衬底104可进一步与电路板122电且物理地耦合。如本文所使用的,封装衬底的管芯侧是管芯所附连的一侧(例如,侧S1),而封装衬底的焊盘侧是附连至电路板的一侧(例如,侧S2)。在一些实施例中,IC封装组件100可仅指的是封装衬底104。
根据各个实施例,第一表面精整层可设置在电布线特征上,诸如封装衬底104的侧S2上的一个或多个焊盘上。第二表面精整层可设置在如本文所描述的侧S1的电布线特征上(例如,图3的表面精整层322)。可在IC组件100中配置第二表面精整层以通过IC组件100的各个部件路由管芯102a和/或102b的电信号。电信号可包括,例如,输入输出(I/O)信号、射频(RF)信号或与管芯102a和/或102b的操作相关联的电源/接地。该第二表面精整层可具有与第一表面精整层不同的化学组分。例如,虽然第一表面精整层可以是镍基,而在一些实施例中第二表面精整层是金基,诸如使用直接浸金(DIG)工艺所应用的金基。
管芯102a和102b可根据各种合适的配置附连至封装衬底104,各种合适的配置包括,所描绘的倒装芯片配置、或诸如例如被嵌入在封装衬底104中或以引线接合布置配置的其他配置。在倒装芯片配置中,管芯102a或102b中的一个或两者可使用互连结构106(诸如,凸块、柱、或也可将管芯102a和102b与封装衬底104电耦合的其他合适结构)附连至具有第二表面精整层的封装衬底104的表面。如以下进一步讨论的,该第二表面精整层可能够使管芯互连结构106比使用封装衬底104的侧S 1和S2两者上的单个表面精整层将可能的更紧密地间隔开并由此允许增加的输入输出密度。
在一些实施例中,管芯102a或102b可表示由半导体材料制造的分立芯片,并且可包括以下部件或作为以下部件的一部分:处理器、存储器、或ASIC。例如,在一些实施例中,诸如模制化合物或底部填充材料(未示出)之类的电绝缘材料可部分地或全部地封装管芯102a或102b的部分、和/或互连结构106。管芯互连结构106可被配置成在管芯102a、管芯102b、和/或封装衬底104之间路由电信号。
封装衬底104可包括配置成路由去往或来自管芯102a和/或102b的电信号。电布线特征可包括,例如,设置在封装衬底104的一个或多个表面上的迹线和/或内部布线特征,例如,内部布线特征诸如沟槽、通孔或用于穿过封装衬底104路由电信号的其他互连结构。在实施例中,电布线特征可被嵌入到一个或多个管芯互连区域116。在实施例中,管芯互连区域116可以是硅贴片。例如,在一些实施例中,封装衬底104可包括电布线特征(诸如,管芯接合焊垫108),该电布线特征具有应用在其上的第二表面精整层,配置成通过嵌入在管芯102a、管芯102b、和/或封装衬底104之间的管芯互连区域116中的导电线容纳管芯互连结构106并路由电信号。
在一些实施例中,例如,封装衬底104为具有芯(图3的中央芯304)和/或建立层的基于环氧树脂的层压衬底,诸如Ajinomoto建立膜(ABF)衬底。封装衬底104可包括在其他实施例中的其他合适类型的衬底,包括例如由玻璃、陶瓷、或半导体材料形成的衬底。
电路板122可以为由电绝缘材料(诸如环氧层压板)构成的印刷电路板(PCB)。例如,电路板122可包括由诸如聚四氟乙烯、酚树脂醛棉纸材料(诸如,阻燃剂4(FR-4)、FR-1、棉纸和环氧材料(诸如,CEM-1或CEM-3)、或利用环氧树脂预浸材料层叠一起的编织的玻璃材料组成的电绝缘层。可穿过电绝缘材料形成结构(未描绘)(例如通孔)用于通过电路板122路由管芯102a或102b中的任一个的电信号。在其他实施例中,电路板122可由其他合适的材料组成。在一些实施例中,电路板122是母板(例如,图5的母板502)。
例如,封装级互连(诸如焊球12)可耦合至封装衬底104上的一个或多个焊盘(land)(在下文中“焊盘110”)和电路板122上的一个或多个焊垫114以形成对应的焊接结合点,该焊接接合点配置成进一步路由在封装衬底104和电路板122之间的电信号。例如,可以球栅阵列(BGA)布置配置焊球112。在一些实施例中,焊盘110可具有设置在其上的第一表面精整层。第一表面精整层可由任何合适的导电材料(诸如包括例如,镍(Ni)、钯(Pd)、金(Au)、银(Ag)、铜(Cu)、和它们的组合的金属)组成。可在其他实施例使用用于将封装衬底104与电路板122物理和/或电耦合的其它合适的技术,包括例如平面网格阵列(LGA)结构。
图2是根据本公开的实施例的用于应用双表面精整层的封装衬底制作过程200的部分的示例性流程图。图3提供示出了根据示例性实施例的封装衬底制造过程200中的阶段的所选操作的截面图。因此,图2和图3将彼此结合进行描述。为了有助于该描述,在图2中执行的操作参照从图3中的操作移动到操作的箭头。此外,不是所有的附图标记都在图3中的每个操作中被描绘。
封装衬底制造过程200可开始于操作201,其中可提供用于应用双表面精整层的封装衬底。所提供的衬底可包括具有设置在其上的电介质层(例如,图3的电介质层302和306)的芯(例如,图3的中央芯304)。电介质层可具有嵌入在其中的图案化金属层(例如,图3的图案化金属层)。一般而言,可以本领域已知的任何方式形成图案化金属层和在图案化金属层下面的任何数量的层。例如,图案化金属层可以是采用半加成工艺(SAP)形成的顶部建立层。电介质层可以是本领域已知的任何组分并且可以任何常规方式被应用于图案化子表面(sub-surface)级金属层。例如,在一些实施例中,电介质层可包括聚合物(环氧基树脂),可具有二氧化硅填料以提供满足封装的可靠性要求的合适的机械性质。
衬底可具有管芯侧(例如,图3的管芯侧S1),该管芯侧被配置成具有设置在其上的一个或多个管芯(例如,图1的102a和102b)。在实施例中,衬底可具有一个或多个焊垫(例如,图3的312a-b和314a-b),管芯可附连至该一个或多个焊垫。在实施例中,焊垫可包括铜或任何其他合适的导电材料。衬底可具有嵌入在其中的一个或多个管芯互连区域(例如,图3的管芯互连区域310)。管芯互连区域可具有设置在其上的一个或多个导电焊垫(例如,图3的铜焊垫)。管芯互连区域的焊垫可电连接至表面级金属(例如,图3的焊垫312a-b)。管芯互连区域可具有嵌入在其中的导电线(未描绘)。导电线可建立设置在管芯互连区域上的导电焊垫之间的电连接。在一些实施例中,管芯互连区域可包括硅,诸如硅贴片或桥。
衬底可具有焊盘侧,该焊盘侧具有设置在其上的一个或多个焊盘(例如,图3的焊盘316a-d)。焊盘侧可被配置成经由一个或多个焊盘附连至一个或多个电路板。可以本领域已知的任何方式形成衬底,诸如以上所描述的衬底。例如,通过建立工艺,诸如半加成工艺。
在操作203处,可在封装衬底的管芯侧和/或焊盘侧上层叠阻焊剂(例如,图3的管芯侧阻焊剂318a和焊盘侧阻焊剂318b)。阻焊剂可被应用于保护不受氧化并防止焊盘到焊盘桥接。可通过丝网印刷、喷涂或真空层压工艺应用阻焊剂。阻焊剂可以是任何合适的材料,包括但不限于,液态光成像焊料掩模(LPSM)和/或干膜光成像焊料掩模(DFSM)。
在已施加阻焊剂之后,在操作205处可形成阻焊剂开口。可通过光刻或任何其他合适的工艺形成阻焊剂开口。可在表面级金属触点上形成阻焊剂开口以能够对表面级金属触点应用表面精整层。开口也可被形成为使管芯能够经由管芯侧表面级金属触点附连至封装衬底(例如,图1的管芯102a-b)或使封装衬底能够经由焊盘侧表面级金属触点附连至电路板(例如,图1的电路板122)。
在操作207处,可将保护层压层(例如,图3的保护层压层320)应用至焊盘侧。保护层压层可以是任何合适的材料,诸如,但不限于聚对苯二甲酸乙二酯(PET)。该保护层压层可防止在管芯侧表面级金属触点上沉积表面精整层。
在操作209处,在通过形成阻焊剂开口暴露的表面级金属触点(例如,图3的焊盘316a-d)的暴露表面上形成第一表面精整层金属(例如,图3的表面精整层322)。根据各个实施例,第一表面精整层金属具有与焊盘不同的材料组分。可采用各种表面精整层金属组分或电镀堆叠。在图3所描绘的示例性实施例中,化学镀过程用于形成表面精整层322,该表面精整层322包括任何合适的导电材料,诸如包括例如,镍(Ni)、钯(Pd)、金(Au)、银(Ag)、铜(Cu)、和它们的组合的金属。在示例性实施例中,表面精整层322包括6-8微米(μm)厚的镍层。
在操作211处,可去除在管芯侧上的保护层压层(例如,图3的保护层压层320),以及在操作213处,可将保护层压层(例如,图3的保护层压层324)应用至焊盘侧。在焊盘侧上的保护层压层可防止在焊盘侧表面精整层上沉积表面精整层。
在操作215处,可在管芯侧的表面级金属触点(图3的焊垫312a-b和314a-b)的暴露表面上形成第二表面精整层(例如,图3的表面精整层326)。该第二表面精整层可通过诸如直接浸金(DIG)工艺、有机可焊性保护(OSP)工艺、和/或化学镀钯浸金(EPIG)工艺之类的工艺沉积。在实施例中,第二表面精整层可具有与第一表面精整层不同的化学组分。在一些实施方案中,该第二表面精整层可由金、钯、和/或咪唑、或咪唑衍生物(诸如,但不限于,苯并咪唑或苯基)组成。在示例性实施例中,第二表面精整层可小于0.5μm(500纳米(nm))厚。在OSP、DIG、或EPIG工艺中,第二表面精整层(例如,表面精整层326)可在从60nm至300nm的厚度范围内。在操作217处,可去除在焊盘侧上的保护层压层(例如,图3的保护层压层324)。
在一些实施例中,在连接点处的表面精整层的临界尺寸(CD)、或最小横向宽度可至少与焊垫(例如,图3的焊垫312a-b和314a-b)的最大直径一样大;然而,由于第二表面精整层可为小于500nm厚度,因此可减少在管芯侧焊垫上的表面精整层金属的横向膨胀。从而允许相邻焊垫直接的空间的减少。例如,在连接点具有贴片(例如,凸块贴片)的情况下,该最小化的表面精整层的横向膨胀可实现55μm凸块贴片或55μm以下凸块贴片,其中焊垫尺寸为43μm,从而将提供比本领域的当前状态下可能的更高的I/O路由密度。
虽然以上过程描述了第一表面精整层到焊盘侧的应用,接着描述了第二表面精整层到管芯侧的应用,但也可以相反的顺序执行该过程。例如,可将第二表面精整层应用至封装衬底的管芯侧,接着将第一表面精整层应用至封装衬底的焊盘侧。
图4为根据本公开的实施例的利用具有双表面精整层的封装衬底的组装过程400的示例性流程图。可通过以上参考图2描述的示例性方法生产并且可在图3中描绘这种封装衬底。
组装过程400开始于操作401,在操作401处接收具有在预定衬底连接点处的暴露的表面精整层的封装衬底。同样,在示例性实施例中,在将芯片耦合至封装衬底之前,在封装衬底的表面上不存在阻焊剂,并且没有焊料位于表面精整层上。可在图3中描绘示例性封装衬底。
在操作402处,IC芯片可容纳有设置在芯片连接点上的焊料凸块。虽然IC芯片可通常是任何常规类型,但在一些实施例中,IC芯片可以是具有大I/O计数的处理器,诸如微处理器。在实施例中,如以上所描述的,芯片I/O和电源焊料凸起可具有55μm的贴片。在操作410处,IC芯片可与表面平整的衬底对齐以使焊接的IC芯片连接点与表面平整的衬底连接点对齐。然后在操作420处使芯片侧焊料熔合以将芯片贴装至衬底连接点,从而完成封装430。
可在使用任何合适硬件和/或软件按需配置的系统中实现本公开的实施例。图5示意性地示出了根据一些实施例的计算设备,该计算设备包括如本文所描述的封装衬底,诸如,通过图3所描绘的封装衬底。计算设备500可容纳诸如母板502之类的板。母板502可包括多个部件,该多个部件包括,但不限于,处理器504和至少一个通信芯片506。处理器504可物理且电耦合至母板502。在一些实施例中,至少一个通信芯片506还可物理且电耦合至母板502。在进一步实现中,通信芯片506可以是处理器504的一部分。
根据其应用,计算设备500可包括可能或可能不物理且电耦合至母板502的其他部件。这些其它组件可包括,但不限于,易失性存储器(例如,DRAM)、非易失性存储器(例如,ROM)、闪存、图形处理器、数字信号处理器、加密处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码解码器、视频编码解码器、功率放大器、全球定位系统(GPS)装置、指南针、盖革(Geiger)计数器、加速度计、陀螺仪、扬声器、照相机以及大容量存储装置(诸如硬盘驱动器、紧凑盘(CD)、数字多功能盘(DVD)等等)。
通信芯片506可实现无线通信以供将数据转移至计算设备500或转移来自计算设备800的数据。术语“无线”及其衍生词可用于描述通过使用经调制的电磁辐射经由非固态介质来传递数据的电路、设备、系统、方法、技术、通信信道等。尽管在一些实施例中相关联的设备可能不包含任何线,但是该术语并不暗示相关联的设备不包含任何线。通信芯片506可实现任何数量的无线标准或协议,无线标准或协议包括,但不限于,电子与电气工程师协会(IEEE)标准(包括Wi-Fi(IEEE802.11家族)、IEEE 802.16标准(例如,IEEE 802.16-2005修改))、长期演进(LTE)项目连同任何修改、更新和/或修订版本(例如,先进的LTE项目、超移动宽带(UMB)项目(也被称为“3GPP2)等等)。”可兼容BWA网络的IEEE 802.16一般被称为WiMAX网络,WiMAX代表全球微波接入互操作性的首字母缩写,是用于通过针对IEEE 802.16标准的整合和互操作性测试的产品的认证标志。通信芯片506可根据全球移动通信(GSM)系统、通用分组无线业务(GPRS)、通用移动电信系统(UMTS)、高速链路分组接入(HSPA)、演进的HSPA(E-HSPA)、或LTE网络操作。通信芯片506可根据用于GSM演进的增强型数据(EDGE)、GSM EDGE无线电接入网络(GERAN)、通用陆地无线接入网络(UTRAN)或演进的UTRAN(E-UTRAN)操作。通信芯片506可根据码分多址(CDMA)、时分多址(TDMA)、数字增强型无绳通信(DECT)、演进数据优化(EV-DO)、它们的衍生物、以及指定用于3G、4G、5G及以上的任何其他无线协议操作。在其他实施例中,通信芯片506可根据其他无线协议操作。
计算设备500可包括多个通信芯片506。例如,第一通信芯片506可专用于较短程的无线通信,如,Wi-Fi和蓝牙;第二通信芯片506可专用于较长程的无线通信,如,GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
计算设备500的处理器504可封装在包括如本文中所描述的封装衬底的IC组件(例如,图1的封装组件100)中。例如,图1的电路板122可以为母板502而处理器504可以为安装在本文中所描述的封装衬底104上的管芯102。封装衬底104和母板502可利用本文所描述的封装级互连结构耦合在一起。术语“处理器”可指的是任何设备或设备的一部分,其处理来自寄存器和/或存储器的电子数据,以将该电子数据转换成可存储于寄存器和/或存储器中的其它电子数据。
通信芯片506还可包括可封装在包括如本文所描述的封装衬底的IC组件(例如,图1的封装组件100)中的管芯(例如,图1的管芯102)。在进一步实现中,容纳在计算设备500中的另一部件(例如,存储器设备或其他集成电路设备)可包括可封装在包括如本文所描述的封装衬底104的IC组件(例如,图1的IC组件100)中的管芯(例如,图1的管芯102)。
在多个实现中,计算设备500可以是膝上型计算机、上网本、笔记本、超极本、智能手机、平板、个人数字助理(PDA)、超移动PC、移动电话、桌面计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字照相机、便携式音乐播放器或数字视频记录仪。在进一步的实现方案中,计算设备500可以是处理数据的任何其他电子设备。
示例
根据各个实施例,本公开描述了多个示例。示例1为形成集成电路(IC)封装衬底的方法,包括:在封装衬底的第一侧上沉积第一层压层以及在设置在封装衬底的第二侧上的一个或多个电触点上沉积第一表面精整层,其中第一侧与第二侧相对设置,并且第一层压层用于防止在设置在第一侧上的一个或多个电触点上沉积第一表面精整层;将第一层压层从封装衬底的第一侧去除以暴露设置在第一侧上的一个或多个电触点;在封装衬底的第二侧上沉积第二层压层以及在设置在封装衬底的第一侧上的一个或多个电触点上沉积第二表面精整层,其中第二层压层用于防止在设置在第二侧上的一个或多个电触点上沉积第二表面精整层;以及从封装衬底的第二侧去除第二层压层。
示例2可包括示例1的主题,其中通过直接浸金(DIG)工艺完成第一表面精整层的沉积,以及设置在第二侧上的一个或多个电触点包括管芯接合焊垫。
示例3可包括示例1的主题,其中通过化学镀钯浸金(EPIG)工艺完成第一表面精整层的沉积,以及设置在第二侧上的一个或多个电触点包括管芯接合焊垫。
示例4可包括示例1的主题,其中通过有机可焊性保护(OSP)工艺完成第一表面精整层的沉积,以及设置在第二侧上的一个或多个电接触包括管芯接合焊垫。
示例5可包括示例1-4中的任一个的主题,其中使用化学镀工艺来完成沉积第二表面精整层,以及设置在第二侧上的一个或多个电触点包括一个或多个焊盘。
示例6可包括示例1-4中的任一个的主题,其中沉积第二表面精整层包括沉积镍(Ni),以及设置在第二侧上的一个或多个电触点包括一个或多个焊盘。
示例7可包括示例6的主题,其中沉积第二表面精整层进一步包括沉积钯或金中的一个或两者。
示例8可包括示例7的主题,其中沉积第二表面精整层包括使用化学镀镍浸金(ENIG+EG)工艺沉积金。
示例9为封装衬底,包括:第一侧,该第一侧包括一个或多个焊盘,该一个或多个焊盘具有设置在一个或多个焊盘上的第一表面精整层;以及第二侧,该第二侧与第一侧相对设置,该第二侧具有管芯互连区域,该管芯互连区域具有嵌入在其中的一个或多个电布线特征,该一个或多个电布线特征具有设置在一个或多个电布线特征上并且与其直接接触的第二表面精整层,其中电布线特征被配置成与一个或多个管芯的管芯互连结构接合,并且第二表面精整层具有与第一表面精整层不同的化学组分。
示例10可包括示例9的主题,其中第一表面精整层是在一个或多个焊盘上的最外层表面精整层,以及第二表面精整层是在一个或多个电布线特征上的最外层表面精整层。
示例11可包括示例9的主题,其中第二表面精整层是咪唑或咪唑衍生物。
示例12可包括示例9的主题,其中第二表面精整层为金。
示例13可包括示例9的主题,其中第二表面精整层是钯和金的组合。
示例14可包括示例9的主题,其中第二表面精整层具有小于或等于500纳米的厚度。
示例15可包括示例9的主题,其中第一表面精整层包括镍(Ni)。
示例16可包括示例15的主题,其中第一表面精整层进一步包括钯(Pd)或金(Au)中的一个或两者。
示例17可包括示例9的主题,其中管芯互连区域被设置在电介质层中。
示例18可包括示例9的主题,其中管芯互连区域包括硅桥。
示例19可包括示例9的主题,其中管芯互连区域的一个或多个电布线特征路由在连接至封装衬底的第一管芯和连接至封装衬底的第二管芯之间的电信号。
示例20为封装组件,包括:集成电路(IC)芯片,该集成电路芯片具有一个或多个输入输出(I/O)连接点和一个或多个电源连接点;以及封装衬底,该封装衬底包括:包括一个或多个焊盘的第一侧,该一个或多个焊盘具有设置在一个或多个焊盘上的第一表面精整层;以及与第一侧相对设置的第二侧,第二侧具有嵌入在其中的硅连接区域,该硅连接区域具有嵌入在其中的一个或多个电布线特征,一个或多个电布线特征具有设置在一个或多个电路由特征上并且与其直接接触的第二表面精整层,其中第二表面精整层具有与第一表面精整层不同的化学组分,并且该第二表面精整层电连接至一个或多个I/O连接点或一个或多个电源连接点。
示例21可包括示例20的主题,其中IC芯片为处理器。
示例22可包括示例20的主题,进一步包括与电路板耦合的天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)设备、指南针、盖革计数器、加速度计、陀螺仪、扬声器,或相机中的一个或多个,其中封装组件是膝上型计算机、上网本、笔记本电脑、超级本电脑、智能电话、平板电脑、个人数字助理(PDA)、超移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字相机、便携式音乐播放器,或者数字录像机中的一个或多个。
示例23为用于形成集成电路(IC)封装衬底的设备,包括:用于在封装衬底的第一侧上沉积第一层压层和在设置在封装衬底的第二侧上的一个或多个电触点上沉积第一表面精整层的装置,其中第一侧与第二侧相对设置,以及第一层压层用于防止在设置在第一侧上的一个或多个电触点上沉积第一表面精整层;用于从封装衬底的第一侧去除第一层压层以暴露设置在第一侧上的一个或多个电触点的装置;用于在封装衬底的第二侧上沉积第二层压层并在设置在封装衬底的第一侧上的一个或多个电触点上沉积第二表面精整层的装置,其中第二层压层用于防止在设置在第二侧上的一个或多个电触点上沉积第二表面精整层;以及用于从封装衬底的第二侧去除第二层压层的装置。
示例24可包括示例23的主题,其中用于沉积第一表面精整层的装置进一步包括用于执行直接浸金(DIG)工艺的装置,以及设置在第二侧上的一个或多个电触点包括管芯接合焊垫。
示例25可包括示例23的主题,其中用于沉积第一表面精整层的装置进一步包括用于执行化学镀钯浸金(EPIG)工艺的装置,以及设置在第二侧上的一个或多个电触点包括管芯接合焊垫。
示例26可包括示例23的主题,其中用于沉积第一表面精整层的装置包括用于执行有机可焊性保护(OSP)工艺的装置,以及设置在第二侧上的一个或多个电触点包括管芯接合焊垫。
示例27可包括示例23-26中的任一个的主题,其中用于沉积第二表面精整层的装置进一步包括用于执行化学镀工艺的装置,以及设置在第二侧上的一个或多个电触点包括一个或多个焊盘。
示例28可包括示例23-26中的任一个的主题,其中用于沉积第二表面精整层的装置包括用于沉积镍(Ni)的装置,以及设置在第二侧上的一个或多个电触点包括一个或多个焊盘。
示例29可包括示例28的主题,其中用于沉积第二表面精整层的装置进一步包括用于沉积钯或金中的一个或两者的装置。
示例30可包括示例29的主题,其中用于沉积第二表面精整层的装置包括用于使用化学镀镍浸金(ENIG+EG)工艺沉积金的装置。
示例31可包括示例23的装置,其中设置在第二侧上的一个或多个电触点包括管芯接合焊垫,以及用于沉积第一表面精整层的装置进一步包括:用于执行直接浸金(DIG)工艺的装置、用于执行化学镀钯浸金(EPIG)工艺的装置、或用于执行有机可焊性保护(OSP)工艺的装置中的一个。
所示的实现的上述描述、包括摘要中的描述的不旨在穷举或将本公开的实施例限制为所公开的精确形式。虽然为了说明目的在本文中描述了特定实现和示例,但如相关领域技术人员将认识到的,在本发明的范围内有许多等效修改是可能的。
鉴于以上详细描述,可对本公开的实施例进行这些修改。下面权利要求中使用的术语不应当解释成将本公开的各个实施例限定于说明书和权利要求书所披露的特定实现。相反,本发明的范围完全由所附权利要求确定,所附权利要求将根据已确立的权利要求解释原则来解读。

Claims (24)

1.一种形成集成电路IC封装衬底的方法,包括:
在设置在所述封装衬底的第一侧上的一个或多个焊盘上沉积第一表面精整层,其中所述衬底的所述第一侧与第二侧相对设置;以及
在设置在所述封装衬底的所述第二侧上的管芯互连区域中嵌入的一个或多个电布线特征上沉积第二表面精整层,所述第二表面精整层与所述一个或多个电布线特征直接接触,其中所述电布线特征与一个或多个管芯的管芯互连结构接合,其中所述一个或多个电布线特征包括设置在所述第二侧上的管芯接合焊垫,并且其中在连接点处的第二表面精整层的最小横向宽度至少与所述管芯接合焊垫的最大直径一样大,所述第二表面精整层的厚度被设置成减少在所述管芯接合焊垫上的表面精整层金属的横向膨胀。
2.如权利要求1所述的方法,其特征在于,通过直接浸金DIG工艺完成所述第一表面精整层的沉积。
3.如权利要求1所述的方法,其特征在于,通过化学镀钯浸金EPIG工艺完成所述第一表面精整层的沉积。
4.如权利要求1所述的方法,其特征在于,通过有机可焊性保护OSP工艺完成所述第一表面精整层的沉积。
5.如权利要求1-4中任一项所述的方法,其特征在于,使用化学镀工艺来完成沉积所述第二表面精整层,并且所述设置在第二侧上的一个或多个电触点包括一个或多个焊盘。
6.如权利要求1-4中任一项所述的方法,其特征在于,所述沉积第二表面精整层包括沉积镍Ni,并且所述设置在第二侧上的一个或多个电触点包括一个或多个焊盘。
7.如权利要求6所述的方法,其特征在于,所述沉积第二表面精整层进一步包括沉积钯或金中的一个或两者。
8.如权利要求7所述的方法,其特征在于,所述沉积第二表面精整层包括使用化学镀镍浸金ENIG+EG工艺沉积金。
9.一种封装衬底,包括:
第一侧,所述第一侧包括一个或多个焊盘,所述一个或多个焊盘具有设置在一个或多个焊盘上的第一表面精整层;以及
第二侧,所述第二侧与第一侧相对设置,所述第二侧具有管芯互连区域,所述管芯互连区域具有嵌入在其中的一个或多个电布线特征,所述一个或多个电布线特征具有设置在一个或多个电布线特征上并且与其直接接触的第二表面精整层,其中所述电布线特征被配置成与一个或多个管芯的管芯互连结构接合,并且所述第二表面精整层具有与第一表面精整层不同的化学组分,其中所述一个或多个电布线特征包括设置在所述第二侧上的管芯接合焊垫,并且其中在连接点处的第二表面精整层的最小横向宽度至少与所述管芯接合焊垫的最大直径一样大,所述第二表面精整层的厚度被设置成减少在所述管芯接合焊垫上的表面精整层金属的横向膨胀。
10.如权利要求9所述的封装衬底,其特征在于,所述第一表面精整层是在一个或多个焊盘上的最外层表面精整层,并且所述第二表面精整层是在一个或多个电布线特征上的最外层表面精整层。
11.如权利要求9所述的封装衬底,其特征在于,所述第二表面精整层是咪唑或咪唑衍生物。
12.如权利要求9所述的封装衬底,其特征在于,所述第二表面精整层为金。
13.如权利要求9所述的封装衬底,其特征在于,所述第二表面精整层是钯和金的组合。
14.如权利要求9所述的封装衬底,其特征在于,所述第二表面精整层具有小于或等于500纳米的厚度。
15.如权利要求9所述的封装衬底,其特征在于,所述第一表面精整层包括镍Ni。
16.如权利要求15所述的封装衬底,其特征在于,所述第一表面精整层进一步包括钯Pd或金Au中的一个或两者。
17.如权利要求9所述的封装衬底,其特征在于,所述管芯互连区域被设置在电介质层中。
18.如权利要求9所述的封装衬底,其特征在于,所述管芯互连区域包括硅桥。
19.如权利要求9所述的封装衬底,其特征在于,所述管芯互连区域的一个或多个电布线特征路由在连接至所述封装衬底的第一管芯和连接至所述封装衬底的第二管芯之间的电信号。
20.一种封装组件,包括:
集成电路IC芯片,所述集成电路芯片具有一个或多个输入输出I/O连接点和一个或多个电源连接点;以及
封装衬底,所述封装衬底包括:
包括一个或多个焊盘的第一侧,所述一个或多个焊盘具有设置在一个或多个焊盘上的第一表面精整层;以及
与所述第一侧相对设置的第二侧,所述第二侧具有嵌入在其中的硅连接区域,所述硅连接区域具有嵌入在其中的一个或多个电布线特征,所述一个或多个电布线特征具有设置在一个或多个电路由特征上并且与其直接接触的第二表面精整层,其中所述第二表面精整层具有与第一表面精整层不同的化学组分,并且所述第二表面精整层电连接至所述一个或多个I/O连接点或所述一个或多个电源连接点,其中所述一个或多个电布线特征包括设置在所述第二侧上的管芯接合焊垫,并且其中在连接点处的第二表面精整层的最小横向宽度至少与所述管芯接合焊垫的最大直径一样大,所述第二表面精整层的厚度被设置成减少在所述管芯接合焊垫上的表面精整层金属的横向膨胀。
21.如权利要求20所述的封装组件,其特征在于,所述IC芯片为处理器。
22.如权利要求20所述的封装组件,其特征在于,进一步包括与电路板耦合的天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统GPS装置、指南针、盖革计数器、加速度计、陀螺仪、扬声器,或相机中的一个或多个,其中所述封装组件是膝上型计算机、上网本、笔记本电脑、超级本电脑、智能电话、平板电脑、个人数字助理PDA、超移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字相机、便携式音乐播放器、或者数字录像机中的一个或多个。
23.一种用于形成集成电路IC封装衬底的设备,包括:
用于在封装衬底的第一侧上的一个或多个焊盘上沉积第一表面精整层的装置,其中所述衬底的所述第一侧与第二侧相对设置;以及
用于在所述封装衬底的第二侧上的管芯互连区域中嵌入的一个或多个电布线特征上沉积第二表面精整层的装置,所述第二表面精整层与所述一个或多个电布线特征直接接触,其中所述电布线特征与一个或多个管芯的管芯互连结构接合,其中所述一个或多个电布线特征包括设置在所述第二侧上的管芯接合焊垫,并且其中在连接点处的第二表面精整层的最小横向宽度至少与所述管芯接合焊垫的最大直径一样大,所述第二表面精整层的厚度被设置成减少在所述管芯接合焊垫上的表面精整层金属的横向膨胀。
24.如权利要求23所述的设备,其特征在于,所述设置在第二侧上的一个或多个电触点包括管芯接合焊垫,以及用于沉积第一表面精整层的装置进一步包括以下装置中的一个:
用于执行直接浸金DIG工艺的装置,
用于执行化学镀钯浸金EPIG工艺的装置,或
用于执行有机可焊性保护OSP工艺的装置。
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