CN102598258A - 用于微电子封装衬底的多个表面处理 - Google Patents

用于微电子封装衬底的多个表面处理 Download PDF

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CN102598258A
CN102598258A CN2010800493827A CN201080049382A CN102598258A CN 102598258 A CN102598258 A CN 102598258A CN 2010800493827 A CN2010800493827 A CN 2010800493827A CN 201080049382 A CN201080049382 A CN 201080049382A CN 102598258 A CN102598258 A CN 102598258A
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substrate
area
join domain
processing layer
layer
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CN102598258B (zh
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吴涛
C·古鲁墨菲
R·A·奥尔梅多
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Intel Corp
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Intel Corp
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Abstract

通过以下操作来将多个表面处理剂施加于微电子封装的衬底：将第一表面处理剂施加于衬底的第一区域的连接焊盘，掩蔽衬底的第一区域而不掩蔽衬底的第二区域，将第二不同的表面处理剂施加于衬底的第二区域的连接焊盘，以及移除掩蔽层。

Description

用于微电子封装衬底的多个表面处理
技术领域
本说明书涉及将表面处理剂施加于微电子封装的衬底的连接区域的领域，并且具体涉及将多个不同表面处理剂施加于单个衬底的多个不同连接区域。
背景技术
半导体和微机械器件通常附加到衬底。然后在衬底上附加覆盖以密封和保护内部的器件。覆盖能够包括热片或热管或只是附加到衬底的外部边缘的简易塑料覆盖。衬底构成到印制接线板、插座或某一其它装配台的电和机械连接。附加了覆盖的衬底被叫作封装。随着封装和内部器件的复杂度增加，对于衬底以及其到内部器件和到其外部连接的连接提出了新的需求。
在一些情况中，衬底可能具有不同类型的电连接。对于大小、密度、电容量、阻抗以及其它特性，电连接将具有不同的电要求。当使用丝印、光刻工艺以及其它类似的工艺来创建衬底上的连接时，使用单套制造工艺来创建不同类型的连接可能是困难的。
附图说明
以示例方式而非限制方式在附图的图中示出本发明的实施例，其中，类似参考数字用于表示类似特征，并且其中：
图1是根据本发明的实施例的堆叠封装器件的侧截面图；
图2是根据本发明的实施例的具有两个不同类型的焊盘开口的封装衬底的俯视图；
图3是根据本发明的实施例的具有两个不同类型的焊盘开口和围绕外围的连接条的备选封装衬底的俯视图；
图4A是根据本发明的实施例准备用于封装衬底的两个不同表面处理层的工艺的截面图；
图4B示出根据本发明的实施例将POP焊盘区域表面处理剂添加到图4A的封装衬底；
图4C示出根据本发明的实施例将保护掩蔽层添加到封装衬底；
图4D示出根据本发明的实施例将表面处理剂施加到封装衬底的C4连接区域；
图4E示出根据本发明的实施例从封装衬底移除保护掩蔽层；
图4F示出根据本发明的实施例将C4焊料凸起添加到封装衬底；
图5A是根据本发明实施例的准备用于封装衬底的三个不同表面处理层的备选工艺的截面图；
图5B示出根据本发明的实施例将表面处理剂添加到图5A的无芯衬底的C4连接区域；
图5C示出根据本发明的实施例从无芯衬底移除抗蚀图；
图5D示出根据本发明的实施例将用于POP焊盘区域的抗蚀图形成添加到无芯衬底；
图5E示出根据本发明的实施例将表面处理剂添加到无芯衬底的C4连接区域；
图5F示出根据本发明的实施例将多层连接和电介质以及抗蚀图添加到无芯衬底；
图5G示出根据本发明的实施例将表面处理剂添加到无芯衬底的BGA连接区域；
图5H示出根据本发明的实施例在BGA连接区域上施加保护膜并且从无芯衬底的底部蚀刻铜层；
图5I示出根据本发明的实施例从无芯衬底移除保护膜；
图5J示出根据本发明的实施例将C4连接焊料凸起施加于无芯衬底；以及
图6是根据本发明的实施例在衬底上产生多个表面处理层的工艺流程图。
具体实施方式
在一些POP(堆叠封装)衬底中，在相同的衬底上存在C4(受控崩塌芯片连接)和POP互连区域。单个表面处理层没有最优化互连的性能。为了改进性能，无电表面处理剂(即NiPdAu)能够在POP焊盘被掩蔽的情况下施加于C4焊盘。双C4表面处理层能够用于为C4和POP焊盘互连提供良好的焊点可靠性(SJR)。新的衬底制造工艺能够用于创建两个不同类型的表面处理层，一个在HDI(高密度互连)POP(堆叠封装)衬底的C4侧，并且另一个在POP焊盘侧。
已经证明，对于跌落性能，电解表面处理剂即NiAu是良好的表面处理剂。能够通过施加电解表面处理剂和对所有POP焊盘布线以连接到电解镀覆条来进行高性能POP焊盘表面处理。但是，由于焊盘和线路的高密度，电解表面处理剂不能施加于C4区域。已经证明，对于在电和热老化下的焊点可靠性，无电表面处理剂(即NiPdAu)是优秀的表面处理剂。
图1是能够应用本发明实施例的封装的简化截面图。图1中，封装10是堆叠封装(POP)类型的封装。在倒装芯片配置中，在封装底部的衬底8承载第一裸芯片6。在一个示例中，第一裸芯片是CPU(中央处理单元)、ASIC(专用集成电路)、微控制器或其它逻辑器件。它的电连接主要是在底部上且面向裸芯片，并且被紧密地放置在一起，使得能够将所有希望的引脚安装到裸芯片的底面上。
倒装芯片裸芯片6具有C4连接区域7，其具有密集填塞的焊料凸起栅格，焊料凸起与衬底8上的对应C4连接区域32连接。用适当的覆盖或涂层9封闭裸芯片的顶部。
在封装中在该裸芯片之上还包含第二裸芯片或裸芯片集合16，并且第二衬底12将第二裸芯片或裸芯片集合16与该裸芯片分隔。在示出的示例中，上裸芯片是堆叠式存储器裸芯片，使得三个组成部分16-1、16-2、16-3堆叠在一起以形成裸芯片。但是，可使用任何其它类型的裸芯片或裸芯片组。在单个封装中组合逻辑器件和存储器对于低功率、小型器件具有显著益处。但是，任何其它两个或更多裸芯片能够封装在一起，并且能够颠倒或调整这两个裸芯片的相对位置以适合任何特殊应用。
上衬底12在一侧即顶侧12-1直接连接到第二裸芯片16。这个连接通常提供电和机械支持并且下面对其进行更详细描述。在上衬底的相对侧即底侧12-2，衬底连接到球栅阵列(BGA)34。这个连接由以栅格或栅格部分的形式的焊料球阵列构成。焊料球18构成封装的上衬底12和封装的下衬底8之间的电连接。能够以各种各样方式中的任何方式来进行附加(attachment)。在示出的示例中，连接使用球栅阵列(BGA)，其中，示出该阵列的若干焊料球18。焊料球被放置在封装的下衬底的连接焊盘21上。
覆盖23附加到衬底的外围并且覆盖这两个裸芯片和所有内部连接。该覆盖提供保护免受外部元件干扰并且到衬底的附加能够是气密密封。该覆盖能够包括热片、散热器、热管或各种各样其它冷却器件中的任何，(未示出)。与上覆盖类似的第二覆盖9保护倒装芯片裸芯片6。
上衬底的顶侧承载连接22以构成与上裸芯片的底面的直接接触。该特殊类型的连接能够适于适合任何特殊应用。在示出的示例中，使用焊料凸起。图1在示出的截面图中仅示出五个连接。这是简化图。可能有数十或数百的连接。连接在一侧即顶侧接触裸芯片，并且然后通过通孔延伸至上衬底的底侧上的接触焊盘。这些接触焊盘能够通过衬底的底侧上的BGA连接。这允许构成与裸芯片16的外部连接。
除了衬底和存储器芯片16之间的连接22以外，衬底还承载接线焊盘24，线26附加到其上以连接到存储器裸芯片16的顶部上的对应焊盘(未示出)。接线焊盘通过通孔连接到衬底的底部上的BGA。在一些应用中，线连接用于电源，而倒装芯片裸芯片的顶部上的其它连接用于高速信令或数据。
衬底的顶侧上的另外的接线焊盘28用于将线30连接到存储器堆叠的顶层16-1。如果这个裸芯片是存储器裸芯片，则能够使用线连接而不是接触焊盘22容易地支持存储器器件中典型的较低的连接密度。这些另外的接线焊盘还能够通过通孔连接到BGA。另外，衬底能够提供接线层以将一些焊盘而不是另一些连接到球栅阵列中的不同点。因此，阵列中能够有若干球用于一个焊盘，并且衬底上有若干焊盘连接到一个焊料球。
如上面说明的，下衬底在其顶侧8-1连接到下裸芯片的C4接触区域以及到上衬底的BGA接触区域。在其底侧8-2，它连接到印制电路板(PCB)、印制接线板(PWB)、插座20或某一其它表面。底侧具有BGA 19以连接到PCB上的焊盘阵列。通过下衬底8的通孔将顶侧上的接触点连接到底侧上的接触点。虽然示出C4、线焊以及BGA连接，但是能够使用各种各样不同的连接。这些特殊的低密度和高密度互连能够适于适合任何特殊应用。
图1的示例示出HDI(高密度互连)类型的POP器件的示意图。类似于典型的LDI(低密度互连)POP，该器件的顶部件即上裸芯片16是存储器芯片封装。但是，底部封装与典型的LDI POP封装不同。在裸芯片和衬底之间不是使用线焊，而是HDI类型的衬底12与线焊一起被用于底部封装14。裸芯片和衬底之间的互连是通过倒装芯片以获得HDI区域，但是能够使用其它类型的芯片配置。因此，衬底具有用于倒装芯片连接的HDI区域以及LDI用于线焊连接。
图2示出图1的POP衬底8的俯视图8-1的图示。存在两个类型的焊盘开口。存在HDI区域32，在这个情况中是C4区域，以构成与下裸芯片的倒装芯片连接。这里，连接焊盘是非常密的并且存在小的开口用于裸芯片互连。
在衬底边缘、围绕C4区域的是用于BGA的LDI区域34，其连接到上衬底，上衬底又连接到至上裸芯片的线焊。这里，连接是低密度的并且焊盘具有大的开口。在本文中，这些将被叫作POP焊盘，其用于底部和顶部封装之间的互连。在依赖线焊的常规POP中，所有连接都是这个类型的低密度焊盘。中央HDI连接32连接到下裸芯片并且外围LDI连接34通过封装的上衬底连接到上裸芯片。
既然因为C4焊盘和POP焊盘以不同的方式构成不同类型的连接而使得它们的用途和功能是不同的，那么对焊盘表面处理剂实现焊点可靠性的要求是非常不同的。C4区域焊点一般受底部填充剂(underfill)保护，但是需要在电和热老化条件下的强可靠性。底部填充剂是在已经构成焊料连接之后施加在衬底和裸芯片之间的电介质，用于填充连接之间的空间以及保护它们免受物理、化学以及热影响。另一方面，POP焊盘焊点承受较少的信号或电老化要求，但是需要较高的跌落测试性能。在这些不同连接类型的需要和要求方面存在其它的不同。
为了向这两个类型的连接区域提供干净、可靠、耐用的连接，能够使用不同的表面处理剂。一个表面处理剂用于C4焊盘并且另一表面处理剂用于POP焊盘区域。将在C4和POP焊盘连接的上下文中呈现下面的示例，但是，其它类型的连接和连接组合能够受益于本发明的不同实施例。
已经证明，对于跌落性能，电解表面处理剂即NiAu是良好的表面处理剂。在一个示例中，能够施加电解表面处理剂(即NiAu)作为POP焊盘表面处理剂。另外，能够对所有POP焊盘布线以连接到电解镀覆条。但是，在C4区域中，由于焊盘和线路的高密度，电解表面处理剂工作得不好。已经证明，对于电和热老化下的良好焊点可靠性，无电表面处理剂(即NiPdAu)是优秀的表面处理剂。所以，无电表面处理剂(即NiPdAu)能够在POP焊盘被掩蔽的情况下施加于C4焊盘。
图3示出备选POP衬底的俯视图的图示。在图3的示例中，衬底40具有四个C4区域42-1到42-4。这些各自围绕有POP焊盘连接区域44-1到44-4。POP焊盘通过衬底上的接线线路或导线46耦合到靠近衬底的外部边缘的电解镀覆条48。与图2的示例中一样，POP焊盘区域围绕C4接触区域。电解镀覆条又围绕POP焊盘区域。在示出的示例中，C4连接区域形成正方形。POP焊盘形成围绕C4焊盘正方形的正方形。镀覆条形成围绕POP焊盘区域的正方形并且金属线线路将POP焊盘连接到这些条。这些条然后能够通过通孔连接到衬底的底部上的BGA或其它连接器(未示出)。在示出的示例中，仅对POP焊盘布线以连接到电解镀覆条。但是，取决于特殊应用，各种各样不同的接线和布线变化是可能的。
图4A到4F示出准备具有双表面处理层或两个不同表面处理层的HDI POP衬底的工艺。在正常HDI积层工艺和SR(阻焊)工艺之后，POP焊盘的表面处理剂(即NiAu)将被电解镀覆。然后，POP焊盘将被掩蔽并且C4区域焊盘的表面处理剂(即NiPdAu)将被无电镀覆。在POP焊盘掩蔽层移除之后，将恢复正常HDI工艺。
新工艺的一个明显优点是，满足以下挑战：在C4区域、POP焊盘以及BGA焊盘施加不同的表面处理剂以满足不同的焊点可靠性要求。因为在衬底的C4侧的双表面处理层，所以不需要牺牲性金属阻挡层。
转向图4A，多层衬底51具有电介质区域53和导电路径55，导电通道55通过电介质区域以构成顶面和底面之间的连接。适于图1的示例，图4A的衬底会在底面上具有BGA焊盘并且在接下来的图中发展以支持顶面上的C4和POP焊盘连接。
在图4A的示例中，C4连接在左并且POP焊盘在右。阻焊工艺已经完成以在顶层的阻焊剂56之间显露和限定用于C4连接的两个导电通孔57。还在顶层的阻焊剂之间，存在用于POP焊盘的两个导电通孔59。这两个POP焊盘通过衬底中的金属线61连接到带边缘(strip edge)。这与图3中的POP焊盘和电解镀覆条48之间的金属线46对应。
在图4A中，左侧的C4连接区域被掩蔽。当POP焊盘区域接收表面处理剂时，掩蔽层58保护C4连接区域。可使用光致抗蚀剂或各种各样其它保护膜中的任何保护膜来构成掩蔽层。在一个示例中，掩蔽层由选择性膏印制膜构成。类似地，能够使用光刻工艺、印制或其它技术来图案化掩蔽层。作为另外的备选，能够颠倒准备表面的顺序，使得POP焊盘区域首先完成，然后被掩蔽，并且然后C4连接区域完成。
在图4B中，电解表面处理剂已经施加于右手侧的用于POP焊盘的通孔。在这个示例中，表面处理层是NiAu层。首先，通过掩蔽其它区域以及施加湿镍离子浴来施加镍层63。接着，通过施加湿金浴来形成金层65。虽然示出电解NiAu，但是存在能够施加的各种各样的其它可能的表面处理剂以最优化POP焊盘的质量和功能。备选地，能够使用各种各样的其它表面处理剂，例如电解NiPdAu、电解PdAu、电解NiPd等。
在图4C中，移除左侧的C4连接区域上的掩蔽层并且掩蔽右侧的POP焊盘区域。当C4区域接收表面处理剂时，右侧的掩蔽层67保护POP焊盘区域。可用与图4A和4B中的掩蔽层相同的方式来构成掩蔽层。在这两个情况中，能够通过光刻工艺技术或选择性印制或用各种各样其它方式中的任何方式来建立掩蔽层图案。
在图4D中，在通孔55上形成镍钯层，其中，要构成C4接触点。然后，在镍钯层上形成金层。用无电工艺来施加镍钯并且用浸没工艺来施加金。虽然示出NiPdAu工艺，但是取决于应用，能够使用适合于C4连接的各种各样的其它处理。
在图4E中，从POP焊盘区域移除掩蔽层67，并且在图4E中，C4焊料凸起73被施加在C4连接点上。所得的衬底现在示出具有两个不同类型的表面处理层的两个不同类型的连接区域。在示出的示例中，在施加焊料凸起之前移除保护掩蔽层。这保护掩蔽层免受焊料凸起工艺的热。用不同的掩蔽层材料，可在以后移除掩蔽层。
上面提到的操作中的每个通常涉及上面未描述的很多另外的操作，例如掩蔽、清洗、印制、镀覆蒸发、干燥、加热等。未详细描述这些操作以便简化说明书。取决于用于任何特殊应用的特殊表面处理剂，能够用各种各样不同的方式来修改操作。
图4A到4F的操作能够应用于很多不同类型的具有两个不同接触区域的衬底。这种衬底的另一示例是无芯衬底(coreless substrate)。具有DLL3(直接层和层压)-D类型的无芯衬底的HDI POP的C4侧也呈现两个不同的连接区域。同时，工艺能够有助于在与这两个连接区域相对的BGA侧的希望的表面处理。虽然各种各样不同的表面处理剂能够用于BGA侧，但是一个可能性是直接浸没Au(DIG)表面处理剂。
图5A到5J示出实现HDI POP衬底双表面处理层的备选工艺。利用DLL3-D类型的封装工艺的优点，能够通过仅图案化C4区域来首先电解镀覆C4区域表面处理剂(例如NiPdAu)。在C4区域镀覆完成并且干膜抗蚀剂被移除之后，POP焊盘区域能够被图案化用于不同类型的电解表面处理剂镀覆(例如NiAu)。在正常HDI积层工艺和阻焊工艺之后，能够施加不同的希望的BGA焊盘表面处理剂，例如DIG(直接浸没金)或OSP(有机可焊性保护剂)。
参考图5A，示出具有图案化干膜抗蚀剂(DFR)层81的初始铜膜或片80。如以下附图中能够看出的，初始片形成用于构造无芯衬底的基础并且最终被移除。DFR层限定C4接触焊料凸起的位置。在图5A中，DFR层中的开口填充有电解AuPdAu层83。这能够用各种各样的电解工艺来进行并且层的特殊组成能够适于适合不同的应用。在图5C中，DFR层被移除，将C4连接点留在无芯衬底上。
在图5D中，新的DFR层85被图案化到衬底上。新的层覆盖和保护C4连接区域并且限定POP焊盘区域的位置。在图5E中，图案化DRF层85中的间隙在其内沉积有电解AuNi层87。这能够用各种各样不同的方式来执行，如上面在图4B的上下文中论述的。用于这个表面处理的工艺和材料的特殊选择能够按照希望适于适合任何特殊实施例。
在图5F中，若干新的操作已经应用于无芯衬底。首先，DFR层85已经被移除。接着，已经在C4和POP焊盘连接区域上堆积互连91和导电通孔89和电介质的层。依次通过图案化、沉积、蚀刻以及重复(repeating)来堆积这些层。各种各样不同的工艺能够用于实现这些层。在已经形成通孔和互连之后，在所得的表面上图案化阻焊剂93。将阻焊剂图案化以限定球栅阵列的最终球连接的位置。最终在图5F中，图案化阻焊剂中的用于球的每个开口已经涂有铜层。铜还没有表面处理层。
在图5G中，适当的表面处理剂95已经施加于BGA井。表面处理剂可以是希望的且适合用于BGA连接焊盘的任何处理剂。如果连接焊盘是另一类型，则能够使用不同的表面处理剂。在一个实施例中能够使用DIG或OSP表面处理剂。
在图5H中，保护膜99层压在BGA井上。该膜可由PET(聚酯)或各种各样的其它材料构成，并且在这个示例中被层压在井上。当从无芯衬底的底侧蚀刻底层铜80时，层压保护BGA接触区域。移除底层铜暴露C483和POP焊盘87区域的接触区域。由于图5F中添加的电介质阻挡91，底部接触焊盘在倒置井的内部。
在图5I中，保护膜99被移除。这个图示出在无芯衬底的顶部上的暴露的BGA接触点和在无芯衬底的底部上的这两个不同类型的接触点，即C4和POP焊盘。顶部接触点准备好通过每个井中的金表面处理层与焊料球接触。POP焊盘具有电解金镍表面处理层以接收线用于线焊。C4焊盘准备好用于C4焊料凸起或微球，其将被施加于电解金、钯、金表面处理层。在图5J中，C4焊料凸起已经被施加在无芯裸芯片的底面上的适当位置。
图5A到5J的工艺允许不同的表面处理剂被施加在C4区域、POP焊盘以及BGA焊盘以满足不同的焊点可靠性要求。另外，能够在POP焊盘表面施加电解NiAu表面处理剂，而不用对所有POP焊盘布线以连接到电解镀覆条。这避免可能由暴露会要求连接到共同条的很多铜线路(见例如图3的46、48)而造成的设计挑战和可靠性担忧。
图6是根据本发明的实施例在衬底上产生多个表面处理层的工艺流程图。在图6中，在框103，第一表面处理剂施加于衬底的第一区域。衬底的第一区域能够是低或高密度连接界面。在LDI区域的情况中，连接可以是POP焊盘区域、线焊区域或BGA区域。基于连接区域的属性来选择第一表面处理剂。对于LDI区域，能够使用电解表面处理剂等，例如电解NiAu。备选地，能够使用DIG、OSP以及类似处理剂。
在框105，掩蔽衬底的第一区域。这么做使得衬底的具有第二不同连接区域的第二区域暴露。第二连接区域能够具有与第一类似的密度，但是具有不同的连接要求，或它能够是不同的密度。例如，它能够是高密度区域，例如C4连接区域。
在框107，第二不同表面处理剂施加于衬底的第二区域，而第一区域是被掩蔽的。在C4连接区域的情况中，能够使用无电表面处理剂NiPdAu。但是，其它类型的处理剂也能够用于C4和其它类型的连接区域。
在框109，移除掩蔽层，并且在框111，连接区域完成。这能够通过添加焊料球或凸起、线连接另外的焊盘或适合于所使用的特殊连接区域的某一其它结构来进行。
这两个连接区域能够在彼此的旁边或分隔。它们能够在衬底的相同侧或在衬底的相对侧。能够在高密度区域之前完成低密度区域，或反之亦然。在上面示出的一个示例中，第一连接区域是在衬底的顶面上并且第二连接区域是在衬底的与顶面相对的底面上。
能够通过掩蔽一些连接区域而将表面处理剂施加于另一些连接区域来完成另外的区域。总
各种操作被描述为多个分立操作以帮助理解本说明书。但是，说明的顺序不应该解释成暗示这些操作一定是顺序相关的。具体地，不需要以呈现的顺序来执行这些操作。可用与所描述实施例不同的顺序来执行所描述的操作。可执行各种另外的操作并且可省略所描述的操作。
鉴于上述教导，很多修改和变化是可能的。可对于图中示出的各种组成部分和操作进行各种等效组合和替换。本发明的范围应不受这个详细说明的限制，而是受于此所附的权利要求书限制。
提供上面描述的示例分层、涂层、蚀刻和图案化工艺仅作为示例。可存在其它和不同的工艺，其将不同的表面处理剂施加于不同类型的衬底上的不同类型的连接区域。提供特殊类型的连接区域、封装以及表面处理剂仅作为示例并且可进行不同的选择以适合不同的应用。
可使用与本文示出和描述的那些相比不太复杂或更复杂的表面处理、封装以及制造工艺。因此，取决于许多因素，例如价格约束、性能要求、技术改进或其它情形，配置可从实现到实现而变化。本发明的实施例还可应用于受益于不同类型的表面处理剂的其它类型的封装和连接。另外，本发明的实施例可应用于半导体、微电子、微型机以及使用光刻工艺技术的其它器件的产生。
在上面的说明中，阐述了许多特定细节。但是，理解的是，没有这些特定细节，也可实施本发明的实施例。例如，可用众所周知的等效材料替换本文描述的那些材料，并且类似地，可用众所周知的等效技术来替换所公开的特殊处理技术。另外，步骤和操作可被移除或被添加到所描述的操作，以改进结果或添加另外的功能。在其它情况中，未详细示出众所周知的电路、结构和技术以免影响对本说明书的理解。
虽然已经根据若干示例描述了本发明的实施例，但是，本领域技术人员可认识到，本发明不限于所描述的实施例，而是可用所附权利要求书的精神和范围内的修改和变更来实施。本说明书因此应被视为是说明性的而不是限制性的。

Claims (20)

1.一种方法，包括：
将第一表面处理剂施加于衬底的第一区域的连接焊盘；
掩蔽所述衬底的第一区域，而不掩蔽所述衬底的第二区域；
将第二不同的表面处理剂施加于所述衬底的第二区域的连接焊盘；以及
移除掩蔽层。
2.如权利要求1所述的方法，其中，所述衬底的第一区域是低密度连接界面，并且其中，施加第一表面处理剂包括施加电解表面处理剂。
3.如权利要求2所述的方法，其中，所述电解表面处理剂是NiAu表面处理剂。
4.如权利要求2所述的方法，其中，所述低密度连接界面是POP焊盘区域。
5.如权利要求1所述的方法，其中，所述衬底的第二区域包括高密度连接界面，并且其中，施加表面处理剂包括施加无电表面处理剂。
6.如权利要求5所述的方法，其中，所述无电表面处理剂是NiPdAu表面处理剂。
7.如权利要求5所述的方法，其中，所述高密度连接界面包括C4区域。
8.如权利要求1所述的方法，其中，所述第一区域是在所述衬底的第一表面上，并且所述第二区域是在所述衬底的与所述第一表面相对且平行的第二表面上。
9.如权利要求1所述的方法，其中，所述第一区域是在所述衬底的顶面上，并且所述第二区域是在所述衬底的与所述顶面相对的底面上。
10.如权利要求1所述的方法，还包括：
掩蔽所述衬底的第一和第二区域；
将第三不同的处理剂施加于所述衬底的第三区域；以及
移除掩蔽层。
11.如权利要求10所述的方法，其中，所述衬底的第一和第二区域是在所述衬底的顶面上，并且所述衬底的第三区域是在所述衬底的与所述顶面相对的底面上。
12.如权利要求11所述的方法，其中，第三处理层是直接浸没表面。
13.如权利要求11所述的方法，其中，所述衬底的第三区域包括第三不同类型的接触区域。
14.如权利要求1所述的方法，还包括：在施加所述第一表面处理剂之前，掩蔽所述衬底的第二区域，而不掩蔽所述衬底的第一区域。
15.一种用于堆叠封装式封装的半导体衬底，在一侧具有第一低密度连接区域并且在所述一侧具有第二高密度连接区域，
所述第一连接区域具有当所述第二连接区域是被掩蔽的时施加于所述第一区域的连接焊盘的第一表面处理层，
所述第二连接区域具有当所述第一连接区域是被掩蔽的时施加于所述第二区域的连接焊盘的第二表面处理层。
16.如权利要求15所述的衬底，其中，所述第一表面处理层是电解表面处理层，并且所述第二表面处理层是无电表面处理层。
17.如权利要求16所述的衬底，其中，所述电解表面处理层是NiAu表面处理层，并且所述无电表面处理层是NiPdAu表面处理层。
18.如权利要求15所述的衬底，还包括在所述衬底的第二侧的第三连接区域，所述第三连接区域具有当所述第一和第二连接区域是被掩蔽的时施加的第三不同的处理层。
19.如权利要求18所述的衬底，其中，所述第三处理层是直接浸没表面。
20.如权利要求15所述的衬底，其中，所述衬底的第一和第二区域是在顶面上，用于连接到装配到所述衬底的顶面的裸芯片，并且所述衬底的第三区域是在所述衬底的底面上，用于连接到印制电路板。
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