JP2009295958A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2009295958A
JP2009295958A JP2009008178A JP2009008178A JP2009295958A JP 2009295958 A JP2009295958 A JP 2009295958A JP 2009008178 A JP2009008178 A JP 2009008178A JP 2009008178 A JP2009008178 A JP 2009008178A JP 2009295958 A JP2009295958 A JP 2009295958A
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Japan
Prior art keywords
plating layer
substrate
external connection
connection terminal
semiconductor device
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JP2009008178A
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English (en)
Inventor
Hiroharu Omori
弘治 大森
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Panasonic Corp
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Panasonic Corp
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Priority to JP2009008178A priority Critical patent/JP2009295958A/ja
Priority to US12/372,130 priority patent/US8097962B2/en
Publication of JP2009295958A publication Critical patent/JP2009295958A/ja
Priority to US13/308,038 priority patent/US8907468B2/en
Pending legal-status Critical Current

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  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Chemically Coating (AREA)

Abstract

【課題】半導体装置において、接続バンプと外部接続端子との間の接合性が良好な構造を提供する。
【解決手段】外部接続端子２を有する基板３と、基板３の半導体素子の実装部１に実装された半導体素子とを備えている。外部接続端子２は、基板３の表面上に設けられた端子部２ａの上に、無電解ニッケルめっき層１９と無電解金めっき層２０と電解金めっき層２１とが順次積層されて形成されている。これによって、外部接続端子２の表面である電解金めっき相２１の表面が緻密であるので、外部接続端子２内には湿気が侵入しにくくなり、接合性を向上できる。
【選択図】図３

Description

本発明は、半導体装置に関するものである。
半導体装置は、一般的に、外部接続端子を有する基板と、基板に設けられた半導体素子と、外部接続端子に接続された接続バンプとを備えている。
また、上記外部接続端子は、基板の表面上に設けられた端子部の上に、第一の無電解めっき層、第二の無電解めっき層および第三の無電解めっき層を順次積層して形成されている（なお、これに類似する先行文献としては、たとえば下記特許文献１がある）。
特開２００５−２５６１２８号公報
上述のごとく基板の表面上に設けられた端子部の上に第一の無電解めっき層、第二の無電解めっき層および第三の無電解めっき層を順次積層することにより外部接続端子を形成する理由は、よく知られているように、以下に示す通りである。つまり、外部接続端子を形成した後に接続バンプを介してこの外部接続端子と他の基板とを接続させる時に、その接続に対する信頼性を向上させるためである。具体的には、最下層の端子部が銅層で形成されている場合に、この端子部と接続バンプ（はんだにより形成される）とを強固に接続するため、および、接続バンプによるはんだ喰われを防止するため等である。
しかし、これらの問題点を改善するために上述のごとく基板の表面上に設けた端子部の上に第一の無電解めっき層、第二の無電解めっき層、第三の無電解めっき層を順次積層して外部接続端子を形成した場合には、湿度によって接続バンプと外部接続端子との間の接合性が低下する場合がある。すなわち、無電解めっき層を拡大してみた場合、その表面は非緻密状態となっているので、表面（第三の無電解めっき層）から湿気が浸入しやすい。そして、このように湿気が第三の無電解めっき層から浸入すると、この湿気に起因して第三の無電解めっき層よりも下層（第一または第二の無電解めっき層）を構成する金属原子が第三の無電解めっき層の表面に表出することで、外部接続端子の表面の状態が変性してしまい、その結果として上記接続バンプと外部接続端子との間の接合性が低下するのであった。
そこで、本発明は、接続バンプと外部接続端子との間の接合性を向上させることを目的とするものである。
上記目的を達成するために、本発明は、外部接続端子を有する基板と、基板に設けられた半導体素子とを備えた半導体装置において、外部接続端子は、基板の表面上に設けられた端子部と、端子部の上に設けられた無電解めっき層と、無電解めっき層の上に設けられた電解めっき層とを有している。これにより、外部接続端子の表層が電解めっき層からなるので、表面（電解めっき層）から湿気が浸入することを防止することができる。
本発明では、外部接続端子は端子部の上に無電解めっき層及び電解めっき層が順次形成されたものであるので、接続バンプと外部接続端子との間の接合性を向上させることが出来る。
すなわち、基板の表面上に設けられた端子部の上に無電解めっき層および電解めっき層を順次積層して外部接続端子を形成した場合には、外部接続端子の表面である電解めっき層の表面が緻密である。よって、湿気が電解めっき層の表面から浸入しにくくなり、その結果としてこの外部接続端子の表面の変性を防止でき、これにより接続バンプと外部接続端子との間の接合性を向上させることが出来るのである。
以下、本発明の実施形態を図面に基づいて詳細に説明する。なお、本発明は以下に示す実施形態に限定されない。
図１は本実施形態にかかる半導体装置の断面図であり、図２は基板の上面図であり、図３は図２に示すIII−III線断面図における断面図であり、図４は図３に示す領域IVの拡大図であり、図５は基板の下面図である。
図１および図２に示すごとく本実施形態の半導体装置は、半導体素子の実装部１と外部接続端子２とを上面に有する基板３と、この基板３の半導体素子の実装部１に実装された半導体素子４とを備えている。
半導体素子４は、接続バンプ６を介して、基板３の上面に設けられた接続端子５に電気的に接続されており、この状態（半導体素子４が接続バンプ６を介して接続端子５に電気的に接続された状態）は、接着剤７により固定されている。また、この基板３の下面にも、外部接続端子８と接続バンプ９とが設けられている。
以上の構成で基板３は形成されているが、図１に示すように、この基板３の上には基板３とは異なる基板（基板１０）が設けられている。以下では、その構造を説明する。
基板１０の上面には半導体素子１１および接続端子１３が設けられており、金属細線１２で半導体素子１１と接続端子１３とが電気的に接続されている。半導体素子１１、金属細線１２および接続端子１３は封止樹脂１４で封止されている。
このような基板１０を基板３に接続する方法としては、基板３の上面の外部接続端子２と基板１０の下面の外部接続端子１５との間に接続バンプ１６を介在させ、この接続バンプ１６を介して基板３の上面の外部接続端子２と基板１０下面の外部接続端子１５とを電気的にも構造的にも接続する。
さて、このような基板３の上に基板１０が設けられた半導体装置において、基板３と基板１０とを接続させる作業を行うまでの間に、基板３の上面に設けた外部接続端子２の表面状態が変性しないように、本実施形態では以下のような構成をとっている。
図２に示すごとく、基板３の上面（表面）の内方（中央部分）には、半導体素子の実装部１として複数の接続端子５を形成している。また、基板３の上面のうち半導体素子の実装部１よりも周縁には、複数の外部接続端子２を形成し、各外部接続端子２から基板３の外周部に向けて、銅膜よりなる電解めっき用配線パターン１７を延長している。
電解めっき用配線パターン１７の上面は、図３のごとくソルダーレジスト１８で覆われており、このソルダーレジスト１８のうち外部接続端子２を形成する部分が除去され、この除去された部分に外部接続端子２の端子部２ａが形成されている。具体的には、ソルダーレジスト１８の除去された部分において、銅膜よりなる電解めっき用配線パターン（銅層）１７の端子部２ａ上に順次、第一の無電解めっき層として無電解ニッケルめっき層１９を形成し、第二の無電解めっき層として無電解金めっき層２０を形成し、電解めっき層として電解金めっき層２１を形成している。
電解金めっき層２１を形成するための通電は、電解めっき槽中に基板３を浸漬した状態で、基板３の外周に引き出された電解めっき用配線パターン１７を介して行なう。
図２においては、各電解めっき用配線パターン１７は基板３の外周において分離された状態となっているが、この電解めっき時にはこの図２に示す基板３が平面状に複数個一体化され、その状態において各電解めっき用配線パターン１７は電気的に接続された状態となっている。
そしてこの通電により、電解金めっき層２１を形成した後に、基板３を分割し、この図２に示す状態としている。
図４はこのようにして形成された外部接続端子２の拡大図で、電解めっき用配線パターン１７上に、Ｐｄめっきシード２２が存在し、Ｐｄめっきシード２２を核として無電解ニッケルめっき層１９が形成され、無電解ニッケルめっき層１９の上方に無電解金めっき層２０および電解金めっき層２１が形成されている。
電解金めっき層２１は、電解めっきにより形成されたものであるので、その表面は緻密な状態となっている。よって、電解金めっき層２１の表面からの湿気などの浸入は起きず、当然のこととして電解金めっき層２１の表面の変性は生じない。
すなわち、上述したように基板３の上に基板１０が設けられた半導体装置において、基板３と基板１０とを接続するまでの間に基板３の上面に設けられた外部接続端子２の表面状態が変性しないように、本実施形態ではこの電解金めっき層２１を設けている。このように外部接続端子２の表層部分を電解金めっき層２１で構成することにより、接続バンプ１６を電解金めっき層２１に強固に固定することができるので、接続バンプ１６と外部接続端子２との間の接合性を向上させることができる。
また、このように電解金めっき層２１を形成するために、外部接続端子２から基板３の外周部に向けて、銅膜よりなる電解めっき用配線パターン１７を延長している。
すなわち、この電解めっき用配線パターン１７を完成後の基板３にも残った状態としておくと、例えば図１において基板３および基板１０の熱膨張係数が異なるものであった場合に接続バンプ１６を介して外部接続端子２を引き剥がそうとする力が働いた場合でも、残存する電解めっき用配線パターン１７が、例えば根っこのような働きをすることで、この外部接続端子２の剥離を抑制できるものとなる。
なお、外部接続端子８では図３のように端子部８ａの上に無電解ニッケルめっき層１９が形成されており、また、外部接続端子８の上には半田ボールからなる接続バンプ９が設けられている。ここで、外部接続端子２と同じように端子部８ａの上に無電解ニッケルめっき層１９，無電解金めっき層２０および電解金めっき層２１を順に積層させて外部接続端子８を形成した場合であっても、電解金めっき層２１の上に接続バンプ９を設けると、接続バンプ９が半田ボールであるので無電解金めっき層２０および電解金めっき層２１を構成する金めっきが接続バンプ９中に拡散する。そのため、外部接続端子８では、図３に示すように、端子部８ａの上に無電解ニッケルめっき層１９が形成された構造となる。
この外部接続端子８は、図５に示すように、基板３の下面の周縁に設けられている。基板３の下面では、基板３の上面（図２）と同じく、各外部接続端子８から基板３の外周部に向けて、銅膜よりなる電解めっき用配線パターン１７が延長されていてもよい。
接続端子５は、無電解めっき層および電解めっき層のどちらからなっても良いが、無電解めっき層からなることが好ましい。その理由としては、次の２つを挙げることができる。一つめの理由は、電解めっき用配線以外の配線の設計自由度を確保するためである。具体的には、接続端子５を電解めっき層から形成するためには、電解めっき用配線を設ける必要がある。しかし、接続端子５の間隔が外部接続端子２などの間隔に比べて狭いために（図２）、実装部１に電解めっき用配線を設けると、電解めっき用配線以外の配線の設計自由度がほとんどなくなる。二つめの理由は、接続端子５は、半導体装置の製造工程の比較的早い時点において接着剤７に封止されるので、接続端子５の表層を緻密な構造としなくても接続端子５内に湿気が浸入することを防ぐことができるからである。
また、外部接続端子２の端子部２ａと電解金めっき層２１との間に設けられた無電解めっき層の層数は２個に限定されない。
以上のごとく本発明は、外部接続端子を有する基板と、基板に設けられた半導体素子とを備え、外部接続端子では、基板の表面上に設けられた端子部の上に、無電解めっき層および電解めっき層が順次積層されているので、接続バンプと外部接続端子との間の接合性を向上させることが出来る。
すなわち、基板の表面上に設けられた端子部の上に、無電解めっき層および電解めっき層を順次積層して外部接続端子を形成した場合には、外部接続端子の表面である電解めっき層の表面が緻密であるので、外部接続端子内には湿気が浸入しにくく、その結果としてこの外部接続端子の表面が変性せず、これにより接続バンプと外部接続端子との間の接合性を向上させることが出来るのである。
したがって、各種電子機器に活用される半導体装置の構造として広く活用されるものとなる。
本発明の一実施形態にかかる半導体装置の断面図 本発明の一実施形態における基板３の上面図 図２に示すIII-III線における断面図 図３に示すIV領域の拡大断面図 本発明の一実施形態における基板３の下面図
１ 半導体素子の実装部
２，８，１５ 外部接続端子
２ａ，８ａ 端子部
３，１０ 基板
４，１１ 半導体素子
５，１３ 接続端子
６ 接続バンプ
７ 接着剤
９，１６ 接続バンプ
１２ 金属細線
１４ 封止樹脂体
１７ 電解めっき用配線パターン
１８ ソルダーレジスト
１９ 無電解ニッケルめっき層（第一の無電解めっき層）
２０ 無電解金めっき層 （第二の無電解めっき層）
２１ 電解金めっき層 （電解めっき層）
２２ Ｐｄめっきシード

Claims (5)

  1. 外部接続端子を有する基板と、
    前記基板に設けられた半導体素子とを備え、
    前記外部接続端子は、前記基板の表面上に設けられた端子部と、前記端子部の上に設けられた無電解めっき層と、前記無電解めっき層の上に設けられた電解めっき層とを有している半導体装置。
  2. 請求項１に記載の半導体装置において、
    前記半導体素子は、前記基板の前記表面の中央に設けられ、
    前記外部接続端子は、前記基板の前記表面のうち前記半導体素子が設けられた部分よりも周縁に設けられており、
    前記基板内では、電解めっき用配線パターンが、前記外部接続端子から前記基板の前記表面の外周部へ向かって延びている半導体装置。
  3. 請求項１または２に記載の半導体装置において、
    前記基板は、前記半導体素子に電気的に接続される接続端子を有し、
    前記外部接続端子の表層は、前記電解めっき層であり、
    前記接続端子は、無電解めっき層からなる半導体装置。
  4. 請求項１から３の何れか一つに記載の半導体装置において、
    前記外部接続端子の前記無電解めっき層は、前記端子部の上に設けられた第一の無電解めっき層と、前記第一の無電解めっき層の上に設けられた第二の無電解めっき層とを有し、
    前記端子部は銅層であり、前記第一の無電解めっき層は無電解ニッケルめっき層であり、前記第二の無電解めっき層は無電解金めっき層であり、前記電解めっき層は電解金めっき層である半導体装置。
  5. 請求項１から４の何れか一つに記載の半導体装置において、
    前記外部接続端子に接続された接続バンプをさらに備えている半導体装置。
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