CN108074881A - 封装堆叠结构 - Google Patents

封装堆叠结构 Download PDF

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Publication number
CN108074881A
CN108074881A CN201611011487.9A CN201611011487A CN108074881A CN 108074881 A CN108074881 A CN 108074881A CN 201611011487 A CN201611011487 A CN 201611011487A CN 108074881 A CN108074881 A CN 108074881A
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substrate
perforation
stacking structure
encapsulation stacking
width
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CN201611011487.9A
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CN108074881B (zh
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林长甫
姚进财
余国华
黄富堂
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种封装堆叠结构，包括：第一基板、堆叠于该第一基板上的第二基板、以及设于该第一与第二基板之间的封装层，其中，该第二基板具有贯穿的穿孔，以于形成该封装层时，供该封装层的材料流入，藉以增加该封装层与该第二基板的接触面积，而增加两者的结合力。

Description

封装堆叠结构
技术领域
本发明有关一种封装结构，尤指一种封装堆叠结构。
背景技术
随着半导体封装技术的演进，半导体装置(Semiconductor device)已开发出不同的封装型态，而为提升电性功能及节省封装空间，遂发展出堆叠多个封装结构以形成封装堆叠结构(Package on Package，简称POP)的技术，此种封装方式能发挥系统封装(SiP)异质整合特性，可将不同功用的电子元件，例如：记忆体、中央处理器、绘图处理器、影像应用处理器等，通过堆叠设计达到系统的整合，适合应用于各种轻薄型电子产品。
图1为现有封装堆叠结构1的剖面示意图。如图1所示，该封装堆叠结构1通过焊锡球13堆叠封装基板11及中介基板(interposer)12，其中，该封装基板11上侧设有半导体元件10，而下侧设有用以接置电子装置(如电路板，图略)的焊球17，并于该封装基板11与该中介基板12之间形成封装胶体14，以包覆该半导体元件10与焊锡球13。
然而，现有封装堆叠结构1中，该中介基板12的两侧具有防焊层123，于经过多道制程后，该防焊层123容易发生白化，使得该封装胶体14与该中介基板12之间容易脱层(delamination)。
另外，于形成该封装胶体14时，空气容易残留于该封装基板11与该中介基板12之间，因而容易于该封装胶体14内产生空洞(void)，导致良率降低。
因此，如何克服现有技术中的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失，本发明提供一种封装堆叠结构，以增加该封装层与该第二基板的接触面积，而增加两者的结合力。
本发明的封装堆叠结构包括：第一基板；第二基板，其具有相对的第一表面及第二表面，使该第二基板以其第一表面通过多个导电元件叠设于该第一基板上，其中，该第二基板具有至少一连通该第一表面与第二表面的穿孔；以及封装层，其形成于该第二基板与该第一基板之间及该穿孔中。
前述的封装堆叠结构中，该穿孔的宽度至多为50微米，例如，该穿孔的宽度为10至25微米。
前述的封装堆叠结构中，该第二基板的第一表面与第二表面上具有绝缘保护层，且该穿孔延伸贯穿该绝缘保护层，也就是该绝缘保护层形成有开口，且该开口连通至该穿孔，其中，该开口的宽度大于该穿孔的宽度。例如，该开口的宽度至多为100微米，且该穿孔及该开口的纵剖面呈T形、Ⅰ形或Ⅱ形。
前述的封装堆叠结构中，复包括设于该第一基板上并电性连接该第一基板的电子元件。该穿孔的位置对应该电子元件的位置，例如，该穿孔设于该第二基板的位置对应该电子元件投影至该第二基板的范围内，较佳地，该穿孔设于该第二基板的位置对应该电子元件投影至该第二基板的角落处。
前述的封装堆叠结构中，复包括设于该第二基板上并电性连接该第二基板的电子元件。
由上可知，本发明的封装堆叠结构，主要通过该第二基板形成有该穿孔，以于形成该封装层时，供该封装层的材料流入，藉以增加该封装层与该第二基板的接触面积，而增加两者的结合力，尤其是该穿孔延伸至该绝缘保护层的开口的宽度大于穿孔的宽度，使该封装层填充于该穿孔及该开口时，得以产生锁固(lock)的效果，避免发生脱层问题。
此外，该穿孔可作为模压排气孔，以于形成该封装层时，该封装层可经由该穿孔流至该第二基板的第二表面，因而能排挤出气体，故相比于现有技术，该封装堆叠结构能避免孔洞的发生。
附图说明
图1为现有封装堆叠结构的剖视示意图；
图2为本发明封装堆叠结构的剖视示意图；
图3A至图3D为对应图2的穿孔的不同实施例的局部放大剖视图；以及
图4A至图4C为对应图2的不同实施例的局部上视示意图。
符号说明：
1,2 封装堆叠结构
10 半导体元件
11 封装基板
12 中介基板
123 防焊层
13 焊锡球
14 封装胶体
17 焊球
20,25 电子元件
200,250 焊锡凸块
21 第一基板
210 焊垫
22 第二基板
22a 第一表面
22b 第二表面
220 穿孔
221 电性接触垫
222 外接垫
223 绝缘保护层
223a 开口
23 导电元件
24 封装层
26 底胶
D 宽度
R 扩大宽度。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2为本发明封装堆叠结构2的剖视示意图。如图2所示，该封装堆叠结构2包括一第一基板21、一第二基板22、多个导电元件23以及封装层24。
所述的第一基板21为封装基板，其上设有至少一电子元件20。
于本实施例中，该第一基板21的构造可为核心式(core)或无核心式(coreless)的结构，其具有至少一线路层，且该线路层包含有多个焊垫210。
此外，该电子元件20为主动元件、被动元件或其组合，该主动元件例如为晶片，而该被动元件例如为电阻、电容及电感。具体地，该电子元件20通过多个焊锡凸块200设于部分该焊垫210上，即该电子元件20以覆晶方式电性连接该第一基板21。应可理解地，该电子元件20也可以打线方式电性连接该焊垫210。
所述的第二基板22具有相对的第一表面22a及第二表面22b，且该第二基板22具有至少一连通该第一表面22a与第二表面22b的穿孔220。
于本实施例中，该第二基板22的构造可为核心式或无核心式的结构，其具有至少一线路层，且该线路层包含有多个位于该第一表面22a上的电性接触垫221及多个位于该第二表面22b上的外接垫222，并于该第一及第二表面22a,22b上形成有例如防焊层的绝缘保护层223，且令该些电性接触垫221及外接垫222外露于该绝缘保护层223。
此外，该穿孔220以激光、机械钻孔或其它方式(如喷砂、锉、切割、铣、研磨、水刀或蚀刻等)形成，且该穿孔220的宽度D为50μm以下，较佳为10至25μm。
又，该穿孔220的形状可依需求设计，例如，该穿孔220可延伸贯穿该绝缘保护层223，而于该绝缘保护层223中形成有对应的开口223a，也就是该绝缘保护层223的开口223a连通至该穿孔220。具体地，如图2所示，该穿孔220延伸至该些绝缘保护层223，且其宽度D保持一致(即该穿孔220与该开口223a的宽度均相同)；或者，如图3A及图3B所示，该穿孔220延伸至其中一绝缘保护层223的部分扩大其宽度，以令该穿孔220及该开口223a的纵剖面呈“T”形，也就是该绝缘保护层223的开口223a的宽度R大于穿孔220的宽度D。或者，如图3C所示，该穿孔220延伸至两绝缘保护层223的部分均扩大其宽度，例如该穿孔220及该开口223a的纵剖面呈“Ⅰ”形。抑或，如图3D所示，多个(2个)穿孔220延伸至该绝缘保护层223的部分相互连通，例如该多个穿孔220及该开口223a的纵剖面呈“Ⅱ”形。前述的该穿孔220延伸至该绝缘保护层223的扩大宽度R较佳为100μm以下。
另外，布设于该第二基板22的穿孔220位置主要对应设置于该第一基板21上的该电子元件20的相对位置。如图4A至图4C所示，该穿孔220的位置位于该电子元件20对应该第二基板22的投影范围内，其中，因于该电子元件20的四个角落处的应力较大，较容易发生脱层，故该穿孔220的位置以对应该电子元件20的四个角落较佳，且该穿孔220的位置也可对应该电子元件20的中心位置(如图4B所示)，抑或其它位置，另该穿孔220的数量可为一个或多个，且该穿孔220延伸至该绝缘保护层223的开口223a的形状可为方形(如图4A及图4B所示)或圆弧状(如图4C所示)。应可理解地，该穿孔220的位置、数量及形状等可依需求设计，并不限于上述。
所述的导电元件23结合于该第二基板22的第一表面22a与该第一基板21之间，使该第二基板22叠设于该第一基板21上，且该导电元件23电性连接该第二基板22的电性接触垫221及该第一基板21的焊垫210。
于本实施例中，该导电元件23为焊球或电镀铜柱的金属柱。
所述的封装层24形成于该第二基板22的第一表面22a与该第一基板21之间及该穿孔220中，且包覆该些导电元件23与该电子元件20。
于本实施例中，形成该封装层24的材质为聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(epoxy)或封装材(molding compound)。
另一方面，该第二基板22的第二表面22b上设有至少一电子元件25，且该电子元件25可选自封装件、主动元件、被动元件或其组合，该主动元件例如为晶片，而该被动元件例如为电阻、电容及电感。
于本实施例中，该电子元件25以覆晶方式(如通过焊锡凸块250)电性连接该外接垫222，并形成底胶26于该电子元件25与该第二基板22的第二表面22b(或绝缘保护层223)之间。应可理解地，该电子元件25也可以打线方式电性连接该外接垫222。
综上所述，本发明的封装堆叠结构2通过该穿孔220的设计，供该封装层24的材料流入，藉以增加该封装层24与该第二基板22的接触面积，尤其是该穿孔220延伸至该绝缘保护层223的开口223a的宽度大于该穿孔220的宽度，使该封装层24填充于该穿孔220及该开口223a时，得以产生锁固(lock)的效果，而增加封装层24与第二基板22的结合力，有效避免脱层的发生。
此外，该穿孔220可作为模压排气孔，以于形成该封装层24时，该封装层24可经由该穿孔220流至该第二基板22的第二表面22b，因而能排挤出气体，故能避免孔洞的发生。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (12)

1.一种封装堆叠结构，其特征为，该结构包括：
第一基板；
第二基板，其具有相对的第一表面及第二表面，使该第二基板以其第一表面通过多个导电元件叠设于该第一基板上，其中，该第二基板具有至少一连通该第一表面与第二表面的穿孔；以及
封装层，其形成于该第二基板与该第一基板之间及该穿孔中。
2.如权利要求1所述的封装堆叠结构，其特征为，该穿孔的宽度至多为50微米。
3.如权利要求2所述的封装堆叠结构，其特征为，该穿孔的宽度为10至25微米。
4.如权利要求1所述的封装堆叠结构，其特征为，该第二基板的第一表面与第二表面上具有绝缘保护层，且该穿孔延伸贯穿该绝缘保护层。
5.如权利要求4所述的封装堆叠结构，其特征为，该绝缘保护层形成有开口，且该开口连通至该穿孔。
6.如权利要求5所述的封装堆叠结构，其特征为，该开口的宽度大于该穿孔的宽度。
7.如权利要求5所述的封装堆叠结构，其特征为，该开口的宽度至多为100微米。
8.如权利要求5所述的封装堆叠结构，其特征为，该穿孔及该开口的纵剖面呈T形、Ⅰ形或Ⅱ形。
9.如权利要求1所述的封装堆叠结构，其特征为，该结构还包括接置于该第一基板上并电性连接该第一基板的电子元件。
10.如权利要求9所述的封装堆叠结构，其特征为，该穿孔设于该第二基板的位置对应该电子元件投影至该第二基板的范围内。
11.如权利要求10所述的封装堆叠结构，其特征为，该穿孔设于该第二基板的位置对应该电子元件投影至该第二基板的角落处。
12.如权利要求1所述的封装堆叠结构，其特征为，该结构还包括接置于该第二基板上并电性连接该第二基板的电子元件。
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