CN103633037A - 封装结构及制造方法 - Google Patents
封装结构及制造方法 Download PDFInfo
- Publication number
- CN103633037A CN103633037A CN201210309071.0A CN201210309071A CN103633037A CN 103633037 A CN103633037 A CN 103633037A CN 201210309071 A CN201210309071 A CN 201210309071A CN 103633037 A CN103633037 A CN 103633037A
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- hole
- substrate
- exhaust hole
- layer
- encapsulating structure
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Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000005538 encapsulation Methods 0.000 title abstract 4
- 239000000758 substrate Substances 0.000 claims abstract description 105
- 239000000853 adhesive Substances 0.000 claims description 55
- 230000001070 adhesive effect Effects 0.000 claims description 55
- 238000000034 method Methods 0.000 claims description 33
- 239000000945 filler Substances 0.000 claims description 20
- 239000002245 particle Substances 0.000 claims description 20
- 238000005553 drilling Methods 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 238000007789 sealing Methods 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000000084 colloidal system Substances 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000000047 product Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 230000003467 diminishing effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16151—Cap comprising an aperture, e.g. for pressure control, encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (13)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210309071.0A CN103633037A (zh) | 2012-08-27 | 2012-08-27 | 封装结构及制造方法 |
TW101131277A TWI492682B (zh) | 2012-08-27 | 2012-08-29 | 封裝結構及製造方法 |
US13/859,561 US8981571B2 (en) | 2012-08-27 | 2013-04-09 | Package assembly and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210309071.0A CN103633037A (zh) | 2012-08-27 | 2012-08-27 | 封装结构及制造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN103633037A true CN103633037A (zh) | 2014-03-12 |
Family
ID=50147304
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210309071.0A Pending CN103633037A (zh) | 2012-08-27 | 2012-08-27 | 封装结构及制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8981571B2 (zh) |
CN (1) | CN103633037A (zh) |
TW (1) | TWI492682B (zh) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106098570A (zh) * | 2016-06-23 | 2016-11-09 | 江阴芯智联电子科技有限公司 | 空腔式塑料封装模块结构及其制造方法 |
CN106409823A (zh) * | 2015-08-03 | 2017-02-15 | 爱思开海力士有限公司 | 包括平面层叠的半导体芯片的半导体封装 |
CN108074881A (zh) * | 2016-11-10 | 2018-05-25 | 矽品精密工业股份有限公司 | 封装堆叠结构 |
CN109545754A (zh) * | 2018-11-22 | 2019-03-29 | 京东方科技集团股份有限公司 | 一种芯片的封装结构、封装方法、显示装置 |
CN111834438A (zh) * | 2019-04-18 | 2020-10-27 | 西部数据技术公司 | 半导体部件背侧上用于减轻堆叠封装中的分层的孔结构 |
CN113658920A (zh) * | 2021-08-16 | 2021-11-16 | 长鑫存储技术有限公司 | 封装基板、半导体结构及封装基板的制作方法 |
CN111834438B (zh) * | 2019-04-18 | 2024-05-31 | 西部数据技术公司 | 半导体部件背侧上用于减轻堆叠封装中的分层的孔结构 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6044473B2 (ja) * | 2013-06-28 | 2016-12-14 | 株式会社デンソー | 電子装置およびその電子装置の製造方法 |
TWI576032B (zh) * | 2014-05-26 | 2017-03-21 | 旭德科技股份有限公司 | 基板結構及其製作方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010042908A1 (en) * | 2000-05-18 | 2001-11-22 | Akira Okada | Semiconductor device and manufacturing method of semiconductor device |
US20020173074A1 (en) * | 2001-05-16 | 2002-11-21 | Walsin Advanced Electronics Ltd | Method for underfilling bonding gap between flip-chip and circuit substrate |
US20060103021A1 (en) * | 2004-11-15 | 2006-05-18 | Cheng-Cheng Liu | BGA package having substrate with exhaust hole |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5847458A (en) * | 1996-05-21 | 1998-12-08 | Shinko Electric Industries Co., Ltd. | Semiconductor package and device having heads coupled with insulating material |
KR100403142B1 (ko) * | 1999-10-15 | 2003-10-30 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 |
US20030155656A1 (en) * | 2002-01-18 | 2003-08-21 | Chiu Cindy Chia-Wen | Anisotropically conductive film |
US20070138644A1 (en) * | 2005-12-15 | 2007-06-21 | Tessera, Inc. | Structure and method of making capped chip having discrete article assembled into vertical interconnect |
US8525345B2 (en) * | 2010-03-11 | 2013-09-03 | Yu-Lin Yen | Chip package and method for forming the same |
JP2012028744A (ja) * | 2010-06-22 | 2012-02-09 | Panasonic Corp | 半導体装置用パッケージおよびその製造方法ならびに半導体装置 |
-
2012
- 2012-08-27 CN CN201210309071.0A patent/CN103633037A/zh active Pending
- 2012-08-29 TW TW101131277A patent/TWI492682B/zh active
-
2013
- 2013-04-09 US US13/859,561 patent/US8981571B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010042908A1 (en) * | 2000-05-18 | 2001-11-22 | Akira Okada | Semiconductor device and manufacturing method of semiconductor device |
US20020173074A1 (en) * | 2001-05-16 | 2002-11-21 | Walsin Advanced Electronics Ltd | Method for underfilling bonding gap between flip-chip and circuit substrate |
US20060103021A1 (en) * | 2004-11-15 | 2006-05-18 | Cheng-Cheng Liu | BGA package having substrate with exhaust hole |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106409823A (zh) * | 2015-08-03 | 2017-02-15 | 爱思开海力士有限公司 | 包括平面层叠的半导体芯片的半导体封装 |
CN106098570A (zh) * | 2016-06-23 | 2016-11-09 | 江阴芯智联电子科技有限公司 | 空腔式塑料封装模块结构及其制造方法 |
CN106098570B (zh) * | 2016-06-23 | 2019-01-01 | 江阴芯智联电子科技有限公司 | 空腔式塑料封装模块结构及其制造方法 |
CN108074881A (zh) * | 2016-11-10 | 2018-05-25 | 矽品精密工业股份有限公司 | 封装堆叠结构 |
CN108074881B (zh) * | 2016-11-10 | 2019-10-01 | 矽品精密工业股份有限公司 | 封装堆叠结构 |
CN109545754A (zh) * | 2018-11-22 | 2019-03-29 | 京东方科技集团股份有限公司 | 一种芯片的封装结构、封装方法、显示装置 |
CN111834438A (zh) * | 2019-04-18 | 2020-10-27 | 西部数据技术公司 | 半导体部件背侧上用于减轻堆叠封装中的分层的孔结构 |
CN111834438B (zh) * | 2019-04-18 | 2024-05-31 | 西部数据技术公司 | 半导体部件背侧上用于减轻堆叠封装中的分层的孔结构 |
CN113658920A (zh) * | 2021-08-16 | 2021-11-16 | 长鑫存储技术有限公司 | 封装基板、半导体结构及封装基板的制作方法 |
Also Published As
Publication number | Publication date |
---|---|
US8981571B2 (en) | 2015-03-17 |
TW201410094A (zh) | 2014-03-01 |
TWI492682B (zh) | 2015-07-11 |
US20140054792A1 (en) | 2014-02-27 |
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PB01 | Publication | ||
PB01 | Publication | ||
C53 | Correction of patent of invention or patent application | ||
CB02 | Change of applicant information |
Address after: 528437 No. 9 Jianye East Road, Torch Development Zone, Guangdong, Zhongshan Applicant after: - the core of Electronic Science and Technology (Zhongshan) Co., Ltd. Address before: 528437 export processing zone of Torch Development Zone, Guangdong, Zhongshan Applicant before: Ambit Electronics (Zhongshan) Co., Ltd. |
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COR | Change of bibliographic data |
Free format text: CORRECT: APPLICANT; FROM: AMBIT MICROSYSTEMS (ZHONGSHAN) CORPORATION TO: XUNXIN ELECTRONIC TECHNOLOGY (ZHONGSHAN) CO., LTD. |
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Application publication date: 20140312 |