CN111834438A - 半导体部件背侧上用于减轻堆叠封装中的分层的孔结构 - Google Patents
半导体部件背侧上用于减轻堆叠封装中的分层的孔结构 Download PDFInfo
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Abstract
本发明题为“半导体部件背侧上用于减轻堆叠封装中的分层的孔结构”。本发明公开了一种工艺,所述工艺包括在部件背侧上形成一个或多个孔,在模具套中形成真空,并且使所述部件背侧与所述模具套中的模具化合物接合。所述一个或多个孔形成孔结构。所述孔结构可包括彼此平行或正交的多个孔。所述孔具有孔宽度、孔深度和孔间距。可改变这些特性以使在所述模具套中形成所述真空之后捕捉的空气保留的可能性最小化。
Description
背景技术
当空气或其他气体被捕捉在半导体器件的大气密封区域中时,在半导体器件中发生分层。例如,在将部件附接膜安装到硅晶片上的工艺期间可能发生分层。分层会阻碍散热,导致在半导体封装器件中的操作热点,这可导致在器件操作期间的热失控。热失控为半导体封装的主要故障机制之一。分层对散热的影响可通过结壳热阻分析来量化,该分析显示电阻值随着分层的增加而增加。
可利用故障分析、横截面分析和扫描电子显微镜分析来识别分层位置,诸如在部件间结合部处以及在部件与衬底结合部处。可在直通扫描操作模式下使用扫描声学显微镜来检测分层。任何检测到的分层可在所得的图像中表现为暗化区域,因为超声信号未能穿过大气隔离的空气凹坑。
用于处理分层的常规技术可减少大气隔离的空气的区域,但不能完全消除这些区域。在固化部件附接之后,粘结力、粘结时间和粘结温度均可对分层产生影响。所利用的模制工艺也可通过增强工艺压力影响分层减少。另外的技术诸如改变部件本身可使分层最小化。
附图说明
为了容易地识别对任何特定元件或动作的讨论,参考标号中最有意义的一个或多个数位是指首次引入该元件的附图标号。
图1示出根据一个实施方案的孔构型。
图2示出根据一个实施方案的孔构型。
图3示出根据一个实施方案的孔构型。
图4示出根据一个实施方案的孔构型。
图5示出根据一个实施方案的模制装置500。
图6示出根据一个实施方案的半导体封装制造系统600。
图7示出根据一个实施方案的半导体封装制造工艺700。
具体实施方式
图1示出单孔部件102的横截面视图和底部(背侧)视图。单孔部件102包括具有孔宽度106和孔深度108的孔104。单孔部件102可为随后粘结到另一个部件(例如,存储器管芯)上的任何电子部件。
单孔部件102包括部件顶侧和部件背侧。顶侧可包括半导体部件。孔104被蚀刻到部件背侧中。可利用各种蚀刻技术,包括激光蚀刻、化学蚀刻、物理蚀刻(例如,通过以金刚石为尖端的蚀刻设备)等。如图所示,孔104平分单孔部件102。部件背侧包括由第一组相对边缘确定的宽度和由第二组相对边缘确定的长度,并且宽度小于长度。孔104平分部件背侧并且从第一组相对边缘延伸。气体(如果被捕捉)可被捕捉在部件的中间,因此可利用具有孔104的构型。然而,气体可被捕捉在其他区域,诸如对应于顶侧上的半导体部件的区域。从而,在一些实施方案中,孔104可不平分单孔部件102。在生产期间,可基于例如顶侧特征或基于后制造测试或使用的学习来控制蚀刻设备以定位孔104,使分层最小化。
如图所示,孔104从第一组相对边缘中的每一个的中点延伸。选择第一组相对边缘以使孔104的长度最小化。可选择这种孔构型以使一凹坑的气体在真空工艺期间可行进的距离最小化,以增加移除捕捉的气体的可能性。其他实施方案可利用其他孔构型,包括对角孔、从一个边缘延伸至相邻边缘的孔、从第二组相对边缘延伸的孔等。孔104具有孔宽度106和孔深度108。孔宽度106可为约10μm至约20μm。孔深度108可为约3μm。
图2示出具有正交孔202的部件的部件的横截面视图和底部(背侧)视图。正交孔206和正交孔204形成在部件背侧上。可利用各种蚀刻技术形成孔,包括激光蚀刻、化学蚀刻、物理蚀刻(例如,通过以金刚石为尖端的蚀刻设备)等。如图所示,正交孔204和正交孔206各自平分具有正交孔202的部件的背侧。正交孔204平分部件背侧并从第一组相对边缘延伸,并且正交孔206平分部件背侧并从第二组相对边缘延伸。一般来讲,无论平行于部件背侧的宽度还是长度,孔从部件背侧的一个边缘连续地运行到另一个边缘。
在一些实施方案中,正交孔204和正交孔206中的一者或两者可不平分部件背侧。在生产期间,可改变蚀刻设备以定位孔,使分层最小化。如图所示,正交孔204和正交孔206各自从第一组和第二组相对边缘中的每一个的中点分别延伸。可选择这种孔构型以使一凹坑的气体在真空工艺期间可行进的距离最小化,以增加移除捕捉的空气的可能性。其他实施方案可利用其他孔构型,包括对角孔、从一个边缘延伸至相邻边缘的孔等。
如图所示,正交孔204和正交孔206各自具有孔宽度208和孔深度210。然而在一些实施方案中,孔宽度208和孔深度210可不同于正交孔204和正交孔206。孔宽度208可为约10μm至约20μm。孔深度210可为约3μm。
图3示出具有多个平行孔302的部件的横截面和底部(背侧)视图。具有多个平行孔302的部件包括以恒定或可变孔间距306形成的平行孔304。平行孔304中的每一个具有孔宽度和孔深度,如前所述。在一些情况下,该宽度和深度可为所有平行孔304的相同宽度和深度,并且在其他情况下,平行孔304中的一些或全部可具有不同的孔宽度和/或孔深度。孔宽度可为约10μm至约20μm,并且可朝向部件的边缘(例如,靠近部件背侧的中心的较宽的孔)减小。
孔间距306为在平行孔304中的每一个之间的距离。孔间距306可为约100μm至约1mm。孔间距306在具有多个平行孔302的部件上可为均匀的,或者可变化。例如,孔间距306可在靠近部件背侧的中心变窄(可减小)。
孔结构可取决于部件顶侧上的表面特征,或取决于部件堆叠中的下面的部件/衬底的表面特征。空气凹坑可在任何位置形成,但可更经常地形成于部件背侧的中心区域中。在一个实施方案中,可在中心区域上蚀刻更细间距的孔(和/或较宽的槽)阵列,以改善该区域中潜在捕捉的空气的排出。例如,孔间距306在部件背侧的中心处可比朝向边缘处小。这种较小的孔间距306在部件背侧的中心处形成更细的、或更高密度的孔结构。如前文所述,具有多个平行孔302的部件的其他实施方案可利用其他孔构型,包括对角孔、从一个边缘延伸至相邻边缘的孔、从导致较大孔长度的相对边缘延伸的孔等。
图4示出具有孔矩阵402的部件的横截面底部(背侧)视图。具有孔矩阵402的部件包括在第一孔间距408处形成的第一平行孔404和在第二孔间距410处的与第一平行孔404正交的第二平行孔406。
如先前针对其他实施方案所述,孔宽度和深度可为所有第一平行孔404和/或第二平行孔406的相同宽度和深度,并且在其他情况下,孔中的一些或全部可具有不同的宽度和/或深度。孔宽度可为约10μm至约20μm,并且可朝向部件的边缘(例如,靠近部件背侧的中心的较宽的孔)减小。第一孔间距408和/或第二孔间距410可为约100μm至约1mm。任一间距在部件背侧上可为均匀的,或者可变化。孔结构可取决于部件顶侧上的表面特征,或取决于部件堆叠中的下面的部件/衬底的表面特征。空气凹坑可在任何位置形成,但可更经常地形成于部件背侧的中心区域中。在一个实施方案中,可在中心区域上蚀刻更细间距的孔(和/或较宽的槽)阵列,以改善该区域中潜在捕捉的空气的排出。例如,第一孔间距408和第二孔间距410中的一者或两者在部件背侧的中心处可比朝向边缘处小。具有孔矩阵402的部件的其他实施方案可利用其他孔构型,包括对角孔、从一个边缘延伸至相邻边缘的孔、从导致较大孔长度的相对边缘延伸的孔等。
图5示出用于一个实施方案中的部件502的模制装置500。部件502可为(例如)存储器管芯,该存储器管芯包括在其顶侧上的半导体部件。部件与零个或更多个其他部件一起形成在衬底506上的堆叠或封装中。部件附接膜504可安装到每个部件502的部件背侧。这可在半导体晶片切片(从中获得部件502)之前发生。从而在部件附接(例如,如图所示的堆叠)之后,部件附接膜504定位在堆叠的每个部件之间以及在部件和衬底506之间。然后可经由粘结线或本领域已知的其他方法电联接部件502。由于在部件502和部件附接膜504之间的界面中的不合规定之处,大气隔离的空气可趋于在部件502的背侧和部件附接膜504之间形成。在一些情况下,这种大气隔离的空气也可趋于在部件附接膜504和衬底506之间发生。在一些情况下,从而孔结构可包括在衬板506的顶侧上。
形成在部件背侧上的孔结构可在部件附接期间在粘结力下排出大气隔离的空气(或其他气体)。在模具套510中的模制工艺期间以及在用模具化合物填充半导体封装之前,可在模具套510中生成真空512以将空气排出模具套510。孔结构508(诸如前述实施方案中的一个)将可具有大气隔离的空气的半导体封装的区域与模具套510内侧的气流514互连。从而,当将真空512应用到模具套510时,真空512也被应用到大气隔离的空气,将空气从部件间区域驱动。例如,真空512可低于工艺压力。在一个实施方案中,真空512为约1.0托。可将真空512应用约5s。在一个实施方案中,压力从环境压力减少到约01.0托为约5s。此外,工艺温度可为约175℃。将每个部件添加到部件堆叠可需要约400ms至约1s。该工艺包括压制成模具化合物并添加(例如)粘结线(即,在部件之间的电连接)。
图6示出半导体封装制造系统600的一个实施方案,该半导体封装制造系统包括研磨器602、激光器604、部件附接膜安装系统606、晶片锯608、部件附接系统610、线粘结系统612、模具套614和真空系统616。
研磨器602接收晶片。晶片可为硅晶片。硅晶片可用顶侧上的半导体封装部件预制造。然后,研磨器602研磨晶片背侧(并从而研磨部件背侧),以制备用于部件附接膜的晶片。
激光器604蚀刻晶片背侧上的孔结构。激光器604可相对于晶片移动,晶片可相对于激光器604被移动,或两者将孔结构蚀刻到晶片上。由于可利用晶片形成多个部件,因此可将多个孔结构蚀刻到晶片的背侧中。激光器604可接收孔改变,诸如控制信号,以修改被嵌入晶片中的孔结构。孔改变可增加孔;改变孔的位置;改变孔宽度、孔深度或孔间距;等。在一个实施方案中,激光器604以约2W的功率、约40kHz的频率和约200mm/s的速度操作。在其他实施方案中,可利用化学蚀刻设备或物理蚀刻设备(例如,以金刚石为尖端的蚀刻设备)将孔蚀刻到晶片中。
部件附接膜安装系统606安装部件附接膜到晶片。部件附接膜安装系统606可为捕捉的空气(或其他气体)的来源。
晶片锯608将部件中的晶片切块。晶片锯608可接收关于在何处对晶片进行切割以形成部件的指令。
部件附接系统610将每个部件添加到半导体封装。可将每个部件添加到衬底,堆叠到另一个部件上等。这可包括将部件压制到模具化合物上。将部件添加到堆叠可需要约400ms至约1s。该工艺可由机器人系统执行。
线粘结系统612将粘结线附接到衬底和部件。粘结线形成用于半导体封装的电联接器。粘结线的添加可包括在堆叠部件的时间中。
模具套614将模具化合物添加到半导体封装。在该工艺期间,部件背侧与模具套614中的模具化合物接合。模具套614也联接到真空系统616。模具套614和真空系统616一起形成系统以从在部件(例如,部件及其部件附接膜)之间移除捕捉的空气。真空系统616在模具套614上抽吸真空,并且可将压力从环境压力在约5s内减少到约1.0托。工艺温度可为约175℃。
然后发送半导体封装以另外的处理。另外的处理可包括确定所利用的孔结构的有效性。可通过向激光器604或相对于激光器604的控制晶片的其他部件发送孔改变控制信号改变无效孔结构。无效孔结构可为导致故障次数超过阈值的孔结构。也可利用其他输入改变激光器604或相对于激光器604的控制晶片的其他部件。
半导体封装制造系统600可根据图7所示的工艺操作。
参考图7,半导体封装制造工艺700在一个实施方案中首先接收晶片(框702)。晶片可为制造的半导体硅晶片。然后研磨晶片的背侧(框704)。在晶片被分成多个部件时,研磨晶片背侧使每个部件背侧研磨。在部件背侧中形成孔结构(框706)。在晶片被切块成多个部件时,在晶片背侧上形成孔结构也使在每个部件背侧上形成孔结构。从而在晶片切块之前执行该步骤可更有效。孔结构可为参考图1至图4所示或讨论的孔构型中的一者。
将部件附接膜安装到晶片(框708),具体地讲安装到晶片背侧。该工艺易于在晶片背侧(且从而在部件背侧)和部件附接膜之间引入大气隔离的空气(或其他气体)。然后将晶片切块(框710),例如使用模具锯将其切块成单个部件。每个部件可安装有部件附接膜,并且从而可具有捕捉的空气。拾取并附接每个部件(框712)。部件可通过堆叠附接到衬底或另一个部件。将部件添加到堆叠可需要约400ms至约1s。在衬底和任何安装到衬底的部件的部件附接膜之间还可发生捕捉的空气。在一些实施方案中,衬底还具有蚀刻在其中的孔结构。
然后将部件电联接(框714),例如使用在衬底和部件之间以及在部件之间提供电联接的粘结线。执行线粘合的时间可包括执行部件附接的时间。执行真空模制(框716)。可在模具套上抽吸真空。真空可抽吸压力,使其在约5s内从环境压力下降至约1.0托。还将模具化合物引入模具套中。在该工艺期间,部件背侧与模具套中的模具化合物接合。工艺温度可为约175℃。然后可执行另外的工艺(框718)。另外的工艺可包括激光标记、球附接、封装锯切、测试等。该测试可导致应用到后续晶片的孔结构改变。可基于超过阈值的故障次数来改变孔结构。后续晶片可具有更多的孔;较少的孔;改变的孔位置;不同的孔宽度、孔深度或孔间距等。例如,可蚀刻初始晶片以在所得的部件上具有单孔。这种晶片仍可由于捕捉的空气而产生故障。可控制蚀刻设备以产生多个平行孔。这些孔的这些间距可朝向所得部件的中心变细。另选地,捕捉的可与部件顶侧上的部件相关。可移动孔在所得部件上的位置以对应于故障位置,增加在真空模制工艺期间移除捕捉的空气的可能性。可利用其他孔结构以使在真空模制工艺期间捕捉的空气保留的可能性最小化。
Claims (20)
1.一种半导体部件的堆叠,包括:
第一半导体部件,所述第一半导体部件定位在第二半导体部件上,其中所述第一半导体部件包括在一个侧面上形成的图案,另外,其中所述侧面面向所述第二半导体部件。
2.根据权利要求1所述的半导体部件的堆叠,其中所述图案包括延伸到所述第一半导体部件的边缘的至少一个孔。
3.根据权利要求2所述的半导体部件的堆叠,其中所述至少一个孔包括具有孔间距的第一组多个平行孔,所述孔间距朝向所述第一半导体部件的中心线变小。
4.根据权利要求2所述的半导体部件的堆叠,其中所述至少一个孔包括第一组多个平行孔和与所述第一组多个平行孔正交的第二组多个平行孔,从而形成孔的矩阵。
5.根据权利要求2所述的半导体部件的堆叠,所述至少一个孔包括具有可变孔宽度的多个平行孔。
6.根据权利要求5所述的半导体部件的堆叠,所述可变孔宽度朝向所述第一半导体部件的边缘减小。
7.根据权利要求2所述的半导体部件的堆叠,所述至少一个孔具有介于10μm和20μm之间的孔宽度。
8.根据权利要求2所述的半导体部件的堆叠,所述至少一个孔具有3μm的孔深度。
9.根据权利要求2所述的半导体部件的堆叠,所述至少一个孔包括具有介于100μm和1mm之间的孔间距的多个平行孔。
10.根据权利要求9所述的半导体部件的堆叠,所述孔间距朝向所述第一半导体部件的边缘增加。
11.根据权利要求2所述的半导体部件的堆叠,所述至少一个孔包括具有可变孔深度的多个平行孔。
12.一种装置,包括:
第一半导体部件,所述第一半导体部件具有定位在第二半导体部件上的背侧部分;并且
其中所述第一半导体部件的所述背侧部分包括一个或多个孔,以允许空气在所述第一半导体部件和所述第二半导体部件之间流动。
13.根据权利要求12所述的装置,其中所述一个或多个孔包括第一组多个平行孔。
14.根据权利要求13所述的装置,其中所述第一组多个平行孔具有孔间距,所述孔间距朝向所述背侧部分的中心变小。
15.根据权利要求13所述的装置,其中所述一个或多个孔还包括与所述第一组多个平行孔正交的第二组多个平行孔,形成孔的矩阵。
16.根据权利要求12所述的装置,其中所述背侧部分包括比部件宽度长的部件长度,所述一个或多个孔包括平分所述背侧部分且在所述部件长度上从边缘延伸到边缘的第一孔。
17.根据权利要求16所述的装置,其中所述一个或多个孔还包括平分所述背侧部分且从所述部件宽度的边缘延伸到边缘的第二孔。
18.根据权利要求17所述的装置,其中所述第一孔和所述第二孔为正交孔。
19.根据权利要求17所述的装置,其中所述第一孔和所述第二孔不正交。
20.一种半导体封装,包括:
装置,所述装置用于将第一半导体部件与第二半导体部件分离;和
装置,所述装置用于使气体能够在所述第一半导体部件和用于将所述第一半导体部件与所述第二半导体部件分离的所述装置之间流动。
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---|---|---|---|---|
JP2003142509A (ja) * | 2001-08-21 | 2003-05-16 | Oki Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US20030141103A1 (en) * | 2002-01-31 | 2003-07-31 | Ng Wee Lee | PCB solder pad geometry including patterns improving solder coverage |
US20070045779A1 (en) * | 2005-09-01 | 2007-03-01 | Hiatt W M | Methods for forming through-wafer interconnects, intermediate structures so formed, and devices and systems having at least one solder dam structure |
CN101049045A (zh) * | 2004-10-27 | 2007-10-03 | 皇家飞利浦电子股份有限公司 | 减少mems器件中的空气阻尼 |
US20080308946A1 (en) * | 2007-06-15 | 2008-12-18 | Micron Technology, Inc. | Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices |
US20080315369A1 (en) * | 2006-06-29 | 2008-12-25 | Yeo Song Yun | Semiconductor device and semiconductor package having the same |
US20130017764A1 (en) * | 2011-07-15 | 2013-01-17 | Allison William C | Polishing pad with aperture |
KR20130042311A (ko) * | 2011-10-18 | 2013-04-26 | 에스케이하이닉스 주식회사 | 반도체 적층 패키지 및 그 제조 방법 |
CN103633037A (zh) * | 2012-08-27 | 2014-03-12 | 国碁电子(中山)有限公司 | 封装结构及制造方法 |
US20160276313A1 (en) * | 2015-03-17 | 2016-09-22 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
CN109585370A (zh) * | 2017-09-28 | 2019-04-05 | 英飞凌科技股份有限公司 | 包括自对准背侧导电层的半导体芯片及其制造方法 |
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003142509A (ja) * | 2001-08-21 | 2003-05-16 | Oki Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US20030141103A1 (en) * | 2002-01-31 | 2003-07-31 | Ng Wee Lee | PCB solder pad geometry including patterns improving solder coverage |
CN101049045A (zh) * | 2004-10-27 | 2007-10-03 | 皇家飞利浦电子股份有限公司 | 减少mems器件中的空气阻尼 |
US20070045779A1 (en) * | 2005-09-01 | 2007-03-01 | Hiatt W M | Methods for forming through-wafer interconnects, intermediate structures so formed, and devices and systems having at least one solder dam structure |
US20080315369A1 (en) * | 2006-06-29 | 2008-12-25 | Yeo Song Yun | Semiconductor device and semiconductor package having the same |
US20080308946A1 (en) * | 2007-06-15 | 2008-12-18 | Micron Technology, Inc. | Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices |
US20130017764A1 (en) * | 2011-07-15 | 2013-01-17 | Allison William C | Polishing pad with aperture |
KR20130042311A (ko) * | 2011-10-18 | 2013-04-26 | 에스케이하이닉스 주식회사 | 반도체 적층 패키지 및 그 제조 방법 |
CN103633037A (zh) * | 2012-08-27 | 2014-03-12 | 国碁电子(中山)有限公司 | 封装结构及制造方法 |
US20160276313A1 (en) * | 2015-03-17 | 2016-09-22 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
CN109585370A (zh) * | 2017-09-28 | 2019-04-05 | 英飞凌科技股份有限公司 | 包括自对准背侧导电层的半导体芯片及其制造方法 |
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US20200335481A1 (en) | 2020-10-22 |
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