TWI620313B - 用於嵌入半導體晶粒的橋結構 - Google Patents
用於嵌入半導體晶粒的橋結構 Download PDFInfo
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- TWI620313B TWI620313B TW103140857A TW103140857A TWI620313B TW I620313 B TWI620313 B TW I620313B TW 103140857 A TW103140857 A TW 103140857A TW 103140857 A TW103140857 A TW 103140857A TW I620313 B TWI620313 B TW I620313B
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- Prior art keywords
- semiconductor
- bridge structure
- trench
- wafer
- die
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Abstract
本發明揭示一種半導體裝置及其製造方法。該半導體裝置包含安裝於一基板之一表面上之一半導體晶粒,諸如一控制器晶粒。一橋結構亦安裝至該基板,其中該半導體晶粒裝配於形成於該橋結構之一底面中之一溝渠內。該橋結構可由一半導體晶圓形成為用作一機械間隔層之一虛設橋結構或用作一機械間隔層及一積體電路半導體晶粒兩者之一積體電路(IC)橋結構。記憶體晶粒亦可安裝於該橋結構之頂部上。
Description
對可攜式消費性電子產品之需求之強勁增長推進對高容量儲存裝置之需要。非揮發性半導體記憶體裝置(諸如快閃記憶體儲存卡)變得廣泛用於滿足對數位資訊儲存及交換之日益增長需求。其可攜性、多功能性及堅固設計以及其高可靠性及大容量已使得此等記憶體裝置理想地用於各種電子裝置(其包含(例如)數位相機、數位音樂播放器、視訊遊戲機、PDA及蜂巢式電話)中。
儘管吾人已知諸多不同封裝組態,但快閃記憶體儲存卡一般可製造為系統級封裝(SiP)或多晶片模組(MCM),其中複數個晶粒安裝及互連於一小覆蓋區基板上。一般而言,該基板可包含一剛性介電基座,其具有蝕刻於一或兩側上之一導電層。電連接形成於晶粒與(若干)導電層之間,且(若干)導電層提供用於將晶粒連接至一主機裝置之一電引線結構。一旦建立晶粒與基板之間之電連接,則通常將總成裝入提供一保護性封裝之一模製化合物中。
圖1及圖2中展示一習知半導體封裝20之一橫截面側視圖及一俯視圖(圖2中無模製化合物)。典型封裝包含附裝至一基板26之複數個半導體晶粒,諸如快閃記憶體晶粒22及一控制器晶粒24。在晶粒製程期間,複數個晶粒接合墊28可形成於半導體晶粒22、24上。類似地,複數個接觸墊30可形成於基板26上。晶粒22可附裝至基板26,且接著
晶粒24可安裝於晶粒22上。接著,藉由將接線32附裝於各自晶粒接合墊28與接觸墊30對之間而將全部晶粒電耦合至基板。一旦建立全部電連接,則可將晶粒及接線囊封於一模製化合物34中以密封封裝且保護晶粒及接線。
為最有效率地使用封裝覆蓋區,吾人已知將半導體晶粒堆疊於彼此之頂部上,彼此完全重疊或具有如圖1及圖2中所展示之一偏移。在一偏移組態中,一晶粒堆疊於另一晶粒之頂部上,使得下晶粒之接合墊保持曝露。一偏移組態提供便利地接達堆疊中之半導體晶粒之各者上之接合墊的一優點。儘管圖1中之堆疊中展示兩個記憶體晶粒,但吾人已知在堆疊中提供更多記憶體晶粒,諸如(例如)四個或八個記憶體晶粒。
為增加半導體封裝中之記憶體容量,同時維持或減小封裝之總體大小,記憶體晶粒之大小已變得比封裝之總體大小更大。因而,記憶體晶粒之覆蓋區通常近乎與基板之覆蓋區一樣大。
控制器晶粒24一般小於記憶體晶粒22。據此,將控制器晶粒24習知地放置於記憶體晶粒堆疊之頂部處。此組態具有某些缺點。例如,難以形成自控制器晶粒上之晶粒接合墊向下至基板之大量接線。吾人已知在控制器晶粒下方提供一內插器或重分佈層,使得自控制器晶粒至內插器之接線被建立,且接著建立自內插器向下至基板之接線。然而,此增加半導體裝置製造之成本及複雜性。再者,自控制器晶粒至基板之接線之相對較長長度使半導體裝置之操作變慢。
20‧‧‧半導體封裝
22‧‧‧快閃記憶體晶粒/半導體晶粒
24‧‧‧控制器晶粒/半導體晶粒
26‧‧‧基板
28‧‧‧晶粒接合墊
30‧‧‧接觸墊
32‧‧‧接線
34‧‧‧模製化合物
100‧‧‧半導體裝置/封裝
102‧‧‧基板
104‧‧‧通孔
106‧‧‧電跡線
108‧‧‧接觸墊
112‧‧‧被動組件
114‧‧‧半導體晶粒
116‧‧‧晶粒接合墊
118‧‧‧接線
120‧‧‧橋結構
120a‧‧‧虛設橋結構
120b‧‧‧積體電路(IC)橋結構
122a‧‧‧軌條
122b‧‧‧軌條
124‧‧‧晶粒接合墊
130‧‧‧積體電路
140‧‧‧半導體晶粒
142‧‧‧積體電路
144‧‧‧接線
150‧‧‧模製化合物
180‧‧‧半導體晶粒
200‧‧‧步驟
204‧‧‧步驟
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300‧‧‧半導體晶圓
302‧‧‧溝渠
304‧‧‧第一主表面
305‧‧‧第二主表面
306‧‧‧鋸片
308‧‧‧劃割線
310‧‧‧平坦部
312a‧‧‧劈開點
312b‧‧‧劈開點
314a‧‧‧劈開點
314b‧‧‧劈開點
h1‧‧‧橋結構之高度
h2‧‧‧溝渠之高度
h3‧‧‧高度
h4‧‧‧空間
w‧‧‧寬度
圖1係一習知半導體裝置之一先前技術邊視圖,其包含堆疊成一偏移關係之一對半導體晶粒。
圖2係一習知半導體裝置之一先前技術邊視圖,其包含堆疊成一重疊關係且由一間隔層分離之一對半導體晶粒。
圖3係根據本發明之實施例之用於形成一半導體晶粒之一流程圖。
圖4係根據本發明之一第一實施例之一半導體裝置之製造中之一階段之一透視圖。
圖5係根據本發明之一第一實施例之一半導體裝置之製造中之一進一步階段之一透視圖。
圖5A係根據本發明之一替代實施例之一半導體裝置之製造中之一階段之一透視圖。
圖6係根據本發明之實施例之用於形成一橋晶圓之一流程圖。
圖7至圖9係根據本發明之一實施例之包含溝渠之一經部分處理之晶圓之俯視圖、透視圖及仰視圖。
圖10至圖13係根據本發明之第一實施例之一虛設橋結構之不同視圖。
圖14係根據本發明之實施例之一橋結構之一邊視圖。
圖15係根據本發明之一第一實施例之一半導體裝置之製造中之一進一步階段之一透視圖。
圖16係根據本發明之一第一實施例之一半導體裝置之製造中之一進一步階段之一透視圖。
圖17係根據本發明之一第一實施例之一半導體裝置之製造中之一進一步階段之一透視圖。
圖18及圖19係根據本發明之一第二實施例之用於形成一IC橋結構之替代方法之流程圖。
圖20及圖21係根據本發明之一實施例之包含溝渠之一IC晶圓之俯視圖及仰視圖。
圖22至圖25係根據本發明之第二實施例之一IC橋結構之不同視圖。
圖26係根據本發明之第二實施例之一半導體裝置之製造中之一階段之一透視圖。
圖27係根據本發明之第二實施例之一半導體裝置之製造中之一進一步階段之一透視圖。
圖28係根據本發明之第二實施例之一半導體裝置之製造中之一進一步階段之一透視圖。
圖29係根據本發明之第二實施例之一半導體裝置之製造中之一進一步階段之一透視圖。
圖30係根據本發明之一替代實施例之一半導體裝置之製造中之一階段之一透視圖。
圖31係根據本發明之一進一步替代實施例之一半導體裝置之製造中之一階段之一透視圖。
圖32至圖33繪示根據本發明之實施例之橋結構之進一步替代實施例之視圖。
現將參考圖3至圖33而描述本發明,在實施例中,本發明係關於一種半導體裝置,其包含安裝於一基板之一表面上之一半導體晶粒,諸如一控制器。一橋結構亦安裝至該基板,其中該半導體晶粒裝配於形成於該橋結構之一底面中之一溝渠內。該橋結構可自一半導體晶圓切割以形成為兩種不同類型之橋結構之一者。
一第一橋結構(本文中稱為一虛設橋結構)係由一半導體晶圓形成且用作一機械間隔層。在此實施例中,該半導體晶圓可包含一主表面中之溝渠列及相對主表面中之非積體電路。接著,各自半導體晶粒可自該晶圓分割成虛設橋結構且附裝至基板。
一第二橋結構(本文中稱為一IC橋結構)係由一半導體晶圓形成且用作一機械間隔層及一積體電路半導體晶粒兩者。可藉由至少兩種方
法而製造IC橋結構。在一第一方法中,在該半導體晶圓之一主表面上處理積體電路,且僅在與該主表面上之該等積體電路對準之後,在相對主表面中形成溝渠。在一第二方法中,在該半導體晶圓之一主表面中形成溝渠,且僅在與該主表面中之該等溝渠對準之後,在相對主表面上形成積體電路。接著,藉由該第一方法或該第二方法而形成之各自半導體晶粒可自該晶圓分割成IC橋結構且附裝至基板。下文中解釋此等實施例之橋結構之進一步細節。
應瞭解,本發明可體現為諸多不同形式,且不應被解釋為受限於本文中所闡述之實施例。確切而言,此等實施例經提供使得本發明將透徹完整且將對熟習此項技術者充分傳達本發明。其實,本發明意欲涵蓋此等實施例之替代例、修改方案及等效物,其等包含於由隨附申請專利範圍界定之本發明之範疇及精神內。此外,在本發明之以下詳細描述中,諸多具體細節經闡述以提供對本發明之透徹理解。然而,一般技術者應清楚,可在無此等具體細節之情況下實踐本發明。
如本文中所使用,術語「頂部」及「底部」、「上」及「下」、及「垂直」及「水平」僅供例示及說明,且並非意指限制本發明之描述,此係因為所引用項之位置及定向可交換。此外,如本文中所使用,術語「實質上」及/或「約」意謂:對於一給定應用,特定尺寸或參數可在一可接受之製造容限內變動。在一實施例中,可接受之製造容限係±25%。
現將參考圖3、圖6、圖18及圖19之流程圖及圖4至圖5、圖7至圖17及圖20至圖33之視圖而解釋本發明之一實施例。儘管圖式展示一個別半導體裝置100或其之一部分,應瞭解,裝置100可與一基板面板上之複數個其他裝置100一起經批量處理以達成規模效益。該基板面板上之半導體裝置100之列數及行數可變動。
基板面板可開始於複數個基板102(例如,圖4至圖5中亦僅展示
一個此類基板)。基板102可為各種不同晶片載體介質,其包含一印刷電路板(PCB)、一引線框或一捲帶式自動接合(TAB)捲帶。基板可包含複數個通孔104、電跡線106及接觸墊108。基板102可包含更多通孔104、跡線106及墊108(圖中僅對其等之部分編號),且其等可位於不同於圖中所展示之位置的位置中。
參考圖3之流程圖,可在一步驟200中將被動組件112附裝至基板102。該一或多個被動組件可包含(例如)一或多個電容器、電阻器及/或電感器,但可考量其他組件。所展示之被動組件112(圖中僅對其等之一者編號)僅供例示,且在進一步實施例中,數目、類型及位置可變動。被動組件112可在基板102之表面上方延伸。因而,其等可安裝於下文所解釋之記憶體晶粒堆疊之覆蓋區之外部。替代地,被動組件可定位於基板102上以便裝配於安裝於基板上之一橋結構之一溝渠內,亦如下文所解釋。如圖中所展示,被動組件112可裝配於該橋結構中之該溝渠內。
在步驟204中,可將一半導體晶粒114安裝於基板102之一表面上。如下文所解釋,半導體晶粒114亦可定位於基板102上以便在橋結構安裝於基板上時裝配於橋結構之溝渠內。半導體晶粒114可為一控制器ASIC。然而,晶粒114可為其他類型之半導體晶粒,諸如DRAM或NAND。
圖5展示安裝於基板102上之半導體晶粒114。半導體晶粒114包含晶粒接合墊116,例如,圖5中標記晶粒接合墊116之一者。在一線接合步驟206中,可經由接線118而將晶粒接合墊116電耦合至基板102上之接觸墊108。應瞭解,可使用其他技術來將半導體晶粒114電耦合至基板102。例如,半導體晶粒114可為焊接至基板102之接觸墊上之一覆晶。作為一進一步實例,可藉由已知印刷程序而將導電引線印刷於晶粒接合墊與接觸墊之間以將半導體晶粒114電耦合至基板102。
所展示之晶粒接合墊116及接線118之數目僅為清楚起見,且應瞭解,在進一步實施例中,可存在更多接觸墊108、晶粒接合墊116及接線118。再者,儘管圖5中展示半導體晶粒114僅在兩側上具有晶粒接合墊及接線,但應瞭解,在進一步實施例中,半導體晶粒114可在半導體晶粒114之全部四側上具有晶粒接合墊及接線,例如圖5A中所展示。替代地,在進一步實例中,半導體晶粒114可在一側或三側上具有晶粒接合墊116及接線118。
根據本發明,可接著在步驟208中將一橋結構120安裝至基板102。橋結構120在一底面中形成有一溝渠。橋結構120可安裝於基板102上,使得半導體晶粒114(及基板102之表面上之其他可能結構)位於該溝渠內。本發明之一特徵在於:橋結構係由一半導體晶圓形成。此特徵之一優點在於:橋結構可由相同於安裝於橋結構之頂部上之其他半導體晶粒的材料製成(如下文中所解釋),藉此避免熱失配。一進一步優點在於:製造半導體裝置100之製造設備通常具有用於處置半導體晶圓之工具及程序。因此,由一半導體晶圓形成橋結構120涉及製造設備之最少額外成本及處理步驟。
現參考圖6至圖8,根據一第一實施例之虛設橋結構120a可由半導體晶圓300形成。一半導體晶圓300開始為可在步驟250中形成之晶圓材料之一晶錠。在一實例中,形成晶圓300之晶錠可為根據一丘克拉斯基區(Czochatski zone(CZ))或浮區(floating zone(FZ))程序而生長之單晶矽。然而,如下文所解釋,在其中完成之橋結構僅為機械間隔層(諸如圖6中)之實施例中,形成晶圓300之晶錠可為多晶矽或任何多晶半導體材料以減少此等虛設橋結構之材料成本。
應瞭解,除矽之外,晶圓300亦可由包含(但不限於)以下各者之任何其他半導體元素或化合物形成:IV族元素半導體、IV族化合物半導體、VI族元素半導體、III-V族半導體、II-VI族半導體、I-VII族半
導體、IV-VI族半導體、V-VI族半導體及II-V族半導體。另外,由於晶圓300用於形成圖6之實施例中之一間隔層,所以虛設橋結構120a可為超出半導體元素或化合物之各種材料。
在步驟252中,可自一晶錠切割半導體晶圓300且拋光半導體晶圓300之兩個主表面以提供光滑表面。晶圓300可具有一第一主表面304(圖9)及一相對第二主表面305(圖7)。在步驟256中,可將一砂輪應用於第二主表面305以背面研磨晶圓300(例如,自780微米至280微米),但此等厚度僅供例示且在不同實施例中可變動。圖中以虛線展示此步驟,此係因為可在實施例中跳過此步驟且使晶圓300保持其被切割時之厚度。亦可想到,隨後在程序中(例如在下文所解釋之溝渠形成步驟之後)執行背面研磨步驟256。
在步驟258中,使溝渠302(圖7及圖8中對其等之部分編號)形成至晶圓300之第二主表面305中。在實施例中,溝渠可為6毫米寬且沿平行長度跨第二主表面305延伸。溝渠302彼此隔開,使得一旦晶圓被分割(如下文所解釋),則各溝渠302定位於所得半導體晶粒之一底面中之相同位置中。例如,在一實施例中,經分割之橋結構120各具有12毫米之一寬度。在此一實例中,溝渠302可隔開12毫米(中心至中心)且經形成以便位於橋結構之寬度之中間。因此,一12毫米寬之橋結構將具有一6毫米寬溝渠,且該溝渠之各側具有3毫米。應瞭解,此等尺寸之各者僅供例示,且在進一步實施例中,此等尺寸之各者可變動。再者,儘管在一實施例中溝渠302居中於各橋結構中,但應瞭解,在進一步實施例中,溝渠302可代以在橋結構之整個寬度中更接近於一邊緣或另一邊緣。
溝渠302可形成150微米至200微米之間之一深度。應瞭解,可形成比以下佈建深或淺之溝渠302:溝渠足夠深以定位於半導體晶粒114及任何接線(其形成於半導體晶粒114上)上方,且溝渠壁與半導體晶
粒/接線之間無接觸。
可藉由各種不同技術而形成溝渠302。在一實例中,可用一鋸片306形成溝渠302(圖8),鋸片306執行至晶圓300之表面中之一「半切(half-cut)」,即,至表面中,但未完全穿過晶圓之厚度。圖8中展示鋸片已形成一些但非全部溝渠302。在此實例中,鋸片306之厚度可變動。在一實例中,鋸片306可為60微米寬。此一鋸片可進行100次穿行以在晶圓300中形成6毫米寬且具有均勻深度之一單個溝渠。可對跨晶圓300之寬度之全部溝渠重複該程序。
應瞭解,在進一步實施例中,鋸片之厚度可為不同的。例如,刀片可為1毫米(6次穿行以形成具有均勻深度之一6毫米寬溝渠)、2毫米(3次穿行以形成具有均勻深度之一6毫米寬溝渠)或6毫米(一單次穿行以形成具有均勻深度之一6毫米寬溝渠)。可考量其他刀片厚度。
在一進一步實施例中,可在具有一圓形銑刀(圖中未展示)之一銑削程序形成溝渠302。當鋸片306藉由平行於晶圓300之第二主表面305之一旋轉軸而進行半切時,該銑刀藉由垂直於第二主表面305之一旋轉軸而進行半切。該銑刀可具有(例如)6毫米之一直徑及至少為溝渠302之深度之一厚度,使得可在銑刀之一單次穿行中形成各溝渠302。在進一步實施例中,該銑刀可具有一較小直徑以便採用一次以上穿行來形成具有均勻深度之一單個溝渠。
在一進一步實施例中,可考量使用一雷射(圖中未展示)來形成溝渠302。在一此類實例中,一低功率CO2雷射可用於削磨晶圓之一部分以在第二主表面305中進行所要半切。根據所使用之雷射束之直徑,該雷射可在一單次穿行或多次穿行中形成各溝渠。
在一進一步實施例中,可在晶圓300之第二主表面305中蝕刻溝渠302。可在各種不同程序(其包含(例如)使用一液態蝕刻劑、一乾式電漿蝕刻劑或一蒸氣蝕刻劑)中蝕刻溝渠。在一實例中,跨整個第二
主表面305而施加一光阻劑(圖中未展示)。使用下文所解釋之光罩對準方法之一者,接著藉由使用超紫外光而將第二主表面305上之該光阻劑(圖中未展示)曝露於一經對準之溝渠光罩(圖中未展示)。接著,使該光阻劑(圖中未展示)顯影,此導致該溝渠光罩之光學圖案被轉移為該光阻劑中之開窗(圖中未展示)。接著,在不影響該光阻劑之情況下,將晶圓300之整個第二主表面305曝露於切割第二主表面305中之溝渠的一選擇性蝕刻。在一剝離程序中移除該光阻劑以在第二主表面305中產生溝渠302。
在一實施例中,用於蝕刻溝渠302之程序可為一各向異性蝕刻,此可導致溝渠302具有矩形或近似矩形之側壁。在進一步實施例中,該程序可為一各向同性蝕刻,此可導致溝渠302具有更接近圓形之側壁。蝕刻劑之濃度及蝕刻劑保留於晶圓300上之時間兩者可經控制以提供具有所要深度及尺寸之溝渠302。
如上文所提及,在一實施例中,溝渠302之深度可在150微米至200微米之間。在一實例中,可一次性地形成此深度之一溝渠302。因此,在其中使用一60微米寬鋸片來切割一溝渠302之一實例中,可在鋸片之100次橫向穿行中將一6毫米溝渠完全切割至所要深度。在進一步實施例中,可考量各切割(或雷射或蝕刻程序)僅達到一部分深度。例如,當溝渠302係150微米深時,可存在三個單獨部分深度切割:一第一部分深度切割向下至50微米,一第二部分深度切割向下至100微米,且一第三部分深度切割向下至150微米。在進一步實施例中,用於形成全深度之部分切割/雷射/蝕刻之數目可在三個以上或三個以下變動。
因此,在使用一60微米鋸來切割一6毫米溝渠之一實例中,當在三個部分切割中形成深度時,可進行總共300次切割來形成該溝渠:跨寬度之一第一組100次切割達到一第一部分深度,跨寬度之一第二
組100次切割達到一第二部分深度,且跨寬度之一第三組100次切割達到一第三部分深度。此外,此等數目僅供例示,且可存在不同數目個橫向且部分深度之切割。並非進行跨寬度之連續切割且接著在一新深度處重複,而是可藉由進行向下至全深度之連續切割且接著跨溝渠之寬度重複而形成一溝渠302。
在相對於圖6所描述之實施例中,晶圓300之第一主表面304未被處理成包含積體電路。在此一實施例中,當判定將溝渠定位於第二主表面305上之何處時,可無需使第二主表面305上之溝渠302與第一主表面304對準。在此一實施例中,可如上文所解釋般形成溝渠,且接著,當第二主表面305面向上時,在步驟260中劃割晶圓300且將其分割成各形成一虛設橋結構120a之個別半導體晶粒。可想到,第一主表面304可包含在形成溝渠302之前需要使定位於第二主表面305上之溝渠與其對準之特徵。下文中描述用於使第二主表面305上之溝渠與第一主表面304上之特徵對準之各種實施例。
在圖6之實施例中,在分割之前,未在晶圓300上形成積體電路,及完成之虛設橋結構120a用作不具有電功能之機械間隔層。圖10及圖11展示包含溝渠302之一完成之虛設橋結構120a之俯視圖及俯視透視圖。圖12及圖13展示包含溝渠302之一完成之虛設橋結構120a之仰視圖及仰視透視圖。圖14展示在步驟208(圖3)中安裝於基板102上之後之虛設橋結構120a之一邊視圖。如圖13中所見,溝渠302在橋結構120a之一下表面中界定軌條122a及122b。在實施例中,軌條122a、122b沿橋結構120a之整個長度延伸。虛設橋結構120a可經由軌條122a、122b上之一黏著劑(諸如晶粒附著膜)而附裝至基板102。
圖14亦展示定位於溝渠302內之半導體晶粒114。溝渠302及半導體晶粒114之相對大小僅供例示且可能未按比例繪製。在一實例中,半導體晶粒114可具有約5毫米之一寬度。當接線118自半導體晶粒114
之一或多個邊緣引出時,半導體晶粒114及接線可裝配於具有6毫米之一寬度w之一溝渠內,如上文所提及。只要該溝渠足夠大以容納半導體晶粒114及接線(若存在),則此等尺寸可全部變動。
如上文所提及,橋結構120之高度h1可為(例如)約280微米,且溝渠302之高度h2可(例如)在自76微米至127微米之範圍內。此使溝渠上方之橋結構之一高度h3係153微米至204微米。此等尺寸之各者僅供例示且可在進一步實施例中變動。半導體晶粒114可具有46微米之一厚度。附著半導體晶粒114之晶粒附著膜可具有10微米之一厚度,且附著橋結構120之晶粒附著膜可具有20微米之一厚度。就此等尺寸而言,可在半導體晶粒114上方之溝渠302內存在自117微米至168微米範圍內之一空間h4。此空間足夠大以使接線可被使用。在進一步實施例中,此等尺寸可變動。例如,在進一步實施例中,空間h4可為106微米。
再次參考圖3之流程圖及圖15之透視圖,在步驟214中,可將一或多個半導體晶粒140堆疊於虛設橋結構120a之頂部上。圖中以虛線展示線接合橋結構120之步驟212,此係因為可在其中橋結構不具有電功能之實施例中跳過此步驟。如圖16中所展示,半導體晶粒140可堆疊成一階梯狀組態。儘管圖中展示兩個此類半導體晶粒140,但在進一步實施例中,晶粒堆疊中可存在一單個半導體晶粒140或兩個以上半導體晶粒。半導體晶粒140可包含用作(例如)記憶體晶粒且更佳地用作NAND快閃記憶體晶粒之積體電路142,但可考量其他類型之半導體晶粒。
在步驟216中,半導體晶粒140可在一已知線接合程序(使用(例如)一接線毛細管(圖中未展示))中經由接線144而線接合至基板102上之接觸墊108。
在晶粒堆疊經形成且線接合至基板102上之接觸墊108之後,可
在步驟220中將半導體裝置100裝入模製化合物150內,且在步驟224中自面板單切半導體裝置100以形成一完成之半導體裝置100,如圖17中所展示。模製化合物150可為諸如(例如)可購自Sumitomo公司及Nitto Denko公司(兩者之總公司均在日本)之一已知環氧樹脂。其後,裝置100可在步驟226中經歷電測試及預燒。在一些實施例中,可在步驟228中將完成之半導體裝置100視情況圍封於一蓋(圖中未展示)內。
相對於圖6至圖17而描述之虛設橋結構120a係由不具有積體電路之一經部分處理之晶圓形成之一間隔層。虛設橋結構120a容許半導體晶粒114(及其他可能組件)安裝於基板之表面上且在基板之表面上方延伸,同時提供將記憶體晶粒堆疊安裝於其上之一平坦表面。
然而,如所提及,橋結構120可代以為由具有積體電路之一半導體晶圓形成之一IC橋結構120b。可依至少兩種方式製造此一實施例。在一第一製程中,在溝渠302形成於相對第二主表面305中之前使積體電路形成於晶圓300之第一主表面304上。相對於圖18之流程圖及其後之圖式而描述此實施例。在一第二製程中,在積體電路形成於相對第一主表面304中之前形成第二主表面305中之溝渠。參考圖19之流程圖及其後之圖式而描述此實施例。
現參考圖18之流程圖,可自步驟262中形成之一晶錠切割晶圓300。在此實施例中,形成晶圓300之該晶錠可為根據一CZ或FZ程序而生長之單晶矽。儘管矽係一實例,但更一般而言,該晶錠可由包含(但不限於)以下各者之任何其他半導體元素或化合物形成:IV族元素半導體、IV族化合物半導體、VI族元素半導體、III-V族半導體、II-VI族半導體、I-VII族半導體、IV-VI族半導體、V-VI族半導體及II-V族半導體。
在步驟264中,可自一晶錠切割半導體晶圓300且拋光半導體晶圓300之第一主表面304(圖20)及第二主表面305(圖21)兩者以提供光
滑表面。在步驟266中,第一主表面可經歷各種處理步驟以在第一主表面上及在第一主表面中形成積體電路。該等步驟可包含:使用垂直劃割線308及水平劃割線308來劃割第一主表面304以有助於自晶圓300分割各自半導體晶粒。在實施例中,積體電路可充當NAND快閃記憶體半導體晶粒,但可考量其他類型之積體電路。
在步驟268中,可將一砂輪應用於第二主表面305以背面研磨晶圓300,例如自780微米至280微米,但此等厚度僅供例示且可在不同實施例中變動。如同上文,可省略此步驟或在晶圓300處理之一後續階段中執行此步驟。
在步驟270中,可使佈置於第二主表面305中之溝渠302相對於第一主表面304中之各自積體電路而對準。可藉由諸多不同方法而完成此對準。在一實例中,已知第一主表面304上之積體電路之位置相對於表面304上之一選定點,且已知表面304上之該選定點之位置相對於相對表面305上之一對應選定點。在此例項中,可藉由使溝渠之位置與第二主表面305上之選定點對準而使第二主表面305上之溝渠302之位置與第一表面304上之積體電路對準。
例如,晶圓300通常包含一平坦部310(圖20至圖21),其用於識別及定向用於處理之晶圓之晶體結構。平坦部310終止於稱作劈開點之點,其中晶圓300之圓化部分與平坦部310交切。第一主表面304具有劈開點312a及312b,且第二主表面305具有劈開點314a及314b。表面304上之劈開點312a與表面305上之劈開點314a對準(其等展示為在圖20及圖21之視圖中相對於彼此翻轉,此係因為晶圓300在圖21之視圖中相對於圖20翻轉)。劈開點312b及314b同樣如此。
第一主表面304上之積體電路之位置可形成相對於劈開點之至少一者(例如劈開點312a)之一已知關係。已知劈第一主表面304上之開點312a之位置相對於第二主表面305上之劈開點314a之位置。因此,
可將第二主表面305中之溝渠302之位置設定於相對於劈開點314a之預定距離處以便確保第二主表面305中之溝渠302相對於第一主表面304中之積體電路對準。
在一進一步實施例中,當第二主表面305面向上時,一IR(紅外線)攝影機可用於透過晶圓而成像以使第二主表面上之溝渠位置與第一主表面上之積體電路對齊。紅外線具有比可見光長之一波長且具有較少散射。因此,可使第一主表面304上之積體電路之特徵自第二主表面305成像。此容許將第二主表面305中之溝渠之位置界定成與第一主表面304上之積體電路適當對準。例如,自在日本東京具有營業點之Disco公司獲知用於一晶圓之第一主表面與第二主表面之間之對準之此項技術。
應瞭解,其他技術可用於使晶圓300之第一主表面上之積體電路與晶圓300之第二主表面上之現有溝渠302對準,或用於使第二主表面上之溝渠302與第一主表面上之現有特徵對準。1996年6月25日發佈之名稱為「Double Sided Wafer,Alignment Technique」之美國專利第5,530,552號及2012年10月9日發佈之名稱為「Methods of Forming Microdevice Substrates Using Double-Sided Alignment Techniques」之美國專利第8,283,256中描述此等技術之進一步實例。該兩個專利之全文以引用方式併入本文中。
一旦使溝渠之位置相對於第一主表面上之各自積體電路適當地對準,則可在步驟274中使溝渠302形成於第二主表面305中,如圖21中之第二主表面305之視圖中所展示。可依相同於上述實施例之任何者之方式形成溝渠。在形成溝渠302之後,可在步驟276中劃割晶圓300且將其分割成個別半導體晶粒。各經分割之IC橋結構120b可用作一間隔層及一積體電路半導體晶粒,如下文所解釋。
圖19描述用於形成IC橋結構120b之一替代製程。可在步驟282中
自如上文所描述般形成之一晶錠切割晶圓300,且可在步驟284中自該晶錠切割晶圓300且拋光晶圓300,如上文所描述。在步驟286中,經切割之晶圓可經歷一背面研磨程序,但在進一步實施例中,可省略此程序或隨後在製程中執行此程序。在步驟288中,可根據上述實施例之任何者而使溝渠302形成於晶圓300之第二主表面305上。
在步驟290中,可使用於形成第一主表面304上之積體電路的光罩相對於第二主表面305上之溝渠302而對準。可使用用於第一主表面304與第二主表面305之間之對準之上述方法之任何者來執行此對準。一旦將積體電路之位置設定成與溝渠對準,則可在步驟294中使積體電路形成於晶圓300之第一主表面中及形成於晶圓300之第一主表面上。如同上文,積體電路可形成NAND快閃記憶體,但可考量其他積體電路。在形成體積電路之後,晶圓300可在步驟296中經劃割及分割以產生複數個半導體晶粒。各半導體晶粒可為一IC橋結構120b,如下文所解釋。
圖22至圖25展示藉由圖18或圖19之程序而形成之一IC橋結構120b之各種視圖。IC橋結構120b可相同於虛設橋結構120a,但可在相對於溝渠302之一表面中包含一積體電路130,且可包含晶粒接合墊124(圖22及圖23中對其等之一者編號)。如同虛設橋結構120a,IC橋結構120b可安裝於基板102上之半導體晶粒114上方,如圖26中所展示。其後,在步驟212(圖3)中,IC橋結構120b可經由接線144而線接合至基板102,如圖27中所展示。
接著,可新增額外半導體晶粒140且額外半導體晶粒140與接線144線接合,如圖27及圖28中所展示且如上文所描述。新增之半導體晶粒140之數目可大於或小於兩個。再者,由於在此實施例中IC橋結構120b本身可為一記憶體晶粒,所以在進一步實施例中無需新增額外半導體晶粒140。並非在安裝半導體晶粒140之前線接合IC橋結構
120b,而是可安裝半導體晶粒140,且接著在相同程序中使IC橋結構120b與全部半導體晶粒140線接合。
在晶粒堆疊經形成且線接合至基板102上之接合墊之後,可將裝置100裝入模製化合物150內(步驟220)且自面板單切裝置100(步驟224)以形成一完成之半導體裝置100,如圖29中所展示。其後,在步驟226中,裝置100可經歷電測試及預燒。在一些實施例中,可在步驟228中將完成之封裝100視情況圍封於一蓋(圖中未展示)內。
半導體裝置100可用作為一LGA(平面柵格陣列)封裝以便用作為一主機裝置內之可移除記憶體。在此等實施例中,接觸指(圖中未展示)可形成於基板102之一下表面上以在將半導體裝置100插入一主機裝置中之後與該主機裝置中之接針配合。替代地,半導體裝置100可用作為一BGA(球狀柵格陣列)封裝以便永久地附裝至一主機裝置內之一印刷電路板。在此等實施例中,焊球(圖中未展示)可形成於基板102之一下表面上之接觸墊上以焊接至一主機裝置之一印刷電路板上。
在上述實施例中,橋結構可由已被部分處理或完全處理之一半導體晶圓300形成。應瞭解,在晶圓300已被切割,被拋光,且形成有溝渠302之後,可自一晶圓300之任何點處分割橋結構120。
包含溝渠302之橋結構120容許將半導體晶粒114(例如一控制器)安裝於基板102之表面上,同時提供用於安裝額外記憶體晶粒之一較大平坦表面。
再者,由一半導體晶圓形成橋結構提供進一步優點。例如,如上文所提及,半導體裝置製造廠通常具有用於處置及處理半導體晶圓之資源。用於在處理晶圓300時將其固持之真空夾盤、用於將晶粒附著膜施加至晶圓300之第二主表面的設備、用於將晶圓300切割成各自橋結構120之晶圓分割設備、及用於將經分割之橋結構轉移至基板102
上之取放型機器人全部共同地存在於用於處置其他半導體晶圓之一半導體裝置製造廠中。此容許容易地製造橋結構120且幾乎不會給工廠帶來額外成本。
再者,藉由由一半導體晶圓形成橋結構120,橋結構120可由相同於半導體晶粒140之材料製成。例如,半導體晶粒114可在操作時產生熱量,且此熱量可引起橋結構120及半導體晶粒140膨脹。由於橋結構120及半導體晶粒140可具有相同材料,所以其等可具有相同熱膨脹係數。因此,當半導體加熱橋結構及橋結構上之記憶體晶粒時,其等將膨脹相同程度。應瞭解,當使用一虛設橋結構120a時,亦可使用除半導體材料之外之材料。此等材料之部分可具有相同於或類似於半導體材料之一熱膨脹係數以防止熱失配。
在以上描述中,橋結構120係一虛設橋結構或一功能性IC橋結構。然而,在進一步實施例中,橋結構120可為具有積體電路之一半導體晶粒,但為不用作一電組件之半導體晶粒。例如,可發生:由於各種原因,在形成積體電路之後將一半導體晶圓判定為有缺陷。在該情況中,並非捨棄該晶圓,而是可在該晶圓之第二主表面中形成溝渠302,如上文所解釋,且將該晶圓分割成橋結構。此等橋結構可包含積體電路,但其等可用作為無需線接合至基板102之虛設橋結構。在一進一步實施例中,在形成溝渠之前或在形成溝渠之後,可自一缺陷晶圓之第一主表面磨除積體電路,且接著將該晶圓分割成虛設橋結構。
在上述實施例中,一單個半導體晶粒114(諸如一控制器)可安裝至基板102,且接著圍封於橋結構120之溝渠302內。然而,應瞭解,在進一步實施例中,不同半導體晶粒(其包含(例如)DRAM、NAND或其他較小記憶體晶粒)及/或其他電子組件可安裝於基板上且定位於溝渠302內。
另外,圖30展示:兩個半導體晶粒114、180可安裝於溝渠302內。在進一步實施例中,兩個以上半導體晶粒及/或其他電子組件可安裝於基板上,當橋結構120安裝至基板上時,該等半導體晶粒及/或電子組件裝配於溝渠302內。
應進一步瞭解,半導體晶粒114在溝渠302內可具有不同大小。例如,圖4及圖5展示佔據溝渠302之相對較小部分之一半導體晶粒114。圖31展示佔據溝渠302之一相對較大部分之一半導體晶粒114之一進一步實施例。
在上述實施例中,溝渠302在橋結構120之相對邊緣之間延伸。然而,在一進一步實施例中,如圖32及圖33中所展示,溝渠302可僅在相對邊緣之間部分地延伸,在一邊緣處敞開,但在相對邊緣處未敞開。
總言之,本發明之一實例係關於一種用於一半導體裝置之橋結構,該橋結構包括:一第一表面;一第二表面,其相對於該第一表面;及一溝渠,其形成於該第二主表面中;其中形成該橋結構之一材料係來自由一單晶半導體元素或化合物及一多晶半導體元素或化合物組成之一群組。
在一進一步實例中,本發明係關於一種半導體裝置,其包括:一基板;一第一半導體晶粒,其安裝至該基板之一表面;及一橋結構,其安裝至該基板之該表面之該第一半導體晶粒上方,該橋結構在相鄰於該基板之該橋結構之一表面中包含一溝渠,該溝渠自該橋結構之一邊緣至少部分地延伸至該橋結構之一相對邊緣,該第一半導體晶粒裝配於該橋結構之該溝渠內。
在另一實例中,本發明係關於一種半導體裝置,其包括:一基板;一第一半導體晶粒,其直接安裝至該基板之一表面;一橋結構,其直接安裝至該基板之該表面之該第一半導體晶粒上方,該橋結構在
面向該基板之該橋結構之一表面中包含一溝渠,該溝渠在該橋結構之相對邊緣之間延伸,該第一半導體晶粒裝配於該橋結構之該溝渠內,該橋結構包括來自具有一第一厚度之一經部分處理之晶圓的一虛設間隔層;及一群組之一或多個第二半導體晶粒,其來自具有小於該第一厚度之一第二厚度之一半導體晶圓。
為說明及描述之目的,已呈現本發明之[實施方式]。此並非意欲具窮舉性或將本發明限制於所揭示之精確形式。可鑑於上述教示而進行諸多修改及變動。所描述之實施例經選擇以最佳地解釋本發明之原理及其實際應用以藉此使熟習此項技術者能夠在各種實施例中最佳地利用本發明且使本發明與適合於所預期之特定用途之各種修改一起使用。意欲使本發明之範疇由本發明之隨附申請專利範圍界定。
Claims (12)
- 一種用於自一半導體晶圓切割之一半導體裝置之橋結構,該半導體晶圓包括複數個橋結構,該複數個橋結構之邊界係界定於該半導體晶圓內,該橋結構包括:一第一表面;一或多個積體電路,其形成於該第一表面中,使得該橋結構係一功能性半導體晶粒;一第二表面,其相對於該第一表面;及一溝渠,其形成於該第二表面中,該溝渠以晶圓層級形成於跨半導體晶圓之列或行之連續線中;其中形成該橋結構之一材料係來自由一單晶半導體元素或化合物及一多晶半導體元素或化合物組成之一群組。
- 如請求項1之橋結構,其中形成該橋結構之該材料係來自由以下各者組成之該群組的一材料:IV族元素半導體、IV族化合物半導體、VI族元素半導體、III-V族半導體、II-VI族半導體、I-VII族半導體、IV-VI族半導體、V-VI族半導體及II-V族半導體。
- 如請求項1之橋結構,其中該橋結構係來自一半導體晶圓之一半導體晶粒。
- 如請求項1之橋結構,其中該橋結構在該第一表面中包含積體電路。
- 如請求項4之橋結構,其中該等積體電路用作快閃記憶體。
- 如請求項1之橋結構,其中該橋結構不包含積體電路。
- 如請求項1之橋結構,其進一步包括彼此相對且各延伸於該第一表面與該第二表面之間之第一邊緣及第二邊緣,該第二表面中之該溝渠自該第一邊緣延伸至該第二邊緣。
- 一種半導體裝置,其包括:一基板;一第一半導體晶粒,其直接安裝至該基板之一表面;一橋結構,其直接安裝至該基板之該表面之該第一半導體晶粒上方,該橋結構在面向該基板之該橋結構之一第一表面中包含一溝渠,該溝渠在該橋結構之相對邊緣之間延伸,該第一半導體晶粒裝配於該橋結構中之該溝渠內,該橋結構包括來自一經處理晶圓的一間隔層,該經處理晶圓具有跨該橋結構及軸向鄰近該橋結構之額外橋結構之一長度而連續地被鋸開之該溝渠,且該晶圓具有一第一厚度及位於該橋結構之一第二表面中之多個積體電路,該第二表面相對於該第一表面,該第二表面中之該等積體電路對準該第一表面中之該溝渠;及一群組之一或多個第二半導體晶粒,其來自具有小於該第一厚度之一第二厚度之一半導體晶圓。
- 如請求項8之半導體裝置,其中形成該橋結構之該材料係來自由一單晶半導體元素或化合物及一多晶半導體元素或化合物組成之該群組的一材料。
- 如請求項8之半導體裝置,其中形成該橋結構之該材料係來自由以下各者組成之該群組的一材料:IV族元素半導體、IV族化合物半導體、VI族元素半導體、III-V族半導體、II-VI族半導體、I-VII族半導體、IV-VI族半導體、V-VI族半導體及II-V族半導體。
- 如請求項8之半導體裝置,其中該橋結構係來自一半導體晶圓之一半導體晶粒。
- 如請求項8之半導體裝置,其中該等積體電路用作快閃記憶體。
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