CN110140432A - 印刷电路板和用于制造印刷电路板的方法 - Google Patents

印刷电路板和用于制造印刷电路板的方法 Download PDF

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Publication number
CN110140432A
CN110140432A CN201780079100.XA CN201780079100A CN110140432A CN 110140432 A CN110140432 A CN 110140432A CN 201780079100 A CN201780079100 A CN 201780079100A CN 110140432 A CN110140432 A CN 110140432A
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printed circuit
circuit board
chamber
power chip
dielectric fluid
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CN110140432B (zh
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N·德格雷纳
S·莫洛夫
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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Abstract

本发明涉及一种嵌入有功率芯片的印刷电路板，其中，功率芯片与印刷电路板之间的互连由微米/纳米线构成，印刷电路板包括设置功率芯片的腔，并且其中，该腔进一步填充有电介质流体。

Description

印刷电路板和用于制造印刷电路板的方法
技术领域
本发明总体涉及嵌入有功率芯片的印刷电路板和用于制造嵌入有功率芯片的印刷电路板的方法。
背景技术
功率芯片嵌入印刷电路板(PCB)正在进入市场，因为与陶瓷基板上的较常规的功率芯片组件相比，它是低成本、低阻抗、低电磁干扰且高效冷却的技术。然而，仍然存在的问题是功率芯片与印刷电路板的铜焊盘之间的互连的可靠性。
传统上，互连是使用焊接、烧结、直接铜淀积或使用导电粘合剂来执行的。
当组件经受热机械应力时，例如由于热膨胀系数的不匹配和热梯度，会损坏互连而最终导致功率模块的故障。
为了克服上述问题，提出了由微米/纳米铜线构成的软互连。纳米线与其直径相比具有大的长度，并且是足够柔性的以在低应变和低应力下形变。它们具有较高的密度，形成纳米线森林，以有效传递电流和热。
由此，由于芯片与印刷电路板之间的热效应而引起的机械位移在不对其造成损坏的情况下被纳米线吸收。
发明内容
技术问题
然而，纳米线可能在热、电流和压力的混合作用下，受到粘结/集聚/氧化。
这种集聚导致纳米线森林变硬/熔化，然后互连失去其柔性。
本发明的目的是允许功率芯片与印刷电路板之间的热阻减小，热电容增大，防止纳米线氧化并防止纳米线由于热和电流的共同作用而集聚在一起。
问题的解决方案
为此，本发明关于一种印刷电路板，该印刷电路板嵌入有功率芯片，其中，功率芯片与印刷电路板之间的互连由微米/纳米线构成，印刷电路板包括设置所述功率芯片的腔，其特征在于所述腔还填充有电介质流体。
为此，本发明还关于一种用于制造印刷电路板的方法，该印刷电路板嵌入有功率芯片，其中，功率芯片与印刷电路板之间的互连由微米/纳米线构成，所述印刷电路板包括设置所述功率芯片的腔，其特征在于所述方法包括用电介质流体填充所述腔的步骤。
由此，保护微米/纳米线不受粘结、集聚、氧化的影响，并且加强了在MOSFET的情况下，诸如栅漏、源漏或栅源的不同电位之间的隔离。
根据特定特征，所述电介质流体是隔离性硅凝胶或油脂或电介质油。
由此，系统可以使用低成本且可靠的电介质流体。
根据特定特征，所述电介质流体在腔填充期间具有低粘性，以允许所述流体适当地填充在所述腔的容积并且填充在所述纳米线之间。
由此，腔的整个剩余容积用电介质流体填充，并且更好地保护微米/纳米线不受粘结、集聚、氧化的影响，并且加强了在MOSFET的情况下，诸如栅漏、源漏或栅源的不同电位之间的隔离。
根据特定特征，所述电介质流体是两相材料。
由此，跃迁能用于在冲击电流期间使温度稳定，由此提高了器件的鲁棒性。
根据特定特征，所述印刷电路板还包括至少一个其他腔，用于使所述电介质流体能够收缩进入和离开所述至少一个其他腔。
由此，可以减小第一腔内的压力变化。
根据特定特征，所述印刷电路板还包括孔，该孔使得所述电介质流体填充在所述腔内，并且在所述腔内填充所述电介质流体之后，该孔用树脂填满。
由此，在组装嵌入有功率芯片的印刷电路板之后，实现腔的填充，并且可以使用较标准的工艺。
根据特定特征，所述印刷电路板还包括柔性膜，在流体伴随着该流体的温度和/或相变而膨胀或收缩时，柔性膜形变。
由此，可以减小第一腔的压力变化。
根据特定特征，所述印刷电路板还包括孔，该孔使得所述电介质流体填充在所述腔内，并且在所述腔内填充所述电介质流体之后，所述孔由柔性膜封闭。
由此，膜还充当孔，并且简化了制造工艺。
本发明的特性将通过阅读以下示例性实施方式的描述而更加清楚地呈现，所述描述参照附图来进行。
附图说明
[图1a]图1a表示根据本发明的制造旨在嵌入功率芯片的印刷电路板的第一部分的第一步骤。
[图1b]图1b表示根据本发明的制造旨在嵌入功率芯片的印刷电路板的第二部分的第一步骤。
[图2]图2表示根据本发明的制造旨在嵌入功率芯片的印刷电路板的第二部分的第二步骤。
[图3]图3表示根据本发明的制造旨在嵌入功率芯片的印刷电路板的第二部分的第三步骤。
[图4]图4表示根据本发明的嵌入有功率芯片的印刷电路板。
[图5]图5表示根据本发明的嵌入有功率芯片的印刷电路板的第一形变例的示例。
[图6]图6表示根据本发明的嵌入有功率芯片的印刷电路板的第二形变例的示例。
[图7]图7表示根据本发明的嵌入有功率芯片的印刷电路板的第三形变例的示例。
[图8]图8表示根据本发明的嵌入有功率芯片的印刷电路板的制造方法的示例。
[图9]图9表示根据本发明的嵌入有功率芯片的印刷电路板的第四形变例的示例。
具体实施方式
图1表示根据本发明的制造旨在嵌入功率芯片的印刷电路板的第一部分的第一步骤。
根据本发明的旨在嵌入功率芯片的印刷电路板的第一部分由印刷电路板Pcba构成，印刷电路板Pcba由FR4材料和铜层Cua构成。
纳米线Nwa设置在铜层Cua的部分上。在图1a的示例中，纳米线建立在印刷电路板的第一部分的铜焊盘上。
另选地，纳米线建立在功率芯片本身上。例如，通过将多孔氧化铝层附接/生长到铜表面，铜电镀以及选择性蚀刻该层而形成纳米线。
所形成的纳米线通常是具有10μm的数量级的长度和100nm的数量级的直径的线。长度与直径之间的比例通常高于10。纳米线的数量足够多，例如，每平方厘米至少一百万个，并且纳米线可以覆盖已处理表面的超过50％，以提供高密度截面。处理纳米线，以获得一致高度，由此促进与功率芯片的表面的同质接触。这可以例如，通过多孔层蚀刻前的研磨步骤来进行。
为了防止因热和电流的共同作用而引起的线的粘结，可以添加表面涂布的步骤。
例如，经由诸如化学气相沉积、电解沉积无电镀、或上述技术的组合的淀积技术，在纳米线的外表面上可以淀积非粘合材料的涂布层。
图1b表示根据本发明的制造旨在嵌入功率芯片的印刷电路板的第二部分的第一步骤。
根据本发明的旨在嵌入功率芯片的印刷电路板的第二部分由印刷电路板Pcbb1至Pcbb3构成，印刷电路板Pcbb1至Pcbb3由FR4材料构成，并且印刷电路板Pcbb3进一步由铜层Cub构成。
纳米线Nwb设置在铜层Cub的部分上。在图1b的示例中，纳米线建立在印刷电路板的第二部分的铜焊盘上。
另选地，纳米线建立在功率芯片本身上。例如，通过将多孔氧化铝层附接/生长到铜表面，铜电镀以及选择性蚀刻层而形成纳米线。
所形成的纳米线通常是具有10μm的数量级的长度和100nm的数量级的直径的线。长度与直径之间的比例通常高于10。纳米线的数量足够多，例如，每平方厘米至少一百万个，并且纳米线可以覆盖已处理表面的超过50％，以提供高密度截面。处理纳米线，以获得一致高度，由此促进与功率芯片的表面的同质接触。这可以例如，通过多孔层蚀刻之前的研磨步骤进行。
为了防止因热和电流的共同作用而引起的线的粘结，可以添加表面涂布的步骤。
例如，经由诸如化学气相沉积、电解沉积无电镀、或上述技术的组合的淀积技术，在纳米线的外表面上可以淀积非粘合材料的涂布层。
印刷电路板Pcbb1包括填充件Sp1，其旨在将功率芯片设置在正确位置。
印刷电路板Pcbb2包括填充件Sp2，其旨在将功率芯片设置在正确位置。
图2表示根据本发明的制造旨在嵌入功率芯片的印刷电路板的第二部分的第二步骤。
在制造了印刷电路板的第二部分时，将功率芯片Di设置在由印刷电路板Pcbb1至Pcbb3形成的腔中。功率芯片Di的位置由填充件Sp1和Sp2确定。
设置在铜层Cub上的纳米线与功率芯片Di的漏极Dr接触。
为了得到高电导性和高热导性并且防止纳米线在组装期间变平，可以活性化漏极Dr表面，例如通过添加诸如焊膏的薄层，其可以促进接触并导致纳米线与漏极Dr表面之间的牢固连接。使用具有例如刮痕或纳米腔的小图案的多孔表面，或生成微米范围短铜纳米线可以促进纳米线与漏极Dr的表面之间的连接。
图3表示根据本发明的制造旨在嵌入功率芯片的印刷电路板的第二部分的第三步骤。
在第三步骤中，用电介质流体填充由印刷电路板Pcbb1至Pcbb3形成的腔，以减小芯片与壳体之间的热阻，由此促进热从功率芯片Di流走，增大热电容，由此限制了冲击电流或短路的情况下的温度增大，防止了纳米线的氧化，防止了因热和电流的共同作用而引起的线的集聚，并且提供在MOSFET功率芯片Di的情况下诸如栅漏、源漏或栅源的不同电位之间的隔离。
电介质流体可以是具有各种级别的粘性的液体，例如隔离性硅凝胶/油脂、电介质油。电介质流体在腔填充期间具有低粘性，以允许流体适当地填充在腔的容积，尤其是填充在纳米线之间。在腔填充之后，粘性会增大，例如，以提供类凝胶粘性。流体还可以是两相材料，例如石蜡或其他类蜡物质，其熔点选择要么充分低，例如42℃，使得其在正常操作期间是液体，要么较高，例如200℃，使得电介质流体仅在如冲击电流或短路的非正常操作期间熔化。由此，跃迁能用于在冲击电流期间使温度稳定，由此提高功率芯片Di的鲁棒性。
腔可以如之前描述在组装过程期间填充，但另选地，腔可以在组装之后填充，如下文将公开的。
在密封之前可以使用机械搅动的附加步骤，例如使用超声波浴进行，以改善纳米线森林中的可用空间内的流体浸透。
图4表示根据本发明的嵌入有功率芯片的印刷电路板。
印刷电路板通过组装印刷电路板的第一部分和第二部分形成，以形成紧压包装型连接，即，功率芯片Di夹在两个铜表面之间而仅有压力效果。首先，在层压工艺期间施加压力，但是在组装过程之后，存在将功率芯片固定的残留压力。
在图4中描述了工艺的一个示例，其中，纳米线建立在具有热过孔的印刷电路板芯上。先前压延过的预浸层层压到先前创建了纳米线的芯。
图5表示根据本发明的嵌入有功率芯片的印刷电路板的第一形变例的示例。
在图5的示例中，印刷电路板的第一部分包括表示为Ho1和Ho2的两个孔，其使得能够在组装印刷电路板的第一部分和第二部分之后，用电介质流体填充由印刷电路板Pcbb1至Pcbb3形成的腔。
在用电介质流体填充了由印刷电路板Pcbb1至Pcbb3形成的腔时，用图5未示出的树脂填充孔Ho1和Ho2。
图6表示根据本发明的嵌入有功率芯片的印刷电路板的第二形变例的示例。
在图6的示例中，印刷电路板的第一部分包括由Me1和Me2表示的两个膜。膜充当膨胀阀。膜Me1和Me2例如是柔性膜，使得其可以在电介质流体由于温度和/或相位变化而膨胀或收缩时形变。
图7表示根据本发明的嵌入有功率芯片的印刷电路板的第三形变例的示例。在图7的示例中，印刷电路板Pcbb1和Pcbb2包括腔Ca1和Ca2，其可以用于允许电介质流体膨胀到腔Ca1和Ca2中以及收缩到腔外Ca1和Ca2。
图8表示根据本发明的嵌入有功率芯片的印刷电路板的制造方法的示例。
在步骤S80，纳米线建立在印刷电路板的第一部分的铜层Cua的部分上和印刷电路板的第二部分的铜层Cub上。
另选地，纳米线建立在功率芯片本身上。例如，纳米线通过将多孔氧化铝层附接/生长到铜表面、铜电镀以及选择性蚀刻层而形成。
所形成的纳米线通常是具有10μm的数量级的长度和100nm的数量级的直径的线。长度与直径之间的比例通常超过10。纳米线的数量足够多，例如，每平方厘米至少一百万个，并且纳米线可以覆盖已处理表面的超过50％，以提供高密度截面。处理纳米线，以获得一致高度，由此促进与功率芯片的表面的同质接触。这可以例如，通过多孔层蚀刻之前的研磨步骤进行。
为了防止因热和电流的共同作用而引起的线的粘结，可以添加表面涂布的步骤。
例如，经由诸如化学气相沉积、电解沉积无电镀、或上述技术的组合的沉积技术，可以在纳米线的外表面上淀积非粘合材料的涂布层。
在步骤81，将功率芯片Di设置在由印刷电路板的第二部分的印刷电路板Pcbb1至Pcbb3形成的腔中。功率芯片Di的位置由填充件Sp1和Sp2确定。
设置在铜层Cub上的纳米线与功率芯片Di的漏极Dr接触。
为了得到高电导性和高热导性并且防止纳米线在组装期间变平，例如通过添加诸如焊膏的薄层，其可以活性化漏极Dr表面，该薄层可以促进接触并导致纳米线与漏极Dr表面之间的牢固连接。使用具有例如刮痕或纳米腔的小图案的多孔表面、或生成微米范围短铜纳米线可以促进纳米线与漏极Dr的表面之间的连接。
在步骤S82中，由印刷电路板Pcbb1至Pcbb3形成的腔填充有电介质流体，以减小芯片与壳体之间的热阻，由此促进热从功率芯片Di流走，增大了热电容，由此限制了冲击电流或短路的情况下的温度增大，防止了纳米线的氧化，防止了因热和电流的共同作用而引起的线的集聚，并且提供MOSFET功率芯片Di的情况下诸如栅漏、源漏或栅源的不同电位之间的隔离。
电介质流体可以是具有各种级别的粘性的液体，例如隔离性硅凝胶/油脂、电介质油。电介质流体在腔填充期间具有低粘性，以允许流体适当地填充在腔的容积尤其是填充在纳米线之间。在腔填充之后，粘性可能增大，例如，以提供类凝胶粘性。流体还可以是两相材料，例如石蜡或其他类蜡物质，其熔点选择要么充分低，例如，42℃，使得其在正常操作期间是液体，要么较高，例如200℃，使得电介质流体仅在如冲击电流或短路的非正常操作期间熔化。由此，跃迁能用于在冲击电流期间使温度稳定，由此提高功率芯片Di的鲁棒性。
腔可以如之前描述在组装过程期间填充，但另选地，腔可以如之后将公开的，在组装之后填充。
在密封之前可以使用机械搅动的附加步骤，例如使用超声波浴进行，以改善纳米线森林中的可用空间内的流体浸透。
印刷电路板通过组装印刷电路板的第一部分和第二部分而形成，以形成紧压包装型连接，即，功率芯片Di夹在两个铜表面之间而仅有压力效果。首先，在层压工艺期间施加压力，但是在组装过程之后，存在将功率芯片固定的残留压力。
这里应当注意的是，如参照图5或6或7所公开的，步骤S83可以在步骤S82之前执行。
图9表示根据本发明的嵌入有功率芯片的印刷电路板的第四形变例的示例。
在第四形变例中，印刷电路板Pcbb1和Pcbb2分别包括柔性膜FM1和FM2，其在流体伴随着流体的温度和/或相变而膨胀或收缩时形变。
膜Me1和Me2例如是柔性膜，使得它们可以在电介质流体由于温度和/或相位变化而膨胀或收缩时形变。膜通常由诸如聚酰亚胺这样的柔性但非渗透性的材料构成，其局部地层压在印刷电路板组件中。
这里应当注意的是，柔性膜还可以位于印刷电路板Pcba和Pcbb3中。
自然地，在不偏离本发明的范围的情况下，可以对本发明的上述实施方式进行许多修改。

Claims (9)

1.一种印刷电路板，该印刷电路板嵌入有功率芯片，其中，该功率芯片与该印刷电路板之间的互连由微米/纳米线构成，所述印刷电路板包括设置所述功率芯片的腔，其特征在于所述腔还填充有电介质流体。
2.根据权利要求1所述的印刷电路板，其特征在于，所述电介质流体是隔离性硅凝胶或油脂或电介质油。
3.根据权利要求2所述的印刷电路板，其特征在于，所述电介质流体在腔填充期间具有低粘性，以允许所述流体适当地填充在所述腔的容积中并填充在所述纳米线之间。
4.根据权利要求1所述的印刷电路板，其特征在于，所述电介质流体是两相材料。
5.根据权利要求1至4中任一项所述的印刷电路板，其特征在于，所述印刷电路板还包括至少一个其他腔，使得所述电介质流体能够收缩进入和离开所述至少一个其他腔。
6.根据权利要求1至5中任一项所述的印刷电路板，其特征在于，所述印刷电路板还包括孔，所述孔使得能够将所述电介质流体填充在所述腔内，并且在所述腔内填充所述电介质流体之后，所述孔被用树脂填满。
7.根据权利要求1至5中任一项所述的印刷电路板，其特征在于，所述印刷电路板还包括柔性膜，在所述流体伴随着所述流体的温度和/或相变而膨胀或收缩时该柔性膜形变。
8.根据权利要求1至5中任一项所述的印刷电路板，其特征在于，所述印刷电路板还包括孔，其使得能够将所述电介质流体填充在所述腔内，并且在所述腔内填充所述电介质流体之后，所述孔由柔性膜封闭。
9.一种用于制造印刷电路板的方法，该印刷电路板嵌入有功率芯片，其中，所述功率芯片与所述印刷电路板之间的互连由微米/纳米线构成，所述印刷电路板包括设置所述功率芯片的腔，其特征在于所述方法包括用电介质流体填充所述腔的步骤。
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