CN104769714A - 包括交替形成台阶的半导体裸芯堆叠的半导体器件 - Google Patents

包括交替形成台阶的半导体裸芯堆叠的半导体器件 Download PDF

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Publication number
CN104769714A
CN104769714A CN201380052412.3A CN201380052412A CN104769714A CN 104769714 A CN104769714 A CN 104769714A CN 201380052412 A CN201380052412 A CN 201380052412A CN 104769714 A CN104769714 A CN 104769714A
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naked core
bare chip
stacking
nitride layer
semiconductor bare
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CN201380052412.3A
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CN104769714B (zh
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S.库马尔
邱进添
黄大成
吕忠
Z.纪
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SanDisk Information Technology Shanghai Co Ltd
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SanDisk Information Technology Shanghai Co Ltd
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Abstract

一种半导体器件，包括交替形成台阶的半导体裸芯堆叠以允许使用短引线键合体在半导体器件内提供大量半导体裸芯。

Description

包括交替形成台阶的半导体裸芯堆叠的半导体器件
背景技术
便携式消费电子产品的强劲增长需要促进了对高容量存储装置的需求。诸如闪存存储卡的非易失性半导体存储器装置正变得越来越广泛用于满足对数字信息存储和交换的日益增长的需要。它们的便携性、多用些和稳定的设计、以及其高可靠性和大容量已经使得这种存储器器件理想地用于各种电子设备，包括例如，数码相机、数字音乐播放器、视频游戏机、PDA和蜂窝电话。
虽然已知了多种封装体配置，但是通常闪存存储卡可以制造为系统级封装体(SiP)或多芯片模块(MCM)，其中，在小足印基板上安装和互连多个裸芯。该基板通常可以包括刚性的介电基底，其具有在一面或两面上蚀刻的导电层。在裸芯和(一个或多个)导电层之间构成电连接，且(一个或多个)导电层提供用于将裸芯连接到主机设备的电引线结构。一旦完成了在裸芯和基板之间的电连接，则通常将该装配件包裹在提供保护性包装的模塑化合物内。
图1和图2中示出了传统半导体封装体20的剖面侧视图和俯视图(在图2中没有示出模塑化合物)。典型的封装体包括附着到基板26的多个半导体裸芯，诸如闪存裸芯22和控制器裸芯24。在裸芯制造工艺期间，可以在半导体裸芯22、24上形成多个裸芯键合垫。类似地，可以在基板26上形成多个接触垫30。裸芯22可以被附着在基板26上，然后裸芯24可以被安装在裸芯22上。然后，可以通过在相应的裸芯键合垫28和接触垫30对之间附着引线键合体32来将所有裸芯电耦合到基板。一旦完成了所有电连接，则可以在模塑化合物34中包封这些裸芯和引线键合体，以密封该封装体并保护这些裸芯和引线键合体。
为了最高效地利用封装体足印，已知上下堆叠半导体裸芯，无论是完全彼此重叠还是带有偏移地重叠，如图1和2所示。在偏移配置中，一个裸芯被堆叠在另一裸芯的顶上使得下方裸芯的键合垫被暴露。偏移配置提供方便地接近在堆叠中的每个半导体裸芯上的键合垫的优点。
随着半导体裸芯变得更薄，且为了增加半导体封装体的存储器容量，在半导体封装体内堆叠的裸芯的数量继续增加。但是，这可能导致从上部裸芯下降到基板的长键合引线。长键合引线容易被损坏或与其他引线键合体短路，且还具有比较短的键合引线更高的信噪比。
附图说明
图1是传统半导体封装体的剖面侧视图。
图2是传统基板和引线键合的半导体裸芯的俯视图。
图3是根据本发明的实施例的半导体器件的整体制造工艺的流程图。
图4是根据本技术的一个实施例的在制造工艺中的第一步骤中的半导体器件的侧视图。
图5是根据本技术的一个实施例的在制造工艺中的第二步骤中的半导体器件的俯视图。
图6是根据本技术的一个实施例的在制造工艺中的第三步骤中的半导体器件的侧视图。
图7是根据本技术的一个实施例的在制造工艺中的第四步骤中的半导体器件的侧视图。
图8是根据本技术的一个实施例的在制造工艺中的第五步骤中的半导体器件的侧视图。
图9是根据本技术的一个实施例的在制造工艺中的第五步骤中的半导体器件的简化透视图。
图10是根据本技术的一个实施例的在制造工艺中的第六步骤中的半导体器件的侧视图。
图10A-10C是用于完成图9所示的制造工艺中的第六步骤的根据各个实施例的侧视图。
图11是根据本技术的一个实施例的在制造工艺中的第七步骤中的半导体器件的侧视图。
图12是根据本技术的一个实施例的在制造工艺中的第八步骤中的半导体器件的侧视图。
具体实施方式
现在将参考图3到12来描述本技术，本技术在各实施例中涉及一种半导体器件，包括交替形成台阶的半导体裸芯堆叠以允许使用短引线键合体在半导体器件内提供大量半导体裸芯。要理解，本发明可以按许多不同的形式来实施，且不应该被限制为在此阐述的实施例。而是，提供这些实施例以便本公开充分和完整，且充分地向本领域技术人员传达该发明。确实，本发明旨在覆盖这些实施例的替换、修改和等同物，这些都被包括在由所附权利要求所限定的本发明的范围和精神中。另外，在本发明的以下详细描述中，阐述大量具体细节以便提供对本发明的全面了解。但是，本领域技术人员将清楚，可以不用这种具体细节来实践本发明。
在此可能使用的术语“顶部”和“底部”、“上方”和“下方”和“垂直”和“水平”仅用于举例和图示目的，且不意图限制本发明的描述，所引用的项目可以在位置和方向上交换。而且，如在此使用的，术语“基本上”、“近似”和/或“大约”意味着所指定的尺度或参数可以对于给定的应用在可接受的制造容许量内变换。在一个实施例中，该可接受制造容许量为±0.25％。
将参考图3的流程图和图4到12的俯视和侧视图来说明本发明的实施例。虽然图4到12每个示出了单个器件100、或其一部分，但是要理解，该器件100可以与基板面板上的多个其他封装体100一起被批处理，以实现规模经济。基板面板上的封装体100的行和列的数量可以改变。
基板面板以多个基板102开始(再次，在图4到12中示出一个这样的基板)。基板102可以是各种不同的芯片承载介质，包括印刷电路板(PCB)、引线框架或带自动键合(TAB)带。在基板102是PCB的情况下，基板可以由具有顶部导电层105和底部导电层107的核心103形成，如图4所示。核心103可以由诸如例如聚酰亚胺薄片、包括FR4和FR5的环氧树脂、双马来酰亚胺-三嗪(BT)等的各种介电材料形成。虽然不是本发明所必要的，但是该核心可以具有在40微米(μm)到200μm之间的厚度，虽然在替换实施例中该核心的厚度可以在该范围之外变化。在可选实施例中，该核心103可以是陶瓷或有机的。
围绕核心的导电层105、107可以由铜或铜合金、镀铜或镀铜合金、合金42(42Fe/58Ni)、镀铜钢或已知用于在基板面板上使用的其他金属和材料形成。导电层可以具有大约10μm到25μm的厚度，虽然在可选实施例中这些层的厚度可以在该范围之外变化。
图3是根据本发明的实施例的半导体器件的整体制造工艺的流程图。在步骤200中，基板102被钻孔以在基板102上定义贯通通孔104。所示的各通孔104(在图中仅编号了一些通孔)仅是示例，且基板可以包括比图中示出的多得多的通孔104，且它们可以处于与图中示出的位置不同的位置。接下来在步骤202中，在顶部和底部导电层的一个或两者上形成导电图案。导电图案可以包括电迹线106和接触垫108，如例如图5和6所示。迹线106和接触垫108(在图中仅编号了一些)仅是示例，且基板102可以包括比图中示出的更多迹线和/或接触垫，且它们可以处于与图中示出的位置不同的位置。
在各实施例中，可以使用成品半导体器件100装配件作为BGA(球栅阵列)封装。基板102的下表面可以包括用于接收如下所述的焊球的接触焊垫108。在其他实施例中，成品半导体器件100可以是包括在主机设备内用于可移除地耦合成品器件100的触指的LGA(焊盘栅阵列)封装体。在这种实施例中，下表面可以包括触指，而不是接收焊球的接触垫。基板102的顶部和/或底部表面上的导电图案可以通过各种已知工艺、包括例如各种光刻工艺来形成。
再次参考图3，然后，可以在步骤204中，在自动光学检查(AOI)中检查基板102。一旦检查完，在步骤206中可以将焊接掩膜110施加到基板。在施加了焊接掩膜之后，在步骤208中，在已知电镀或薄膜沉积工艺中，导电图案上的接触垫、触指、和任何其他焊接区域可以被镀上Ni/Au、合金42等。然后，基板102可以在自动检查工艺(步骤210)中且在最终视觉检查(步骤212)中被检查和测试，以查验电操作，且查看污染、划痕和变色。
假设基板102通过了检查，可以接下来在步骤214中将无源组件112附着到基板。一个或多个无源组件可以包括例如一个或多个电容器、电阻器和/或电感器，虽然可构思其他组件。示出的无源组件112(在图中仅编号了一些)仅是示例，且在其他实施例中，数量、类型和位置可以改变。
根据本技术，接下来在步骤220中可以在基板102上形成多个半导体裸芯堆叠。如以下所述，每个裸芯堆叠可以在相反的方向上形成台阶，且在相邻裸芯堆叠之间用插入物层来实现在相邻裸芯堆叠之间的过渡。参考图7，在偏移台阶配置中，可以将多个半导体裸芯124彼此上下堆叠来形成第一裸芯堆叠120。可以使用裸芯粘贴膜来将裸芯附着到基板和/或其他裸芯。作为一个例子，裸芯粘贴粘合剂可以是来自Henkel AG&Co.KGaA的8988UV环氧树脂，被固化为B阶段以初步地将裸芯124附着在堆叠120中，且随后被固化到最终C阶段以永久地将裸芯124附着在堆叠120中。
例如，半导体裸芯124可以是诸如NAND闪存裸芯的存储器，但是可以使用其他类型的裸芯124。图7示出在堆叠120中安装八个裸芯124的实施例。但是，在其他实施例中，可以在堆叠120中有多于八个或少于八个的裸芯124。
在形成了裸芯堆叠120之后，可以将插入物层128附着到堆叠120中的上裸芯124，如图7所示。插入物层128可以以与堆叠120中的其他裸芯124相同的方式和相同的程度偏移。插入物层128可以是刚性层，由例如FR4和FR5形成，或可以是柔性层，由例如聚酰亚胺带形成。在插入物层的上表面上形成导电图案。如以下所述，提供导电图案和插入物层的目的在于将信号从插入物层128的一侧上的接触垫传送到插入物层的相反侧上的相应接触垫。
现在参考图8的侧视图，一旦形成了裸芯堆叠120，可以使用引线键合体130将堆叠120中的各个裸芯124电连接到基板，将该堆叠中的每个裸芯电连接到基板102。图9是示出基板102和裸芯堆叠120中的仅底部的两个裸芯124的简化透视图。如所示，每个半导体裸芯124可以包括沿裸芯124的一边缘的一行裸芯键合垫132。要理解，每个裸芯124可以包括比图9所示的多得多的裸芯键合垫132。可以使用引线键合体130将在半导体裸芯的该行中的每个裸芯键合垫132电连接到下一相邻的半导体裸芯的该行中的相应裸芯键合垫134。可以使用引线键合体130将底部半导体裸芯124的每个裸芯键合垫132电连接到基板102上的接触垫的该行中的相应接触垫108。
虽然可以通过各种技术形成引线键合体130，但是在一个实施例中，可以将引线键合体130形成为反向球键合体。这些可以通过使用已知构造的引线键合劈刀(未示出)来首先将球键合体134沉积在裸芯(例如底部裸芯124)的裸芯键合垫上来实现。可以通过将一定长度的引线(通常是金或银合金)输送通过引线键合劈刀的中央腔体来形成球键合体134(在图9中编号了该球键合体中的一个)。该引线通过劈刀的末端而伸出，在此，从与劈刀末端相关联的换能器向该引线施加高电压电荷。电荷融化该末端处的引线，且该引线由于融化金属的表面张力而形成球134。然后，在换能器施加超声波能量的同时，可以在负载力下将该球134附着到裸芯键合垫132。
然后，该引线键合劈刀可以输出一小长度的引线，且该引线可以在导电球处被切断以在裸芯键合垫132上留下该球键合体134。然后，可以使用从劈刀的尾端悬挂的引线的小尾巴以为该行中的接下来的下一裸芯键合垫132形成球键合体134。球键合体134可以通过各种其他方法在半导体裸芯124的键合垫形成，所述方法包括例如在晶片级柱凸块(stud bumping)或金凸块(gold bumping)。
然后，在接下来的更低级上(例如在基板102上)形成另一球键合体，如上所述。但是，不切断引线，将引线输出并置于与接下来的更高级上的相应球键合体134接触(虽然在其他实施例中可以跳过一个或多个级)。在换能器施加超声波能量的同时，在负载力下将引线施加到球键合体134。组合的热量、压力和超声波能量产生了引线和球键合体134之间的键合体。然后，引线键合劈刀可以输出一小长度的引线，且该引线可以被切断以在不同级上的相应垫之间形成引线键合体130。
可以水平地横跨裸芯和基板上的垫并垂直地在裸芯和基板上的垫之间重复该工艺，直到形成了所有引线键合体130。在不同实施例中，(水平或垂直地)形成引线键合体130的顺序可以改变。另外，虽然通常在从裸芯堆叠120和基板中的一层到接下来的一层的直线垂直列中示出了引线键合体130，但是这些引线键合体中的一个或多个可以对角地从一层延伸到接下来的一层。另外，可能的是，引线键合体跳过裸芯堆叠120中的一个或多个层。
如上所述，插入物层128可以附着在裸芯堆叠120顶上。插入物层128可以包括第一边缘128a，其具有在数量和位置上对应于裸芯堆叠120中在插入物层128下方的裸芯124上的该行裸芯键合垫132的一行接触垫。可以以与上述引线键合体130相同的方式，在插入物层128的边缘128a上的该行接触垫和相邻的下方的裸芯124(在裸芯堆叠120的顶部的裸芯)之间形成引线键合体130。
以此方式引线键合到插入物层128比传统系统具有多种优点。首先，不需要单独的工艺或单独的工具来引线键合到插入物层128。引线键合到插入物层128与引线键合到插入物层下方的裸芯124相同。另外，由于引线键合体被形成在插入物层128的顶部表面上的接触垫上，接触垫可见，且引线键合体可以被形成在可见的接触垫上，且与例如试图键合到可能不可见或不容易触及的插入物层的下表面的设计相比，更容易地被视觉验证。
现在参考图10的侧视图，接下来，第二裸芯堆叠120可以被附着在插入物层128和第一裸芯堆叠120的顶上。注意，第一堆叠120中的最上部裸芯引线键合到插入物层128的上表面上。为了不损坏那些引线键合体，在插入物层128的上表面上提供膜层134。将在插入物层128上的引线键合体130嵌入在膜层134中，且膜层134将第二裸芯堆叠120与插入物层128隔开。膜层134可以例如是从日本的Nitto Denko公司或加利福尼亚州的Henkel公司可买到的已知组分的电绝缘粘合性环氧树脂。
膜层134可以被施加为粘性的液体，其维持在该状态直到在此后描述的回流工艺中固化。在各实施例中，膜层134被施加为液体，但是具有足够高的粘度以机械地支撑第二裸芯堆叠。在各实施例中，粘度可以是例如大约1-2x 106厘泊，但是要理解，在可选实施例中，粘度可以比这更高或更低。在可选实施例中，可以在膜层134内提供隔垫物球。隔垫物球可以是用作第二裸芯堆叠和插入物层之间的隔垫物的聚合物球体。在现有技术中已知这种隔垫物球，其在例如题为“Method of Making a Semiconductor Package IncludingStacked Semiconductor Die”美国专利号6,650,019中公开，该专利被整体引用并于此。膜层134可以具有某种厚度，使得到插入物层128的引线键合体被嵌入在其中，且第二裸芯堆叠120的底部裸芯不与嵌入的引线键合体130接触。
一旦向插入物层128施加了膜层134，则可以将第二裸芯堆叠120附着在第一裸芯堆叠120的顶上，且将其引线键合到基板。具体地，插入物层128包括插入物层的与第一边缘相对的第二边缘上的第二行接触垫。插入物层128上的导电图案将插入物层的第一边缘上的接触垫电连接到插入物层的第二边缘上的相应接触垫。
从插入物层128的第二边缘上的接触垫和第二裸芯堆叠120中的最底部裸芯124形成引线键合体130。以此方式，来自第二裸芯堆叠的最底部裸芯的裸芯键合垫132经由插入物层128中的电迹线而电耦合到第一裸芯堆叠中的最上部裸芯上的其相应裸芯键合垫132。如此，仅使用短(例如单跳)引线键合体130将第二裸芯堆叠中的裸芯124电耦合到基板102。
可以以与第一裸芯堆叠中的裸芯124相同的方式且以相同的程度来使第二裸芯堆叠120中的裸芯124形成台阶，但是在相反的方向上，以最小化第一和第二裸芯堆叠120总体的足印。可以以多种方式来在插入物层128顶上形成第二裸芯堆叠。在图10A所示的一个例子中，可以以与第一裸芯堆叠120相同的方式形成第二裸芯堆叠120。每个裸芯124可以在偏移台阶配置中被添加到器件100。一旦第二裸芯堆叠120中的所有裸芯都被附着在堆叠中，可以如上所述将裸芯124彼此引线键合，并引线键合到基板102。
在图10B所示的第二例子中，可以将裸芯124和第二裸芯堆叠120彼此装配，与器件100分离，且不作为器件100的装配的关键路径的一部分。第二裸芯堆叠120可以被装配且准备好作为单个预装配的堆叠而被附着到插入物层128和膜层134上，如上所述。一旦第二裸芯堆叠120被附着在堆叠中，可以如上所述将第二裸芯堆叠120中的裸芯124彼此引线键合，并引线键合到基板102。
如图10C所示的第三例子可以具有图10B所示的预装配的裸芯堆叠120，但在图10C的例子中，可以将第二裸芯堆叠120中的裸芯124彼此引线键合，与器件100分离，且不作为器件100的装配的关键路径的一部分。在该例子中，在器件100所需的引线键合体仅是将第二裸芯堆叠中的最底部裸芯124的裸芯键合垫连接到插入物层128。
现在参考图11的侧视图，可以以与将第二裸芯堆叠120添加到第一裸芯堆叠相同的方式将另外的裸芯堆叠120添加到器件100。每个裸芯堆叠可以在与其下方的裸芯堆叠相反的方向上形成台阶，以最小化所有裸芯堆叠整体的足印。图11图示了包括总共24个裸芯的三个裸芯堆叠的例子。图12图示了包括总共32个裸芯的四个裸芯堆叠的例子。所图示的器件100仅示例地根据本技术而具有每个包括更多或更少裸芯124的更多或更少裸芯堆叠120。作为一个另外的例子，可以有八个裸芯堆叠120，每个包括八个裸芯124，在器件100中总共64个裸芯。
在将另外的裸芯堆叠120添加到器件100的情况下，下方的裸芯堆叠120可以包括插入物层128和膜层134，且如上所述地形成引线键合体。器件100中的最上部裸芯堆叠120不需要包括插入物层128或膜层134。
在将裸芯堆叠120安装在基板102上之后，可以在步骤224中安装控制器裸芯(未示出)且将其引线键合到基板。在各实施例中，可以将控制器裸芯安装在最上部裸芯堆叠120上。在其他实施例中，可以将控制器裸芯安装在最下部裸芯堆叠120下。例如，可以将控制器裸芯安装在基板102的顶上。这种实施例的一个例子在2013年1月9日为国际申请日的题为“Semiconductor Device Including an Independent Film Layer For Embeddingand/or Spacing Semiconductor Die”专利合作条约专利申请号PCT/CN2013/070264中公开了。作为另一例子，可以将控制器裸芯安装在基板102内。这种实施例的一个例子在2013年1月28日为国际申请日的题为“Semiconductor Device Including an Embedded Controller Die and Method ofMaking Same”专利合作条约专利申请号PCT/CN2013/071051中公开了。这两个国际专利申请都被整体引用并于此。
在安装和电连接裸芯堆叠和控制器裸芯之后，在步骤226中且如图12所示，裸芯堆叠、引线键合体和基板的至少一部分可以被包封在模塑化合物140中。模塑化合物140可以包括例如固态环氧树脂、酚醛树脂、熔融石英、结晶石英、碳黑和/或金属羟化物。这种模塑化合物可从例如在日本都有总部的Sumitomo公司和Nitto-Denko公司得到。可设想来自其他制造商的其他模塑化合物。可以根据各种已知工艺、包括通过转送模塑或注射模塑技术来施加模塑化合物。在其他实施例中，可以通过FFT(薄自由流动(Flow Free Thin))压缩模塑来进行包封工艺。
可以在包封步骤中，将诸如例如裸芯粘贴膜和膜层134的可固化B阶段粘合剂固化为最终的交联的C阶段。在其他实施例中，在单独的加热步骤中，将粘合剂固化为C阶段。
如图12所示，在步骤226中包封了在面板上的裸芯之后，对于器件是BGA封装体的实施例，在步骤228中，可以将焊料球142焊接到各个封装体的下表面上的接触垫108。在封装体是LGA封装体的情况下，可以跳过步骤226。
在步骤230中可以从面板上单片化各个封装体，以形成图12所示的成品半导体器件100。通过各种切割方法的任一种来单片化每个半导体器件100，所述方法包括锯割、水流切割、激光切割、水引导激光切割、干介质切割和金刚石涂覆线切割。虽然直线切割将通常限定矩形或正方形的半导体器件100，但是要理解，在本发明的其他实施例中，半导体器件100可以具有与矩形和正方形不同的形状。
一旦切割为封装体100，可以在步骤232中测试这些封装体，以确定这些封装体是否适当地运作。如在现有技术中已知，这种测试可以包括电测试、写入(burn in)和其他测试。可选地，在步骤234中，在例如半导体器件是LGA封装体的情况下，成品半导体器件可以被包裹在盖帽(未示出)内。
成品半导体封装体100可以例如是存储卡，诸如例如MMC卡、SD卡、多用途卡、微SD卡、存储棒、紧凑SD卡、ID卡、PCMCIA卡、SSD卡、芯片卡、智能卡、USB卡、MCP类嵌入式卡存储器等。
总之，在一个例子中，本技术涉及一种半导体器件，包括：基板：
第一裸芯堆叠，具有安装到所述基板的第一半导体裸芯和在第一裸芯堆叠的与所述第一半导体裸芯相对的端部的第二半导体裸芯，所述第一裸芯堆叠在第一方向上偏移地形成台阶；
插入物层，具有附着到所述第二半导体裸芯的第一表面和与所述第一表面相对的第二表面；
第二裸芯堆叠，具有与插入物层的第二表面相邻地安装的第三半导体裸芯和在第二裸芯堆叠的与所述第三半导体裸芯相对的端部的第四半导体裸芯，其中所述第二裸芯堆叠在与所述第一方向相反的第二方向上偏移地形成台阶；以及在如下之间的引线键合体
i)所述基板上的接触垫和第一半导体裸芯的裸芯键合垫、ii)所述第二半导体裸芯的裸芯键合垫和所述插入物层的第二表面上的接触垫、以及iii)所述插入物层的第二表面上的接触垫和所述第三半导体裸芯。
在另一个例子中，本技术涉及一种半导体器件，包括：
基板：
第一裸芯堆叠，具有安装到所述基板的第一半导体裸芯和在第一裸芯堆叠的与所述第一半导体裸芯相对的端部第二半导体裸芯，所述第一裸芯堆叠在第一方向上偏移地形成台阶；
插入物层，具有第一边缘和第二边缘，其中，第一组接触垫沿着所述第一边缘，第二组接触垫沿着所述第二边缘，且电迹线将来自所述第一组和第二组的相应接触垫连接到一起，所述插入物层还包括第一表面和第二表面，其中，所述第一表面附着到所述第二半导体裸芯；
第二裸芯堆叠，具有与插入物层的第二表面相邻地安装的第三半导体裸芯和在第二裸芯堆叠的末尾处与所述第三半导体裸芯相对的第四半导体裸芯，其中所述第二裸芯堆叠在与所述第一方向相反的第二方向上偏移地台阶；以及
引线键合体，经由包括如下的路径将所述第四半导体裸芯上的裸芯键合垫与所述基板连接：
i)所述第二堆叠中的在所述第三和第四半导体裸芯之间的任何半导体裸芯上的裸芯键合垫、ii)所述第三半导体裸芯上的裸芯键合垫和所述插入物层上的第二组接触垫中的接触垫、iii)所述插入物层上的第一组接触垫中的接触垫和所述第二半导体裸上的裸芯键合垫、iv)所述第一堆叠中的在所述第一和第二半导体裸芯之间的任何半导体裸芯上的裸芯键合垫、以及v)所述第一半导体裸芯上的裸芯键合垫和所述基板上的接触垫.
在另一个例子中，本技术涉及一种形成半导体器件的方法，包括：
(a)形成基板：
(b)以在第一方向上台阶的偏移配置来将第一裸芯堆叠安装到基板，所述第一裸芯堆叠具有与所述基板相邻的第一半导体裸芯和在所述第一裸芯堆叠的与所述第一半导体裸芯相对的端部的第二半导体裸芯；
(c)将插入物层附着到所述第二半导体裸芯，其中所述插入物层具有附着到所述第二半导体裸芯的第一表面和与所述第一表面相对的第二表面；
(d)以在与所述第一方向相反的第二方向上形成台阶的偏移配置与所述插入物层相邻地安装第二裸芯堆叠，所述第二裸芯堆叠具有与所述插入物层的第二表面相邻地安装的第三半导体裸芯和在所述第二裸芯堆叠的与所述第三半导体裸芯相对的端部的第四半导体裸芯；以及
(e)将所述第一裸芯堆叠和所述第二裸芯堆叠引线到所述基板，所述步骤(e)包括以与在所述第二半导体裸芯和所述第一裸芯堆叠中的其他半导体裸芯的裸芯键合垫之间形成引线键合体相同的工艺、从所述第二半导体裸芯的裸芯键合垫向所述插入物层的第二表面上的第一接触垫形成引线键合体的步骤。
已经为了图示和描述的目的呈现了本发明的前述描述。不旨在穷举或限制本发明到公开的精确形式。在上述教导下，许多修改和变化是可能的。选择上述实施例以便最佳地说明本发明的原理及其实际应用，由此使得本领域技术人员能够最佳地在各种实施例中使用本发明，且设想适用于实际使用的各种修改。本发明的范围旨在由所附的权利要求来限定。

Claims (20)

1.一种半导体器件，包括：
基板：
第一裸芯堆叠，具有安装到所述基板的第一半导体裸芯和在第一裸芯堆叠的与所述第一半导体裸芯相对的端部的第二半导体裸芯，所述第一裸芯堆叠在第一方向上偏移地形成台阶；
插入物层，具有附着到所述第二半导体裸芯的第一表面和与所述第一表面相对的第二表面；
第二裸芯堆叠，具有与插入物层的第二表面相邻地安装的第三半导体裸芯和在第二裸芯堆叠的与所述第三半导体裸芯相对的端部的第四半导体裸芯，其中所述第二裸芯堆叠在与所述第一方向相反的第二方向上偏移地形成台阶；以及
在如下之间的引线键合体：i)所述基板上的接触垫和第一半导体裸芯的裸芯键合垫、ii)所述第二半导体裸芯的裸芯键合垫和所述插入物层的第二表面上的接触垫、以及iii)所述插入物层的第二表面上的接触垫和所述第三半导体裸芯。
2.根据权利要求1所述的半导体器件，其中，所述插入物层包括由所述第一表面和所述第二表面分开的第一边缘和第二边缘，所述第二半导体裸芯的裸芯键合垫和所述插入物层的第二表面上的接触垫沿着所述插入物层的第一边缘。
3.根据权利要求2所述的半导体器件，其中，所述插入物层的第二表面上的接触垫和所述第三半导体裸芯之间的引线键合体沿着所述插入物层的第二边缘。
4.根据权利要求1所述的半导体器件，其中，所述第一裸芯堆叠和第二裸芯堆叠包括闪存裸芯。
5.根据权利要求1所述的半导体器件，其中，所述第一裸芯堆叠和第二裸芯堆叠每个包括四到八个存储器裸芯。
6.根据权利要求1所述的半导体器件，还包括在所述插入物层的第二表面上的、在所述插入物层和所述第二裸芯堆叠之间的膜层。
7.根据权利要求1所述的半导体器件，还包括包封第一和第二裸芯堆叠和引线键合体的模塑化合物。
8.根据权利要求1所述的半导体器件，其中，所述插入物层包括第一插入物层，所述半导体器件还包括：
第二插入物层，具有附着到所述第四半导体裸芯的第一表面和与所述第一表面相对的第二表面；以及
第三裸芯堆叠，具有与所述第二插入物层的第二表面相邻地安装的第五半导体裸芯。
9.根据权利要求1所述的半导体器件，其中，所述第三裸芯堆叠在所述第一裸芯堆叠上方垂直地对齐。
10.一种半导体器件，包括：
基板：
第一裸芯堆叠，具有安装到所述基板的第一半导体裸芯和在第一裸芯堆叠的与所述第一半导体裸芯相对的端部的第二半导体裸芯，所述第一裸芯堆叠在第一方向上偏移地台阶；
插入物层，具有第一边缘和第二边缘，其中，第一组接触垫沿着所述第一边缘，第二组接触垫沿着所述第二边缘，且电迹线将来自所述第一组和第二组的相应接触垫连接到一起，所述插入物层还包括第一表面和第二表面，其中，所述第一表面附着到所述第二半导体裸芯；
第二裸芯堆叠，具有与插入物层的第二表面相邻地安装的第三半导体裸芯和在第二裸芯堆叠的与所述第三半导体裸芯相对的端部的第四半导体裸芯，其中所述第二裸芯堆叠在与所述第一方向相反的第二方向上偏移地形成台阶；以及
引线键合体，经由包括如下的路径将所述第四半导体裸芯上的裸芯键合垫与所述基板连接：i)所述第二堆叠中的在所述第三和第四半导体裸芯之间的任何半导体裸芯上的裸芯键合垫、ii)所述第三半导体裸芯上的裸芯键合垫和所述插入物层上的第二组接触垫中的接触垫、iii)所述插入物层上的第一组接触垫中的接触垫和所述第二半导体裸上的裸芯键合垫、iv)所述第一堆叠中的在所述第一和第二半导体裸芯之间的任何半导体裸芯上的裸芯键合垫、以及v)所述第一半导体裸芯上的裸芯键合垫和所述基板上的接触垫。
11.根据权利要求10所述的半导体器件，其中，所述第一裸芯堆叠和第二裸芯堆叠包括闪存裸芯。
12.根据权利要求10所述的半导体器件，其中，所述第一裸芯堆叠和第二裸芯堆叠每个包括四到八个存储器裸芯。
13.根据权利要求10所述的半导体器件，还包括在所述插入物层的第二表面上的、在所述插入物层和所述第二裸芯堆叠之间的膜层。
14.根据权利要求10所述的半导体器件，还包括包封第一和第二裸芯堆叠和引线键合体的模塑化合物。
15.根据权利要求10所述的半导体器件，其中，所述插入物层包括第一插入物层，所述半导体器件还包括：
第二插入物层，具有附着到所述第四半导体裸芯的第一表面和与所述第一表面相对的第二表面；以及
第三裸芯堆叠，具有与所述第二插入物层的第二表面相邻地安装的第五半导体裸芯，其中，所述第三裸芯堆叠在所述第一裸芯堆叠上方垂直地对齐。
16.一种形成半导体器件的方法，包括：
(a)形成基板：
(b)以在第一方向上形成台阶的偏移配置来将第一裸芯堆叠安装到基板，所述第一裸芯堆叠具有与所述基板相邻的第一半导体裸芯和在所述第一裸芯堆叠与所述第一半导体裸芯相对的端部的第二半导体裸芯；
(c)将插入物层附着到所述第二半导体裸芯，其中所述插入物层具有附着到所述第二半导体裸芯的第一表面和与所述第一表面相对的第二表面；
(d)以在与所述第一方向相反的第二方向上形成台阶的偏移配置与所述插入物层相邻地安装第二裸芯堆叠，所述第二裸芯堆叠具有与所述插入物层的第二表面相邻地安装的第三半导体裸芯和在所述第二裸芯堆叠的与所述第三半导体裸芯相对的端部的第四半导体裸芯；以及
(e)将所述第一裸芯堆叠和所述第二裸芯堆叠引线到所述基板，所述步骤(e)包括以与在第二半导体裸芯和所述所述第一裸芯堆叠中的其他半导体裸芯的裸芯键合垫之间形成引线键合体相同的工艺，从所述第二半导体裸芯的裸芯键合垫向所述插入物层的第二表面上的第一接触垫形成引线键合体的步骤。
17.根据权利要求16所述的方法，还包括将在所述步骤(e)中的从所述第二半导体裸芯的裸芯键合垫到所述插入物层的第二表面上的第一接触垫的引线键合体嵌入在膜层中。
18.根据权利要求16所述的方法，还包括将所述第二裸芯堆叠直接安装到所述膜层的步骤。
19.根据权利要求16所述的方法，还包括将所述第三半导体裸芯引线键合到所述插入物层的第二表面上的第二接触垫的步骤。
20.根据权利要求19所述的方法，还包括在所述插入物层的各相对边缘处提供所述插入物层的所述第一接触垫和第二接触垫的步骤。
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