CN109243981B - 封装结构及其制造方法 - Google Patents

封装结构及其制造方法 Download PDF

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Publication number
CN109243981B
CN109243981B CN201710845069.8A CN201710845069A CN109243981B CN 109243981 B CN109243981 B CN 109243981B CN 201710845069 A CN201710845069 A CN 201710845069A CN 109243981 B CN109243981 B CN 109243981B
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die
package
semiconductor die
stacked
carrier
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CN109243981A (zh
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林汉文
徐宏欣
张简上煜
林南君
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Powertech Technology Inc
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Powertech Technology Inc
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Abstract

本发明提供一种封装结构及其制造方法。所述制造方法包括以下步骤：提供载体，在载体上设置半导体晶粒以及至少一牺牲结构；通过多条导线使半导体晶粒与牺牲结构上的接合垫电性连接；于载体上形成封装体以密封半导体晶粒、牺牲结构以及导线；剥离载体，并通过薄化工程来移除牺牲结构的至少一部分；于半导体晶粒与封装体上形成重布线层，所述重布线层通过导线电性连接至半导体晶粒。

Description

封装结构及其制造方法
技术领域
本发明涉及一种封装结构，尤其涉及一种使用牺牲结构用于引线接合(wirebonding)的一种封装结构的制造方法。
背景技术
为了使电子产品设计实现轻薄、短小的特征，半导体封装技术不断进步以试图开发出体积更小、重量更轻、整合性更高以及在市场上竞争力更高的产品。举例来说，由于集成扇出封装(integrated fan-out package)的紧密性，其变得越来越受欢迎。然而，在现有的扇出封装设计中，如果封装需要多晶粒的堆叠，则通常需要两个重布线层(redistribution layer)以及较大的支柱(pillars)来提供连结。对于此类型的封装设计，其制造过程通常较为复杂、较为耗时，且也有翘曲的问题存在。因此，目前需要生产成本较低且经简化的制造方法/产品设计。
发明内容
本发明提供一种封装结构及其制造方法，其通过使用牺牲结构来固定用于引线接合的导线的位置。所述方法有效地降低了封装的尺寸和制造成本，并且克服了芯片或面板的翘曲问题。
本发明提供一种封装结构的制造方法。所述方法包括以下步骤。提供一载体。在载体上设置半导体晶粒以及牺牲结构。通过多条导线使半导体晶粒与牺牲结构上的接合垫电性连接。于载体上形成封装体以密封半导体晶粒、牺牲结构以及导线。剥离载体，并通过薄化工程来移除牺牲结构以暴露出接合垫或是导线。于半导体晶粒与封装体上形成重布线层。所述重布线层通过导线电性连接至半导体晶粒。
在本发明的一实施例中，所述薄化工程会移除半导体晶粒的一部分以形成薄化半导体晶粒。
在本发明的一实施例中，所述封装结构的制造方法，还包括：于牺牲结构上形成多个被动元件，且形成封装体以密封被动元件。
在本发明的一实施例中，在移除牺牲结构之后，重布线层是形成在半导体晶粒与封装体上，且重布线层是与半导体晶粒以及被动元件电性连接。
本发明另提供一种封装结构，其包括封装体、堆叠晶粒、多个接合垫、多条导线以及重布线层。所述封装体具有顶表面以及与顶表面相对的底表面。堆叠晶粒嵌入于封装体中。接合垫嵌入于封装体中，其中接合垫暴露在封装体的顶表面上。导线嵌入于封装体中，其中堆叠晶粒通过导线与接合垫电性连接。重布线层设置于堆叠晶粒上且位于封装体的顶表面上，其中重布线层通过接合垫及导线与堆叠晶粒电性连接。
在本发明的一实施例中，所述封装体具有第一厚度，且重布线层具有比第一厚度还小的第二厚度。
在本发明的一实施例中，所述封装体提供第一刚性，重布线层提供第二刚性，且第一刚性大于第二刚性。
在本发明的一实施例中，所述封装结构还包括：多个导电球设置在重布线层上。
在本发明的一实施例中，所述接合垫以第一间距配置，导电球以第二间距配置，且第二间距大于第一间距。
基于上述，是通过使用牺牲结构来固定导线的位置。因此，当移除牺牲结构时，能够提供导线或焊点的具体位置以用于进一步的连接。此外，可以在进行薄化工程期间有效地控制半导体晶粒的厚度，从而可以减小封装结构的整体尺寸。另外，由于牺牲结构的存在，晶粒与封装体之间的面积比可降低。因此，可以解决芯片或面板的翘曲问题。整体来说，能够实现封装结构制造工程的简化，进而降低制造成本。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A至图1G为依据本发明实施例封装结构的制造方法的剖面示意图；
图2A至图2G为依据本发明实施例封装结构的制造方法的剖面示意图。
附图标号说明：
100、100’：封装
102：载体
103：黏合层
104A：半导体晶粒
104A-1：第一半导体晶粒
104A-2：第二半导体晶粒
104A-3：第三半导体晶粒
104B：牺牲结构
104T、K1、K2、T1、T2：厚度
105：接合垫
106：导线
108：封装体
108T：第一厚度
110：重布线层
110A：导电元件
110B：介电层
110T：第二厚度
115：被动元件
118：导电端点
120：导电球
CT：连接端点
DL：切割线
DP：晶粒焊盘
P1：第一间距
P2：第二间距
S1：第一表面
W1、W2、W3：宽度
X1：厚度差
Y1：第一表面
Y2：第二表面
具体实施方式
接下来，将配合附图对本发明的较佳实施例进行详细说明。在附图和说明书中，相同或相似的元件将尽可能地以相同标号表示。
图1A至图1G为依据本发明实施例封装结构的制造方法的剖面示意图。参考图1A，提供了载体102。所述载体102可以是玻璃基板或是玻璃支撑板。在一些实施例中，其它适合的基板材料也可适用于载体102，只要是所运用的材料能够在后续处理步骤中承载形成于其上方的封装结构即可。
牺牲结构104B是设置于载体102上。所述牺牲结构104B例如是在后续步骤中被移除的牺牲层。因此，牺牲层的材料没有特别限制，只要是能通过后续的薄化工程步骤来移除即可。牺牲结构104B是通过位于载体102上的黏合层103而设置在载体102上。在一些实施例中，黏合层103可以是晶粒接合膜(die attach film)，或是通过包含环氧树脂的黏合材料所形成。黏合层103可以例如通过涂布、喷墨印刷、膜层贴合或其它适合的方法来形成以提供结构的支撑，并消除牺牲结构104B和载体102之间使用机械固定的必要性。
半导体晶粒104A是设置在载体102上，且位于牺牲结构104B上方。在本实施例中，半导体晶粒104A例如为包括至少一底部半导体晶粒与顶部半导体晶粒彼此堆叠的堆叠晶粒。举例来说，如图1A所示，半导体晶粒104A具有彼此堆叠的第一半导体晶粒104A-1、第二半导体晶粒104A-2以及第三半导体晶粒104A-3。第一导体晶粒104A-1是做为底部半导体晶粒，且第三半导体晶粒104A-3是做为顶部半导体晶粒，而第二半导体晶粒104A-2夹层于两者之间。然而，本发明不以此为限。在半导体晶粒104A中的堆叠晶粒的数量没有特别限制。在一些实施例中，可在每个堆叠的晶粒之间设置晶粒接合膜(图中未示出)以增加它们的黏附性。此外，在本实施例中，半导体晶粒104A例如为特定应用集成电路(Application-Specific Integrated Circuit；ASIC)。然而，本发明不以此为限。也可以使用其它适合的主动元件做为半导体晶粒104A。
如图1A所示，牺牲结构104B的宽度W2大于半导体晶粒104A的宽度W1。在有堆叠晶粒的情况下，牺牲结构104B的宽度W2是大于各个半导体晶粒(104A-1、104A-2以及104A-3)的宽度。所述半导体晶粒104A或是堆叠晶粒各自具有面向载体102的第一表面Y1以及背离载体102的第二表面Y2。此外，接合垫105是设置在牺牲结构104B上，并且是设置在半导体晶粒104A(堆叠晶粒)的第二表面Y2上。所述接合垫105例如是铝焊垫，或是用于引线接合的其它任何适合的材料。在一些实施例中，接合垫105可嵌入于牺牲结构104B内。
另外，如图1A所示，提供有多条导线106以将半导体晶粒104A的接合垫105电性连接至牺牲结构104B的接合垫105。所述导线106例如是用于引线接合，并且具有弯曲的三维结构。在一些实施例中，是在堆叠多个晶粒为一组之后再形成导线106。举例来说，对于多晶粒的堆叠，是在堆叠两个至四个晶粒之后再使用导线106来提供电性连接。如图1A所示的实施例中，在将第一半导体晶粒104A-1设置在牺牲结构104B上之后，并且将第二半导体晶粒104A-2设置在第一半导体晶粒104A-1上之后，是使用导线106将堆叠的半导体晶粒(104A-1及104A-2)上的接合垫105电性连接至牺牲结构104B上的接合垫105。可重复上述的过程一直到将所有的晶粒堆叠，并且建立起电性连接。在一些替代性的实施例中，是在所有的晶粒(104A-1、104A-2及104A-3)堆叠之后再形成导线106。
参考图1B，在引线接合之后，在载体102上形成封装体108以密封半导体晶粒104A、牺牲结构104B以及导线106。半导体晶粒104A、牺牲结构104B以及导线106被封装体108完全密封。在一些实施例中，封装体108可以是通过模制处理形成的模制化合物(moldingcompound)。然而，在一些替代性的实施例中，封装体108可以例如由环氧树脂或其它合适的树脂等绝缘材料所形成。基本上，当晶粒与封装体的面积比较低时，可能会造成晶圆或是面板翘曲的问题发生。如图1B所示，通过使用牺牲结构104B做为基底结构，可增加晶粒(半导体晶粒加上做为虚设晶粒的牺牲结构)与封装体108的面积比。据此，能够解决晶圆或是面板翘曲的问题。
参考图1C，将载体102剥离。也就是说，将载体102与封装体108、半导体晶粒104A及牺牲结构104B分离。在一些替代性的实施例中，为了增加半导体晶粒104A和牺牲结构104B从载体102上剥离的剥离性，可以在将晶粒(104A/104B)放置在载体102之前，先将离型层(图中未示出)设置在载体102上。所述离型层可以例如是光热转换(light to heatconversion；LTHC)离型层，或是其它适合的离型层。
参考图1D，在剥离载体102之后，是通过薄化工程来移除牺牲结构104B以暴露/显露出导线106。具体来说，导线106的连接端点CT被暴露出。在本实施例中，连接端点CT指的是导线106可用于进一步连接的端点部分。然而，本发明不以此为限。在替代性的实施例中，所述连接端点CT可以是接合垫105或是导线106的螺柱(studs)中可用于进一步连接的部分。也就是说，连接端点CT基本上是被视为将导线106连接到后续步骤中形成的重布线层110上的“连接点”部分。其中，接合垫105或是导线106的螺柱的表面积可以大于导线106的剖面面积。
继续参考图1D，薄化工程可以通过机械研磨、化学机械研磨(chemicalmechanical polishing；CMP)或是其它适合的方法来进行。在所述薄化工程之后，被显露的导线106的连接端点CT与半导体晶粒104A的第一表面S1为共平面。在一些实施例中，所述薄化工程可以移除半导体晶粒104A的一部分以形成薄化的半导体晶粒104A。举例来说，在本实施例中，第一半导体晶粒104A-1(或底部半导体晶粒)的一部分是通过薄化工程部分地移除，进而，(导线106的)连接端点CT与第一半导体晶粒104A-1(底部半导体晶粒)的第一表面S1会成为共平面。也就是说，第一半导体晶粒104A-1的厚度会减小。更具体地，参考图1C，第一半导体晶粒104A-1在薄化工程之前具有厚度T1，而如图1D所示，在薄化工程之后，第一半导体晶粒104A-1的厚度会减小至T2。在本实施例中，在进行薄化工程时，半导体晶粒104A的厚度可以减小。但本发明不以此为限。在其它实施例中，半导体晶粒104A的厚度即使在进行薄化工程之后也不会改变。在替代性的实施例中，半导体晶粒104A的厚度可以在薄化工程中依据需求而进行调整。
如图1D所示，牺牲结构104B上的接合垫105通过薄化工程而被移除以暴露出其下方的导线106。也就是说，导线106的端部可被视做为连接端点CT。然而，本发明并不以此为限。在替代性的实施例中，牺牲结构104B上的接合垫105在薄化工程后仍会保留于其上方。在这样的实施例中，是进行薄化工程以暴露出牺牲结构104B上的接合垫105，并且，接合垫105所暴露出的部分可做为连接端点CT。此外，牺牲结构104B可以通过薄化工程而被完全移除，或者，在薄化工程之后可以残留有些许的牺牲结构104B。
参考图1E，通过薄化工程移除牺牲结构104B之后，是在半导体晶粒104A与封装体108上形成重布线层110。所述重布线层110可以包括有彼此交替地形成并堆叠的多个导电元件110A和多个介电层110B。如图1E所示，所述重布线层110包括四个介电层110B。然而，介电层110B的数量没有特别限制，而可以是基于电路设计来进行调整。所述导电元件110A可以包括多个迹线层(trace layers)以及连接迹线层的多个内连结构(interconnectstructure)。此外，在本实施例中，重布线层110是形成在半导体晶粒104A(堆叠晶粒)的第一表面S1上。所述重布线层110是通过导线106的连接端点CT处与半导体晶粒104A电性连接。特别是，导线106是通过连接端点CT与重布线层110的导电元件110A电性连接。接着，是在重布线层110上形成导电端点118，并使其与导电元件110A电性连接。所述导电端点118可以是用于安置球体的多个球下金属图案(under-ball metallurgy；UBM)，或是用于设置被动元件的连接垫。
如图1F所示，在形成重布线层110以及导电端点118之后，是在导电端点118上设置多个导电球120，并且一个或多个被动元件115可以是设置在导电端点118之上。导电端点118和导电球120可以例如是通过球形放置工程(ball placement process)和回焊工程(reflow process)来形成。被动元件115可以是通过焊接工程设置在导电端点118上。在本实施例中，被动元件115例如是设置于重布线层110的第二表面(上表面)上，并且是暴露在封装结构的外部。被动元件115的实例包括电容器、电阻器、电感器、保险丝或天线等。然而，本发明并不以此为限。在将导电球120和被动元件115放置在导电端点118上之后，是对图1F所示的封装结构进行切割(dicing)或分割工程(singulation process)，以呈现如图1G所示的多个单独的封装100。所述切割工程例如是在切割线DL处进行切割处理以将各个封装100分离。
图2A至图2G为依据本发明实施例封装结构的制造方法的剖面示意图。图2A至图2G所示的实施例与图1A至图1G所示的实施例类似，因此，相同元件以相同标号表示，而其详细内容将不予赘述。图2A至图2G所示的实施例与图1A至图1G所示的实施例的差异在于，牺牲结构104B的位置/设计。
如图2A所示，半导体晶粒104A和至少一个牺牲结构104B是设置在载体102上。在示例性的实施例中，多个牺牲结构104B是设置在载体102上以环绕半导体晶粒104A。此外，半导体晶粒104A与牺牲结构104B是设置在载体102的同一平面及同一表面102A上。在本实施例中，牺牲结构104B的宽度(W2/W3)小于半导体晶粒104A的宽度W1。多个牺牲结构104B可以具有不同的宽度W2和W3。然而，宽度W2和W3皆是小于半导体晶粒104A的宽度W1。此外，牺牲结构104B的厚度K2是小于半导体晶粒104A的厚度K1。半导体晶粒104A的厚度K1是指堆叠晶粒中的第一半导体晶粒104A-1(底部半导体晶粒)的厚度。在本实施例中，牺牲结构104B也是在后续步骤中被移除的牺牲层。也就是说，半导体晶粒104A和牺牲结构104B之间的厚度差X1(K1-K2)将决定在后续步骤形成的薄化半导体晶粒104A的厚度。
类似于图1A所示的实施例，接合垫105可以是形成在半导体晶粒104A与牺牲结构104B上以用于引线接合。所述引线接合处理例如是在堆叠多个晶粒为一组之后，或是堆叠所有晶粒之后而进行的。此外，被动元件115可以设置在牺牲结构104B上。举例来说，被动元件115可以与接合垫105相邻设置，并且可以设置在牺牲结构104B的同一表面上。此外，提供有多条导线106以将半导体晶粒104A的接合垫105与牺牲结构104B的接合垫105电性连接。
参考图2B，类似于图1B所示的实施例，在载体102上形成封装体108以密封半导体晶粒104A、牺牲结构104B以及导线106。然而，在图2B的实施例中，所述封装体108更会密封被动元件115。半导体晶粒104A、牺牲结构104B、导线106以及被动元件115是被封装体108完全密封。如图2B所示，通过设置牺牲结构104B使其环绕半导体晶粒104A，可增加晶粒(半导体晶粒加上牺牲虚设晶粒)与封装体108的面积比。据此，能够解决晶圆或是面板翘曲的问题。
参考图2C，在形成封装体108之后，是将载体102剥离。也就是说，是将载体102与封装体108、半导体晶粒104A及牺牲结构104B分离。在一些替代性的实施例中，为了增加半导体晶粒104A和牺牲结构104B从载体102上剥离的剥离性，可以在将晶粒(104A/104B)放置在载体102之前，先将离型层(图中未示出)设置在载体102上。所述离型层可以例如是光热转换(light to heat conversion；LTHC)离型层，或是其它适合的离型层。
参考图2D，在剥离载体102之后，是通过薄化工程来移除牺牲结构104B以暴露/显露出牺牲结构104B上的接合垫105。也就是说，接合垫105的显露部分可做为连接端点CT。然而，本发明不以此为限。在替代性的实施例中，连接端点CT也可以是导线106的端点部分(或是螺柱)。也就是说，可通过执行薄化工程以暴露/显露出导线106的端点部分。如上所述，连接端点CT基本上是被视为将导线106连接到后续步骤中形成的重布线层110上的「连接点」部分。因此，连接端点CT将适用于所有实施例，并且其位置可以是基于哪个用于连接的部分被显露出来(线/焊盘)而进行改变。
如图2D所示，在薄化工程之后，接合垫105的连接端点CT是与半导体晶粒104A的第一表面S1为共平面。特别地，是通过薄化工程移除第一半导体晶粒104A-1(或底部半导体晶粒)的一部分，使得连接端子CT与第一半导体晶粒104A-1的第一表面S1为共平面(底部半导体晶粒)。此外，薄化半导体晶粒(第一半导体晶粒104A-1)的厚度104T是对应于在进行薄化工程之前，半导体晶粒104A(第一半导体晶粒104A-1)和牺牲结构104B之间的厚度差X1(参见图2A)。
参考图2E，通过薄化工程移除牺牲结构104B之后，是在半导体晶粒104A与封装体108上形成重布线层110。图2E所示的重布线层110与图1E所示的重布线层110类似，因此，在此省略其详细的描述。在本实施例中，被动元件115例如是设置于重布线层110的第一表面(下表面)上，并且嵌入于封装体108中。此外，重布线层110是通过导线106的连接端点CT处与半导体晶粒104A电性连接。特别是，导线106是通过(接合垫105的)连接端点CT与重布线层110的导电元件110A电性连接。接着，是在重布线层110上形成导电端点118，并使其与导电元件110A电性连接。
参考图2F，在形成重布线层110以及导电端点118之后，是在导电端点118上设置多个导电球120。导电端点118和导电球120可以例如是通过球形放置工程和回焊工程来形成。在将导电球120放置在导电端点118上之后，是对图2F所示的封装结构进行切割(dicing)或分割工程(singulation process)，以呈现如图2G所示的多个单独的封装100’。所述切割工程例如是在切割线DL处进行切割处理以将各个封装100’分离。
参考图2G，各个封装100’包括封装体108、堆叠晶粒104A、多个接合垫105、多条导线106、重布线层110以及多个导电球120。所述封装体108具有顶表面108A以及与顶表面108A相对的底表面108B。堆叠晶粒104A嵌入于封装体108中。接合垫105嵌入于封装体108中，其中接合垫105的连接端点CT暴露在封装体108的顶表面108A上。导线106嵌入于封装体108中，其中堆叠晶粒104A通过导线106与接合垫105电性连接。重布线层110设置于堆叠晶粒104A上且位于封装体108的顶表面108A上，其中重布线层110通过接合垫105及导线106与堆叠晶粒104A电性连接。
在示例性的实施例中，堆叠晶粒(半导体晶粒104A)具有通过封装体108而暴露出的第一表面S1。接合垫105的连接端点CT与堆叠晶粒104A的第一表面S1以及封装体108的顶表面108A为共平面。此外，堆叠晶粒104A可包括第一晶粒(第一半导体晶粒)104A-1、第二晶粒(第二半导体晶粒)104A-2以及第三晶粒(第三半导体晶粒)104A-3。第一晶粒104A-1具有通过封装体108而暴露出的第一表面S1。第二晶粒104A-2堆叠在第一晶粒104A-1上与第一表面S1相对的一侧。第二晶粒104A-2覆盖第一晶粒104A-1的一部分，且未被第二晶粒104A-2覆盖的第一晶粒104A-1的其他部分包括晶粒焊盘DP(接合垫105)。第一晶粒104A-1的晶粒焊盘DP通过导线106与接合垫105电性连接。此外，第三晶粒104A-3堆叠在第二晶粒104A-2上，且第三晶粒104A-3覆盖第二晶粒104A-2的一部分，且未被第三晶粒104A-3覆盖的第二晶粒104A-2的其他部分包括晶粒焊盘DP，且第二晶粒104A-2的晶粒焊盘DP通过导线106与接合垫105电性连接。
如图2G的实施例所示，各个封装100’更包括至少一被动元件115嵌入于封装体108中。然而，本发明不以此为限。在替代性的实施例中，被动元件115可以是设置在重布线层110上。此外，在示例性的实施例中，封装体108具有第一厚度108T，且重布线层110具有比第一厚度108T还小的第二厚度110T。也就是说，封装体108提供第一刚性，而重布线层110提供第二刚性，且第一刚性大于第二刚性。此外，接合垫105是以第一间距P1配置，导电球120是以第二间距P2配置，且第二间距P2大于第一间距P1。也就是说，各个封装100’是对应于扇出封装(fan-out packages)。另外，第一间距P1和第二间距P2是基于接合垫105和导电球120的中心位置来计算。
在上述的实施例中，是通过使用牺牲结构来固定导线的位置。因此，当移除牺牲结构时，能够提供导线或焊点的具体位置以用于进一步的连接。此外，可以在进行薄化工程期间有效地控制半导体晶粒的厚度，从而可以减小封装结构的整体尺寸。另外，由于牺牲结构的存在，晶粒与封装体之间的面积比可降低。因此，可以解决芯片或面板的翘曲问题。整体来说，能够实现封装结构制造工程的简化，进而降低制造成本。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的精神和范围内，当可作些许的更改与润饰，故本发明的保护范围当视权利要求书所界定的为准。

Claims (10)

1.一种封装结构的制造方法，其特征在于，包括：
提供载体；
于所述载体上设置半导体晶粒以及至少一牺牲结构；
通过多条导线将所述半导体晶粒电线连接至所述牺牲结构上的接合垫；
于所述载体上形成封装体以密封所述半导体晶粒、所述牺牲结构以及所述多条导线；
剥离所述载体；
通过薄化工程来移除所述牺牲结构；以及
于所述半导体晶粒与所述封装体上形成重布线层，其中所述重布线层通过所述多条导线电性连接至所述半导体晶粒。
2.根据权利要求1所述的封装结构的制造方法，其特征在于，所述牺牲结构是设置在所述载体上，所述半导体晶粒是设置在所述牺牲结构上，且所述牺牲结构的宽度大于所述半导体晶粒的宽度。
3.根据权利要求1所述的封装结构的制造方法，其特征在于，所述重布线层是在移除所述牺牲结构后形成在所述半导体晶粒与所述封装体上，并且将多个被动元件设置在所述重布线层上。
4.根据权利要求1所述的封装结构的制造方法，其特征在于，在进行所述薄化工程之后会暴露出所述接合垫或是暴露出所述多条导线。
5.根据权利要求1所述的封装结构的制造方法，其特征在于，多个所述牺牲结构是设置在所述载体上以环绕所述半导体晶粒，且所述半导体晶粒与所述牺牲结构是设置在所述载体的同一平面及同一表面上。
6.一种封装结构，其特征在于，包括：
封装体，其具有顶表面以及与所述顶表面相对的底表面；
堆叠晶粒，嵌入于所述封装体中，所述堆叠晶粒具有通过所述封装体而暴露出的第一表面；
多条导线，嵌入于所述封装体中，所述封装体仅暴露出所述多条导线的连接端点，其中所述堆叠晶粒与所述多条导线电性连接，且所述连接端点与所述堆叠晶粒的所述第一表面为共平面；以及
重布线层，设置于所述堆叠晶粒上且位于所述封装体的所述顶表面上，其中所述重布线层直接接触所述多条导线的所述连接端点且通过所述多条导线与所述堆叠晶粒电性连接。
7.根据权利要求6项所述的封装结构，其特征在于，还包括：
至少一被动元件，设置于所述重布线层的第二表面上，并且暴露在所述封装结构的外部。
8.根据权利要求6所述的封装结构，其特征在于，所述堆叠晶粒的所述第一表面与所述封装体的所述顶表面为共平面。
9.根据权利要求6所述的封装结构，其特征在于，所述堆叠晶粒包括：
第一晶粒，其具有通过所述封装体而暴露出的所述第一表面；
第二晶粒，堆叠在所述第一晶粒上与所述第一表面相对的一侧，且所述第二晶粒覆盖所述第一晶粒的一部分，且未被第二晶粒覆盖的所述第一晶粒的其他部分包括晶粒焊盘，且所述第一晶粒的所述晶粒焊盘与所述多条导线电性连接。
10.根据权利要求9所述的封装结构，其特征在于，所述堆叠晶粒还包括：
第三晶粒，堆叠在所述第二晶粒上，且所述第三晶粒覆盖所述第二晶粒的一部分，且未被第三晶粒覆盖的所述第二晶粒的其他部分包括晶粒焊盘，且所述第二晶粒的所述晶粒焊盘与所述多条导线电性连接。
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