TWI495066B - 晶圓級封裝結構及其製造方法 - Google Patents

晶圓級封裝結構及其製造方法 Download PDF

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Publication number
TWI495066B
TWI495066B TW101131685A TW101131685A TWI495066B TW I495066 B TWI495066 B TW I495066B TW 101131685 A TW101131685 A TW 101131685A TW 101131685 A TW101131685 A TW 101131685A TW I495066 B TWI495066 B TW I495066B
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Taiwan
Prior art keywords
bonding wires
die
external connection
active surface
connection terminals
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TW101131685A
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English (en)
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TW201409639A (zh
Inventor
Tsung Jen Liao
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Chipmos Technologies Inc
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Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Priority to TW101131685A priority Critical patent/TWI495066B/zh
Priority to CN201310058953.9A priority patent/CN103681534A/zh
Priority to US13/846,608 priority patent/US8836144B2/en
Publication of TW201409639A publication Critical patent/TW201409639A/zh
Priority to US14/325,811 priority patent/US8980695B2/en
Application granted granted Critical
Publication of TWI495066B publication Critical patent/TWI495066B/zh

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Description

晶圓級封裝結構及其製造方法
本發明係關於一種晶圓級封裝結構及其製造方法，特別係關於一種適用於立體堆疊之晶圓級封裝結構及其製造方法。
因應目前電腦與消費電子產品之可攜式及多功能的要求，其外形尺寸需不斷縮小，而積體電路晶片之積體電路密度則不斷提升。受限於可用空間的限制，因此許多不同的封裝方式如：多晶片模組(multi-chip module；MCM)、覆晶封裝(flip chip package)、三維垂直堆疊封裝(3D stack package)、晶圓級晶片尺寸封裝(wafer level chip scale package；WLCSP)等技術應運而生。晶圓級封裝技術的概念基本上是在整片晶圓上執行晶片尺寸的封裝技術，也就是在晶圓階段就完成了於積體電路晶片上直接形成錫球等大部分的封裝工作，不但省略了傳統封裝技術中承載晶片之基板或導線架，也簡化了封裝製程。因此，晶圓級晶片尺寸封裝可以縮小封裝體尺寸，並且在製程及材料成本上也相當具有優勢。
而為了在相同面積下做出更高積體電路密度的半導體結構，三維封裝取代二維封裝是不可避免的。目前的三維垂直堆疊封裝大多使用矽穿孔(through silicon via；TSV)結構形成上下導通，然而其製作成本及難度皆盛高。本發明揭露一種特殊的半導體封裝結構，能夠藉由其重複堆疊 達到三維晶圓級封裝的效果。
一種改良式的晶圓級封裝結構-擴散型(fan-out)晶圓級封裝，是在晶片之主動表面形成擴散到晶片外的重佈線層(Redistribution Layer；RDL)。此種封裝結構只有單一表面可設置錫球，以電性連接至印刷電路板上，並無法形成三維晶粒對晶粒(die-to-die)、三維晶圓對晶圓(wafer-to-wafer)或三維晶粒對晶圓(die-to-wafer)的堆疊結構。
再者，擴散型(fan-out)晶圓級封裝因未使用基板或導線架等承載件，僅以封膠體包覆晶片，其結構強度較不足，且封膠體的熱傳導係數與晶片的熱傳導係數差異甚大，因此容易產生翹曲(warpage)現象，進而影響封裝結構的可靠度。
為了達成三維垂直堆疊晶圓級封裝，本發明揭露一種新的結構與製作方法，以低成本及簡化的製程形成上下導通的封裝結構，以進行半導體結構之垂直堆疊。
本發明一實施例揭露一半導體封裝結構，該結構包含一晶粒、複數條銲線、一封膠體以及複數個第一外部連接端子。晶粒包含一主動表面及一相對於主動表面的背表面。各銲線之一第一端連接晶粒之背表面，相對於第一端之一第二端與主動表面電連接。封膠體覆蓋晶粒的背表面及銲線，其中各銲線之局部未被覆蓋。第一外部連接端子設 置於封膠體之上，並分別包覆未被封膠體覆蓋之銲線且電連接銲線。根據本發明另一實施例，上述半導體封裝結構進一步包含形成於封膠體上的至少一凹陷結構，用以容納第一外部連接端子。根據本發明另一實施例，上述半導體封裝結構進一步包含複數個導電銲墊，與銲線之第二端連接。
本發明另一實施例揭露一半導體堆疊結構，堆疊結構包含兩個以上的半導體封裝結構相互堆疊，其中該半導體封裝結構包含一晶粒、複數條銲線、一封膠體以及複數個第一外部連接端子。晶粒包含一主動表面及一相對於主動表面之背表面；各銲線之一第一端連接晶粒之背表面，相對於第一端之一第二端與主動表面電連接；封膠體覆蓋晶粒的背表面及銲線，其中各銲線之局部未被覆蓋。第一外部連接端子設置於封膠體之上，並分別包覆未被封膠體覆蓋之銲線且電連接銲線；其中半導體封裝結構透過第一外部連接端子相互電連接，以形成半導體堆疊結構。
本發明一實施例所揭露的一半導體封裝結構由以下方法製造：提供一承載板；設置一晶粒於承載板上，晶粒包含一主動表面以及相對主動表面之一背表面，其中主動表面與承載板相接；形成複數條銲線，各銲線具有一第一端及相對第一端之一第二端，第一端連接晶粒之背表面，第二端連接承載板；形成一封膠體，覆蓋晶粒及銲線，其中各銲線之局部未被覆蓋；移除承載板；電連接銲線之第二端與晶粒之主動表面；以及形成複數個第一外部連接端子於 封膠體之上，第一外部連接端子分別包覆未被封膠體覆蓋之銲線且與銲線電連接。
上文已相當廣泛地概述本揭露之技術特徵，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
圖1為依據本發明一實施例顯示的一半導體封裝結構10，半導體封裝結構10包含一晶粒11、複數條銲線14、一封膠體13以及複數個第一外部連接端子16，其中第一外部連接端子16可為錫球。晶粒11包含一主動表面121及一相對主動表面121之背表面122，主動表面121上具有複數個接墊121A。銲線14之一第一端14A連接晶粒11之背表面122。本實施例中銲線14之材質可為銅、銀、鈀、金或其合金；銲線14是以現行之打線製程所形成，且所形成之銲線14為圓弧形。封膠體13覆蓋晶粒11的背表面122及銲線14，其中各銲線14的局部未被封膠體13覆蓋而暴露於封膠體13之外；更具體而言，銲線14未被封膠體13所覆蓋的部位為圓弧之頂部。第一外部連接端子16設置於封膠體13之上，並分別 對應置放在暴露於封膠體13之外的銲線14上以包覆銲線14並與銲線14電連接。本實施例中，銲線14相對於第一端14A之第二端14B與晶粒11之主動表面121藉由一圖案化導電層40電連接；更具體而言，圖案化導電層40包含複數個導電跡線41，各導電跡線41分別電連接銲線14之第二端14B與主動表面121上之接墊121A。半導體封裝結構10透過銲線14分別與第一外部連接端子16和晶粒11之主動表面121電連接，而形成上下電性導通之封裝結構，因此可進一步進行半導體封裝結構之垂直堆疊作業。
圖2為依據本發明另一實施例顯示一半導體封裝結構10A，本實施例除了具有圖1中半導體封裝結構10的特徵外，進一步具有與圖案化導電層40(本實施例中為複數個導電跡線41)電連接的複數個第二外部連接端子31。半導體封裝結構10A可透過第二外部連接端子31與印刷電路板(未顯示)連接或與另一個半導體封裝結構(未顯示)連接，且第二外部連接端子31可為錫球。
圖3為依據本發明另一實施例顯示一半導體封裝結構10B，本實施例除了具有圖2中半導體封裝結構10A的特徵外，圖案化導電層40進一步包含設置於導電跡線41上的複數個導電銲墊21，銲線14之第二端14B與導電銲墊21連接，導電銲墊21有助於銲線14與圖案化導電層40之接合以及打線製程之對位。
圖4依據本發明另一實施例顯示一半導體封裝結構10C ，本實施例除了具有圖2中半導體封裝結構10A的特徵外，進一步於封膠體13之上表面823形成至少一凹陷結構821，凹陷結構821對應銲線14之位置而設置，用以容納第一外部連接端子16，使第一外部連接端子16分別包覆未被封膠體13覆蓋之銲線14且與銲線14電連接。半導體封裝結構10C也可藉由凹陷結構821使銲線14局部暴露於封膠體13之外。凹陷結構821之數量可大於或等於一，且其形狀並不限制，可為分別對應單一第一外部連接端子16之多個凹洞，或對應多個第一外部連接端子16之長條凹槽或環形凹槽。本實施例並不限制第一外部連接端子16設置於凹陷結構821內，可另包含複數個置放於封膠體13之上表面823上的第一外部連接端子16。
圖5依據本發明圖1或圖3之實施例，顯示一半導體封裝結構中晶粒11與圖案化導電層40電連接的俯視圖。請同時參考圖1或圖3，圖案化導電層40包含複數個導電跡線41，各導電跡線41之一端與晶粒11之主動表面121上的接墊121A電連接，另一端延伸至晶粒11之外，銲線14分別連接晶粒11之背表面122與導電跡線41，而第一外部連接端子16設置於封膠體13之上，並分別包覆未被封膠體13覆蓋之銲線14而與銲線14電連接。較佳地，如圖3所示，導電跡線41上可具有導電銲墊21，銲線14則連接晶粒11之背表面122與導電銲墊21，導電銲墊21的設置有利於打線製程之對位以及銲線14與圖案化導電層40之接合。本實施例中，電連接 單個第一外部連接端子16與單個導電跡線41/導電銲墊21的銲線14數目可為一條或複數條。以複數條銲線14電連接單個第一外部連接端子16與單個導電跡線41/導電銲墊21，可確保各電性接點間完整連接。
圖6依據本發明另一實施例顯示一半導體堆疊結構100。半導體堆疊結構100包含兩個以上的半導體封裝結構10相互垂直疊置，其中一個半導體封裝結構10包含一晶粒11、複數條銲線14、一封膠體13以及複數個第一外部連接端子16。晶粒11包含一主動表面121及一相對主動表面121之背表面122，主動表面121上具有複數個接墊121A。銲線14之一第一端14A連接晶粒11之背表面122。封膠體13覆蓋晶粒11的背表面122及銲線14，其中各銲線14的局部未被封膠體13覆蓋而暴露於封膠體13之外。第一外部連接端子16設置於封膠體13之上，並分別對應置放在暴露於封膠體13之外的銲線14上以包覆銲線14並與銲線14電連接。本實施例中，銲線14相對於第一端14A之第二端14B與晶粒11之主動表面121藉由一圖案化導電層40電連接；更具體而言，圖案化導電層40包含複數個導電跡線41，各導電跡線41分別電連接銲線14之第二端14B與主動表面121上之接墊121A。半導體封裝結構10透過銲線14分別與第一外部連接端子16和晶粒11之主動表面121電連接，而形成上下電性導通之封裝結構。因此，半導體封裝結構10可藉由第一外部連接端子16與另一個半導體封裝結構10相互電連接，以形成半導體 堆疊結構100。雖然圖6實施例的兩個半導體封裝結構10為相同結構，但本發明所涵蓋的範圍不限於此，任兩個半導體封裝結構可以為相同也可不同，且也可選自如圖2、圖3或圖4之結構或其任一組合。
圖7依據本發明另一實施例顯示一半導體堆疊結構100A，本實施例除了具有圖6中半導體堆疊結構100的特徵外，半導體封裝結構10C進一步具有與導電跡線41電連接的複數個第二外部連接端子31。因此，半導體堆疊結構100A可藉由第二外部連接端子31與印刷電路板30連接或與其它外部元件(未顯示)連接。
圖8-1至圖8-6依據本發明另一實施例顯示一半導體封裝結構的製作步驟。見圖8-1，首先提供一承載板80，承載板80的上表面具有複數個銲點80A。見圖8-2，設置一晶粒11於承載板80上，晶粒11包含一主動表面121以及相對主動表面121之一背表面122，其中主動表面121具有複數個接墊121A，且晶粒11以主動表面121與承載板80相接。見圖8-3，形成複數條銲線14，此步驟可為現行之打線製程，且銲線14之材質可為銅、銀、鈀、金或其合金，銲線14具有一第一端14A及一第二端14B，第一端14A連接晶粒11之背表面122，第二端14B連接銲點80A。見圖8-4，形成一封膠體13，覆蓋晶粒11及銲線14，其中各銲線14之局部未被封膠體13覆蓋而暴露於封膠體13之外。本實施例中形成暴露出銲線14之局部的封膠體13的方式可先使封膠體13完全包覆 晶粒11與銲線14，再以一蝕刻步驟移除封膠體13表面直至暴露出銲線14之局部為止。
見圖8-5，移除承載板80，使銲線14之第二端14B顯露於封膠體13之外，並且形成一圖案化導電層40(本實施例中為複數個導電跡線41)於晶粒11的主動表面121以及封膠體13的下表面，使銲線14之第二端14B與晶粒11之主動表面121上的接墊121A電連接。見圖8-6，形成第一外部連接端子16於封膠體13之上，使第一外部連接端子16分別與暴露於封膠體13之外的銲線14電連接。本實施例中第一外部連接端子16可為錫球，而此步驟可為一植球步驟，植球方式例如但不限於網版印刷、蒸鍍、電鍍、落球、噴球等。另外，本實施例可選擇性地形成複數個分別與導電跡線41電連接的第二外部連接端子31。
圖9A至圖9B依據本發明之另一實施例顯示兩種半導體封裝結構。圖9A相較於圖8-6，進一步包含形成至少一凹陷結構821於封膠體13之上表面的步驟。凹陷結構821對應暴露於封膠體13之外的銲線14並用以容納第一外部連接端子16，有助於第一外部連接端子16之定位及附著效果。凹陷結構821可以藉由一蝕刻步驟形成，例如但不限於使用二氧化碳雷射的蝕刻步驟。由於二氧化碳雷射只會移除封膠體而不會移除金屬，因此蝕刻步驟能夠確保金屬銲線14不被破壞。圖9B相較於圖9A，進一步包含形成一球下金屬層(under bump metallization，UBM)1011於凹陷結構821內 ，球下金屬層1011位於第一外部連接端子16與封膠體13的上表面之間，可加強第一外部連接端子16與封膠體13間的結合力；再者，於封膠體13的上表面亦形成金屬結構的球下金屬層1011，使封膠體13之上下表面皆具有金屬結構，可改善封裝結構翹曲的問題。
圖10-1至圖10-6依據本發明另一實施例顯示一半導體封裝結構的製作步驟。見圖10-1，首先提供一承載板80，承載板80上設置一具有複數個凸起部20A之金屬層20。本實施例中可為厚度一致的銅膜金屬層，藉由一微影蝕刻步驟形成凸起部20A。見圖10-2，設置一晶粒11於金屬層20上，晶粒11包含一主動表面121以及相對主動表面121之一背表面122，其中主動表面121上具有接墊121A，且晶粒11以主動表面121與金屬層20相接。見圖10-3，形成複數條銲線14，此步驟可為現行之打線製程，且銲線14之材質可為銅、銀、鈀、金或其合金，銲線14具有一第一端14A及一第二端14B，第一端14A連接晶粒11之背表面122，第二端14B連接金屬層20之凸起部20A。見圖10-4，形成一封膠體13，覆蓋晶粒11及銲線14，其中各銲線14的局部未被覆蓋而暴露於封膠體13之外。本實施例中形成暴露出銲線14之局部的封膠體13的方式可先使封膠體13完全包覆晶粒11與銲線14，再以一蝕刻步驟移除封膠體13表面直至暴露出銲線14之局部為止。
見圖10-5，移除承載板80，並且進行一蝕刻步驟將圖 10-4中的金屬層20蝕刻形成一圖案化導電層40，圖案化導電層40包含複數個導電跡線41'以及由凸起部20A形成之複數個導電銲墊21'，各導電跡線41'分別對應連接晶粒11主動表面121上之接墊121A與導電銲墊21'。另一實施例中，在移除承載板80之後，上述蝕刻步驟可將圖10-4中的金屬層20完全蝕刻至只剩下凸起部20A所形成之導電銲墊21'，接著再以例如電鍍方式形成複數個導電跡線41'，使各導電跡線41'分別對應連接晶粒11主動表面121上之接墊121A與導電銲墊21'。
見圖10-6，形成第一外部連接端子16於封膠體13之上，使第一外部連接端子16分別與暴露於封膠體13之外的銲線14電連接。本實施例中第一外部連接端子16可為錫球，而此步驟可為一植球步驟，植球方式例如但不限於網版印刷、蒸鍍、電鍍、落球、噴球等。另外，本實施例可選擇性地形成複數個分別與導電跡線41'電連接的第二外部連接端子31。
圖11A至圖11B依據本發明之另一實施例顯示兩種半導體封裝結構。圖11A相較於圖10-6，進一步包含形成至少一凹陷結構821於封膠體13上表面的步驟。凹陷結構821對應暴露於封膠體13之外的銲線14並用以容納第一外部連接端子16，有助於第一外部連接端子16之定位及附著效果。凹陷結構821可以藉由一蝕刻步驟形成，例如但不限於使用二氧化碳雷射的蝕刻步驟。由於二氧化碳雷射只會移除封 膠體而不會移除金屬，因此蝕刻步驟能夠確保金屬銲線14不被破壞。圖11B相較於圖11A，進一步包含形成一球下金屬層(under bump metallization，UBM)1011於凹陷結構821內，球下金屬層1011位於第一外部連接端子16與封膠體13的上表面之間，可加強第一外部連接端子16與封膠體13間的結合力；再者，於封膠體13的上表面亦形成金屬結構的球下金屬層1011，使封膠體13之上下表面皆具有金屬結構，可改善封裝結構翹曲的問題。
本揭露之技術內容及技術特點已揭示如上，然而本揭露所屬技術領域中具有通常知識者應瞭解，在不背離後附申請專利範圍所界定之本揭露精神和範圍內，本揭露之教示及揭示可作種種之替換及修飾。例如，上文揭示之許多製程可以不同之方法實施或以其它製程予以取代，或者採用上述二種方式之組合。
此外，本案之權利範圍並不侷限於上文揭示之特定實施例的製程、機台、製造、物質之成份、裝置、方法或步驟。本揭露所屬技術領域中具有通常知識者應瞭解，基於本揭露教示及揭示製程、機台、製造、物質之成份、裝置、方法或步驟，無論現在已存在或日後開發者，其與本案實施例揭示者係以實質相同的方式執行實質相同的功能，而達到實質相同的結果，亦可使用於本揭露。因此，以下之申請專利範圍係用以涵蓋用以此類製程、機台、製造、物質之成份、裝置、方法或步驟。
10、10A、10B、10C‧‧‧半導體封裝結構
11‧‧‧晶粒
121‧‧‧主動表面
121A‧‧‧接墊
122‧‧‧背表面
13‧‧‧封膠體
14‧‧‧銲線
14A‧‧‧第一端
14B‧‧‧第二端
16‧‧‧第一外部連接端子
20‧‧‧金屬層
20A‧‧‧凸起部
21、21'‧‧‧導電銲墊
30‧‧‧印刷電路板
31‧‧‧第二外部連接端子
40‧‧‧圖案化導電層
41、41'‧‧‧導電跡線
80‧‧‧承載板
80A‧‧‧銲點
821‧‧‧凹陷結構
823‧‧‧封膠體上表面
100、100A‧‧‧半導體堆疊結構
1011‧‧‧球下金屬層
圖1依據本發明一實施例顯示一半導體封裝結構；圖2依據本發明另一實施例顯示一半導體封裝結構；圖3依據本發明另一實施例顯示一半導體封裝結構；圖4依據本發明另一實施例顯示一半導體封裝結構；圖5依據本發明圖1或圖3之實施例顯示一半導體封裝結構中晶粒與圖案化導電層電連接的俯視圖；圖6依據本發明另一實施例顯示一半導體堆疊結構；圖7依據本發明另一實施例顯示一半導體堆疊結構；圖8-1至圖8-6依據本發明另一實施例顯示一半導體封裝結構的製作步驟；圖9A至圖9B依據本發明之另一實施例顯示兩種半導體封裝結構；圖10-1至圖10-6依據本發明另一實施例顯示一半導體封裝結構的製作步驟；以及圖11A至圖11B依據本發明之另一實施例顯示兩種半導體封裝結構。
100‧‧‧半導體堆疊結構
10‧‧‧半導體封裝結構
11‧‧‧晶粒
121‧‧‧主動表面
121A‧‧‧接墊
122‧‧‧背表面
13‧‧‧封膠體
14‧‧‧銲線
14A‧‧‧銲線第一端
14B‧‧‧銲線第二端
16‧‧‧第一外部連接端子
40‧‧‧圖案化導電層
41‧‧‧導電跡線

Claims (17)

  1. 一種半導體封裝結構，該結構包含：一晶粒，包含一主動表面及一相對於該主動表面之背表面；複數條銲線，各該銲線之一第一端連接該晶粒之該背表面，相對於該第一端之一第二端與該主動表面電連接；一封膠體，覆蓋該晶粒的該背表面及該些銲線，其中各該銲線之局部未被覆蓋；以及複數個第一外部連接端子，設置於該封膠體之上，並分別包覆未被該封膠體覆蓋之該些銲線且電連接該些銲線。
  2. 如請求項1所述之結構，進一步包含一圖案化導電層，電連接該些銲線之第二端與該主動表面。
  3. 如請求項2所述之結構，進一步包含複數個第二外部連接端子，與該圖案化導電層電連接。
  4. 如請求項2所述之結構，其中該圖案化導電層進一步包含複數個導電跡線，分別電連接該些銲線之第二端與該主動表面，其中與該些導電跡線之其中之一電連接之該銲線數目大於或等於一。
  5. 如請求項4所述之結構，其中該圖案化導電層進一步包含複數個導電銲墊，該些導電銲墊分別設置於該些導電跡線上，並與該些銲線之第二端連接。
  6. 如請求項1所述之結構，進一步包含至少一凹陷結構，形成於該封膠體上，用以容納該些第一外部連接端子。
  7. 一種半導體堆疊結構，該堆疊結構包含兩個以上的半導體 封裝結構相互堆疊，其中該半導體封裝結構包含：一晶粒，該晶粒包含一主動表面及一相對於該主動表面之背表面；複數條銲線，各該銲線之一第一端連接該晶粒之該背表面，相對於該第一端之一第二端與該主動表面電連接；一封膠體，覆蓋該晶粒的該背表面及該些銲線，其中各該銲線之局部未被覆蓋；以及複數個第一外部連接端子，設置於該封膠體之上，並分別包覆未被該封膠體覆蓋之該些銲線且電連接該些銲線；其中該些半導體封裝結構透過該些第一外部連接端子相互電連接，以形成該半導體堆疊結構。
  8. 如請求項7所述之堆疊結構，其中該半導體封裝結構進一步包含一圖案化導電層，電連接該些銲線之第二端與該主動表面。
  9. 如請求項8所述之堆疊結構，其中該半導體封裝結構進一步包含複數個第二外部連接端子，與該圖案化導電層電連接。
  10. 如請求項8所述之堆疊結構，其中該圖案化導電層進一步包含複數個導電跡線，分別電連接該些銲線之第二端與該主動表面，其中與該些導電跡線之其中之一電連接之該銲線數目大於或等於一。
  11. 如請求項7所述之堆疊結構，其中該半導體封裝結構進一步包含至少一凹陷結構形成於該封膠體上，用以容納該些 第一外部連接端子。
  12. 一種製造一半導體封裝結構的方法，該方法包含：提供一承載板；設置一晶粒於該承載板上，該晶粒包含一主動表面以及相對該主動表面之一背表面，其中該主動表面與該承載板相接；形成複數條銲線，各該銲線具有一第一端及相對該第一端之一第二端，該第一端連接該晶粒之該背表面，該第二端連接該承載板；形成一封膠體，覆蓋該晶粒及該些銲線，其中各該銲線之局部未被覆蓋；移除該承載板；電連接該些銲線之第二端與該晶粒之該主動表面；以及形成複數個第一外部連接端子於該封膠體之上，該些第一外部連接端子分別包覆未被該封膠體覆蓋之該些銲線且與該些銲線電連接。
  13. 如請求項12所述之方法，其中電連接該些銲線之第二端與該晶粒之該主動表面包含形成一圖案化導電層。
  14. 如請求項13所述之方法，其中該圖案化導電層包含複數個導電跡線及複數個導電銲墊，且形成該圖案化導電層的步驟更包含：於提供該承載板的步驟之後，進一步設置一具有複數個凸起部之金屬層於該承載板上，使該晶粒之該主動表面固接於該金屬層上，其中該些銲線之第二端與該些凸起部 連接；以及於移除該承載板的步驟之後，圖案化該金屬層以形成該些導電跡線並使該些凸起部形成該些導電銲墊，其中該些導電銲墊分別設置於該些導電跡線上。
  15. 如請求項13所述之方法，進一步包含形成複數個第二外部連接端子，分別與該圖案化導電層電連接。
  16. 如請求項12所述之方法，進一步包含於該封膠體之上形成至少一凹陷結構，用以容納該些第一外部連接端子。
  17. 如請求項16所述之方法，進一步包含於該至少一凹陷結構中形成一球下金屬層(under bump metallization，UBM)，該球下金屬層位於該些第一外部連接端子與該封膠體之間。
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