CN106876358A - 电子元件及其制造方法 - Google Patents

电子元件及其制造方法 Download PDF

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CN106876358A
CN106876358A CN201510919622.9A CN201510919622A CN106876358A CN 106876358 A CN106876358 A CN 106876358A CN 201510919622 A CN201510919622 A CN 201510919622A CN 106876358 A CN106876358 A CN 106876358A
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tie point
connector
conductive
pipe core
electronic component
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杨顺迪
波姆皮奥·V·乌马里
周安乐
梁志豪
林根伟
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Yasuyo Co Ltd
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Yasuyo Co Ltd
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Priority to US15/368,653 priority patent/US20170170103A1/en
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Abstract

一种电子元件,包括导电连接层及置于导电连接层上的互相间隔的器件管芯和连接件;器件管芯在与导电连接层接触的一面上具有与导电连接层电性连接的第一连接点,并在其另一面上具有第二连接点;连接件在与导电连接层接触的一面上具有与导电连接层电性连接的第三连接点,并在其另一面上具有第四连接点;第二连接点、第四连接点配置为提供电子元件的对外连接。本发明还提供一种电子元件的制造方法。

Description

电子元件及其制造方法
技术领域
本发明涉及一种电子元件与其制造方法。具体地,本发明涉及一种无引线框架的电子元件及制造该无引线电子元件的方法。
背景技术
电子元件通常通过封装技术而与引线框架结合在一起。在封装中,将晶圆制造中所形成的器件管芯与引线框架进行连接,并将器件管芯与引线框架通过模封材料而固封在一起,形成最终的具有固定结构的电子元件。其中,引线框架中配置部分连接部件与器件管芯中相应的触点通过引线键合或其他接合方式连接在一起,并通过引线框架的相应部分与外界接触。
在电子元件的一般制造过程中,引线框架的配置一般需要耗费大量的时间、人力等,成为电子元件制造成本中的重要节点。
发明内容
基于此,有必要提供一种节省成本与工序的电子元件,以及相应的电子元件的制造方法。
一种电子元件,包括通过在基板上涂覆导电材料形成的导电连接层及置于所述导电连接层上的互相间隔的器件管芯和连接件;所述器件管芯在与所述导电连接层接触的一面上具有与导电连接层电性连接的第一连接点,并在其另一面上具有第二连接点;所述连接件在与所述导电连接层接触的一面上具有与导电连接层电性连接的第三连接点,并在其另一面上具有第四连接点;所述第二连接点、第四连接点配置为提供所述电子元件的对外连接。
一种制造电子元件的方法,包括:
在基板上涂敷导电层,以形成导电连接层;
在所述导电连接层上设置器件管芯与连接件,所述器件管芯与所述连接件设置为互相间隔;所述器件管芯和所述连接件在与所述导电连接层接触的一面上各具有内连接点,所述器件管芯和所述连接件各在相异于与所述导电连接层接触的其他的面上具有外连接点;
固封所述导电连接层、所述器件管芯与所述连接件,并暴露所述器件管芯与所述连接件的外连接点;
剥离所述基板。
在本发明的实施方式中,导电连接层是通过在基板上涂敷导电层而形成的。从而在该电子元件的形成过程中,将不会涉及到引线框架的使用或者是引线键合的工序,直接由涂敷导电连接层、装配器件管芯、装配连接件、模封材料固封即可形成电子元件。由于节省了引线框架的制造与使用过程,电子元件的制造成本、工序时间等,均可以得到节省。
附图说明
以下将结合附图对于本发明的实施方式进行进一步描述,其中:
图1A、图1B为一种实施方式的电子元件的立体视图;
图2为一种实施方式的制造电子元件的方法的流程图;
图3A-图3I为一种实施方式中根据图2所示的制造电子元件的方法在各步骤时所得结构的部分剖面示意图;
图4为另一实施方式的制造电子元件的方法的流程图;
图5A-图5J为一种实施方式中根据图4所示的制造电子元件的方法在各步骤时所得结构的部分剖面示意图;
图6A、图6B为一种实施方式的电子元件的立体视图。
具体实施方式
请参考图1A-1B,其为本发明一种实施方式的电子元件的结构的立体视图。该电子元件100包括导电连接层102、器件管芯104、连接件106等。
如图1A所示,器件管芯104、连接件106设置在导电连接层102上,并且彼此之间设有间隔。器件管芯104在面对导电连接层102的一面上设有第一连接点(图中由于器件管芯104的遮挡而未示出),用以实现器件管芯104与导电连接层102的电性连接;器件管芯104在另一面上设有第二连接点108。类似地,连接件106在其面对导电连接层102的一面上设有第三连接点(图中未示出),用以实现连接件106与导电连接层102的电性连接;连接件106在其另一面上设有第四连接点110。
在可选的实施方式中,第二连接点108、第四连接点110上分别被施加了相应的镀层,用以保护连接点不受到氧化等外界环境的影响。
可以理解的是,通过第二连接点108、第四连接点110,本发明实施方式的电子元件100可以提供对外的电性连接。在可选的实施方式中,第一连接点、第二连接点108分别位于器件管芯104的相反两侧上;第三连接点、第四连接点110亦分别位于连接件106的相反两侧上。
在一种实施方式中,第二连接点108、第四连接点110可以被设置为位于同一平面上,以便后续当电子元件100被装配到例如印刷电路板(Printed Circuit Board,PCB)上时,可以方便地形成与外界的连接。
结合参考图1B所示的,在器件管芯104、连接件106装配到导电连接层102之后,可以利用模封材料112将装配件固封起来,从而形成完整的电子元件100。在进一步可选的实施方式中,电子元件100在装配了器件管芯104、连接件106的导电连接层102的相反的一面上,还可以包括非导电层(图未示),从而形成对导电连接层102的保护。
根据一种可选的实施方式,连接件106由导电材料制成,例如由铜(Cu)制成。从而,器件管芯104上的第一连接点通过导电连接层102、连接件106而被电性地引导到第四连接点110上。
在本发明的实施方式中,导电连接层102是通过在热剥离膜上涂敷导电层而形成的。从而在该电子元件100的形成过程中,将不会涉及到引线框架的使用或者是引线键合的工序,直接由涂敷导电连接层102、装配器件管芯104、装配连接件106、模封材料112固封即可形成电子元件100。由于节省了引线框架的制造与使用过程,电子元件100的制造成本、工序时间等,均可以得到节省。
如图2所示的,其为一种实施方式中制造电子元件的方法的流程图。结合参考图3A至图3I所示的,其为一种实施方式中制造电子元件的方法在各步骤所得的结构的剖面视图。以下将参考图3中所示的各结构而对该制造电子元件的方法的实施方式进行说明。
步骤202,提供一个基板。如图3A所示的,该基板302可以实施为一种热剥离膜,例如可以是200℃的热剥离膜。
步骤204,在基板上涂敷导电层,以形成导电连接层。
具体地,如图3B所示,在基板302上通过分配技术(Dispense)或者丝网印刷术(Screen-Printing)来将导电胶304(Conductive Glue)涂敷在基板302上。在涂敷过程中,应当在欲将装配器件管芯与连接件的位置以及欲实现电性连接的位置上涂敷导电胶304,而将其他不需要的位置留出。
步骤206,在导电连接层上设置器件管芯与连接件。
具体地,如图3C及图3D所示的,在所形成的导电连接层304上,分别装配器件管芯306与连接件308。其中,器件管芯306与连接件308可以相对应地安装在导电连接层304上相对应的涂敷位置处。器件管芯306与连接件308之间可以设置为互相间隔。其中,器件管芯306和连接件308在相对于导电连接层304的一面上设有内连接点,用以实现与导电连接层304的电性连接;器件管芯306与连接件308在相反于其连接到导电连接层304的一面上分别设有外连接点310、312,用以实现与外部的连接。可以理解的是,外连接点310、312提供了最终形成的电子元件的对外电连接。
在可选的一种实施方式中,器件管芯306及/或连接件308的内连接点与外连接点310、312分别位于各自相应的相反两侧的面上。然而,在其他可选的实施方式中,内连接点与外连接点可以设置为具有其他的相对位置关系。
在可选的一种实施方式中,在器件管芯306、连接件308被安装到导电连接层304上时,将其外连接点310、312配置为位于同一平面上。然而,在其他可选的实施方式中,也可以将器件管芯306的外连接点310与连接件308的外连接点312配置在其他不同的相对位置上。
步骤208,固封导电连接层、器件管芯与连接件。
结合参考图3E,在器件管芯306、连接件308被安装到导电连接层304上之后,通过模封材料314将所形成的装配件固封起来,从而形成模封体316。通常地,通过将液态的模封材料314流入模具中而将装配件包固成形,而形成模封体316。在一种示例的实施方式中,由于在步骤202中使用了200℃的热剥离膜作为基板302,在此进行固封所用的模封材料314处于液态时的温度最好不要超过200℃,以免引起热剥离膜的剥离。例如,可以通过120℃的液体成型工艺或者170℃的转送成型工艺来形成模封体316。
步骤210,研磨固封所得的模封体,以暴露外连接点。
结合参考图3F,在步骤208所得到的模封体316上,可能出现的是器件管芯306、连接件308的外连接点310、312被模封材料314淹没而未能暴露的情况。在此情形下,有必要通过一定的工艺手段使得外连接点310、312暴露出来,才能够提供电子元件对外的连接。在该实施方式中,采用的是对模封体316进行研磨的方式,将遮掩的模封材料314去除,从而使外连接点310、312暴露。可以理解的是,如果模封材料314没有遮住外连接点310、312,从而在本发明中并不需要进行模封材料314的去除以暴露外连接点310、312;并且,去除模封材料314的过程还可以使用其他可能的方式,其不应限于本实施方式中所述的研磨。
步骤212,在外连接点上施加镀层。
如图3G所示的,在可选的实施方式中,连接件308可以是由铜(Cu)制成,外连接点310、312可以是由锡(Sn)、铜(Cu)等材料形成。为在后续加工、使用电子元件的过程中让外连接点310、312得到必要的保护,例如免受腐蚀、氧化等外部环境的影响,可以在外连接点310、312上镀上适当的保护层318。
应当说明的是,一种可能的情况上,该器件管芯306的外连接点310在进行晶圆制造时或进行本发明的电子元件的制造之前即已覆盖有前述适当的保护层,以使外连接点310免受本发明中各步骤工艺的影响;从而,在本发明中将不必需要通过步骤212所述的过程来施加该镀层。对于连接件308的外连接点312,也可以具有相似的情况。此外,在图3G中,保护层318被进行了一定程度的放大,以便清楚地显示。
步骤214,分离模封体。
如图3H所示的,当在一次工序中形成了多于一个电子元件(每个电子元件包括预定数量的导电连接层304、器件管芯306与连接件308)时,经过固封形成的模封体316中将包括最终用于形成单个电子元件的多个相应的个体。通过例如锯切、激光等方式,可以将模封体316沿着预定的划道分割成相应的电子元件300。在该示例的实施方式中,通过锯切、激光等方式的分割应当在导电连接件304与基板302的交界处停止。可以理解的是,在其他可选的实施方式中,也可以将模封体316连同基板302完全切开。
步骤216,剥离基板。
请参考图3I,在基板302如前述的实施方式中采用200℃的热剥离膜时,通过加热而将热剥离膜与电子元件300分离开来。
在进一步的可选的实施方式中,该制造电子元件的方法还可以包括在步骤216进行了剥离之后所得的电子元件300的背面、即装配了器件管芯306、连接件308的导电连接件304的相反的一面上,设置相应的保护层(图未示)的步骤,该保护层可以任何可能的方式进行设置。
如图4所示,其为本发明另一实施方式的制造电子元件的流程图。该方法的实施方式中大部分过程与图2所示的过程类似,在此不重复描述与图2中相似的过程,仅说明其中具有实质性异同的步骤。此外,图5A至图5J中也示出了图4中各步骤所得结构的剖面视图,在此亦将仅描述与图3A-图3I中具有实质性异同的部分。
在图4所示的实施方式中,在步骤402提供基板之后,步骤404,在基板上设置非导电层。
具体地,如图5B所示的,在可以是200℃热剥离膜的基板502上,设置非导电层504。在一种可选的实施方式中,该非导电层504可以是非导电性的芯片粘接膜(Die Attach Film,DAF)。
在步骤404之后,步骤406将在非导电层上涂敷导电层,以形成导电连接层。具体地,如图5C所示的,在非导电层504上与图2中的步骤204类似地涂敷导电层,以形成导电连接层506。形成导电连接层506之后,非导电层504位于导电连接层506与基板502之间。
本实施方式在其后的步骤408至418将与图2中的步骤206至步骤216类似,在此将不予赘述。各步骤中所得到的结构如图5D至图5J中所示,其与图3C至图3I中的结构具有类似的特征,例如器件管芯508及其外连接点512、连接件510及其外连接点514、模封材料516、模封体518、镀层520、电子元件500等,在此不予赘述。
如图6A所示的,其为图4、图5中的实施方式所形成的电子元件600的立体视图。可以看到,该电子元件600包括导电连接层602、器件管芯604及其外连接点608、连接件606及其外连接点610等。进一步地,如图6B所示的,在该电子元件600的背面,进一步包括了非导电层612,从而导电连接层602是位于非导电层612与器件管芯604、连接件606之间。通过非导电层612的设置,使得导电连接层602在电子元件600被使用的过程中也得到相应的保护,从而使得电子元件600可以更为可靠。
在本发明的各实施方式中,导电连接层304、506是通过在热剥离膜上涂敷导电层而形成的。从而在该电子元件300、500的形成过程中,将不会涉及到引线框架的使用或者是引线键合的工序,直接由涂敷导电连接层、装配器件管芯、装配连接件、模封材料固封即可形成电子元件。由于节省了引线框架的制造与使用过程,电子元件的制造成本、工序时间等,均可以得到节省。
在此参考了特定的所示的例子对于各种示例的实施方式进行了描述。所述示例的例子被选择为辅助本领域的技术人员来形成对于各实施方式的清晰理解并得实施。然而,可以构建为包括一个或多个实施方式的系统、结构和器件的范围,以及根据一个或多个实施方式实施的方法的范围,并不为所展示的示例性例子所限制。相反地,所属技术领域的技术人员基于本说明书可以理解:可以根据各实施方式来实施出很多其他的配置、结构和方法。
应当理解的是,就于本发明在前描述中所使用的各种位置指示来说,例如顶、底、上、下,彼等指示仅是参考了相应的附图而给出,并且当器件的朝向在制造或工作中发生变化时,可以代替地具有其他位置关系。如上所述,那些位置关系只是为清楚起见而描述,并非限制。
本说明的前述描述是参考特定的实施方式和特定的附图,但本发明不应当限制于此,而应当由权利要求书所给出。所描述的各附图都是示例性的而非限制性的。在附图中,为示例的目的,各元件的尺寸可能被放大,且可能没有绘制为特定的比例尺。本说明也应当包括各元件、工作方式在容限和属性上的不连续的变换。还应当包括本发明的各种弱化实施。
本说明及权利要求书中所使用的词汇“包括”并不排除其他元件或步骤。除非特别指出,在使用单数形式如“一”、“一个”指代确定或不确定的元件时,应当包括该元件的复数。从而,词汇“包括”不应当被理解为限于在其后所列出的条目,不应当理解为不包括其他元件或步骤;描述“器件包括项目A和B”的范围不应当限制为只包括元件A和B的器件。该描述表示,就于本说明而言,只有器件的元件A和B是相关的。
对于所属领域的技术人员而言,在不背离本发明的权利要求的范畴内可以作出多种具体变化。

Claims (15)

1.一种电子元件,其特征在于:包括通过在基板上涂覆导电材料形成的导电连接层及置于所述导电连接层上的互相间隔的器件管芯和连接件;所述器件管芯在与所述导电连接层接触的一面上具有与导电连接层电性连接的第一连接点,并在其另一面上具有第二连接点;所述连接件在与所述导电连接层接触的一面上具有与导电连接层电性连接的第三连接点,并在其另一面上具有第四连接点;所述第二连接点、第四连接点配置为提供所述电子元件的对外连接。
2.根据权利要求1所述的电子元件,其特征在于:进一步包括施加在所述第二连接点与所述第四连接点上的镀层。
3.根据权利要求1所述的电子元件,其特征在于:所述基板为热剥离膜。
4.根据权利要求1所述的电子元件,其特征在于:所述连接件的材料为铜。
5.根据权利要求1所述的电子元件,其特征在于:进一步包括位于装配了所述器件管芯和连接件的所述导电连接层的相反一侧上的非导电层。
6.根据权利要求1所述的电子元件,其特征在于:所述第一连接点与所述第二连接点分别位于所述器件管芯的相反两侧的面上。
7.根据权利要求1所述的电子元件,其特征在于:所述第三连接点与所述第四连接点分别位于所述连接件的相反两侧的面上。
8.根据权利要求1所述的电子元件,其特征在于:所述第二连接点与所述第四连接点配置为位于同一平面上。
9.一种制造电子元件的方法,其特征在于,包括:
在基板上涂敷导电层,以形成导电连接层;
在所述导电连接层上设置器件管芯与连接件,所述器件管芯与所述连接件设置为互相间隔;所述器件管芯和所述连接件在与所述导电连接层接触的一面上各具有内连接点,所述器件管芯和所述连接件各在相异于与所述导电连接层接触的其他的面上具有外连接点;
固封所述导电连接层、所述器件管芯与所述连接件,并暴露所述器件管芯与所述连接件的外连接点;
剥离所述基板。
10.根据权利要求9所述的制造电子元件的方法,其特征在于:所述在基板上涂敷导电层的步骤之前进一步包括:在基板上设置非导电层,以使所述非导电层位于所述导电层与所述基板之间。
11.根据权利要求9所述的制造电子元件的方法,其特征在于:所述暴露器件管芯与所述连接件的外连接点包括:对固封所述导电连接层、所述器件管芯与所述连接件所得的模封体进行研磨,以暴露器件管芯与所述连接件的外连接点。
12.根据权利要求9所述的制造电子元件的方法,其特征在于:在暴露所述器件管芯与所述连接件的外连接点之后进一步包括:在所述器件管芯与所述连接件的外连接点上施加镀层。
13.根据权利要求9所述的制造电子元件的方法,其特征在于:所述器件管芯及/或所述连接件的内连接点与所述外连接点分别位于各自相应的相反两侧的面上。
14.根据权利要求9所述的制造电子元件的方法,其特征在于:所述在所述导电连接层上设置器件管芯与连接件包括:将所述器件管芯与所述连接件的外连接点配置为位于同一平面上。
15.根据权利要求9所述的制造电子元件的方法,其特征在于:所述基板为热剥离膜。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1491439A (zh) * 2001-11-22 2004-04-21 ���ṫ˾ 多芯片电路模块及其制造方法
CN1585114A (zh) * 2003-08-22 2005-02-23 全懋精密科技股份有限公司 有电性连接垫金属保护层的半导体封装基板结构及其制法
US20130288428A1 (en) * 2011-09-28 2013-10-31 Nitto Denko Corporation Method for producing semiconductor device
CN103730434A (zh) * 2012-10-11 2014-04-16 台湾积体电路制造股份有限公司 Pop结构及其形成方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI495066B (zh) * 2012-08-31 2015-08-01 Chipmos Technologies Inc 晶圓級封裝結構及其製造方法
KR101419597B1 (ko) * 2012-11-06 2014-07-14 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US20150187608A1 (en) * 2013-12-26 2015-07-02 Sanka Ganesan Die package architecture with embedded die and simplified redistribution layer
US9659844B2 (en) * 2015-08-31 2017-05-23 Texas Instruments Incorporated Semiconductor die substrate with integral heat sink

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1491439A (zh) * 2001-11-22 2004-04-21 ���ṫ˾ 多芯片电路模块及其制造方法
CN1585114A (zh) * 2003-08-22 2005-02-23 全懋精密科技股份有限公司 有电性连接垫金属保护层的半导体封装基板结构及其制法
US20130288428A1 (en) * 2011-09-28 2013-10-31 Nitto Denko Corporation Method for producing semiconductor device
CN103730434A (zh) * 2012-10-11 2014-04-16 台湾积体电路制造股份有限公司 Pop结构及其形成方法

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Application publication date: 20170620