JP2004193557A - 半導体デバイス - Google Patents
半導体デバイス Download PDFInfo
- Publication number
- JP2004193557A JP2004193557A JP2003317885A JP2003317885A JP2004193557A JP 2004193557 A JP2004193557 A JP 2004193557A JP 2003317885 A JP2003317885 A JP 2003317885A JP 2003317885 A JP2003317885 A JP 2003317885A JP 2004193557 A JP2004193557 A JP 2004193557A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- semiconductor
- die
- via hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16147—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/81141—Guiding structures both on and outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06589—Thermal management, e.g. cooling
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】半導体デバイス(1)、マイクロ電気機械システムパッケージ及びこれを作る方法は、垂直IC梱包のための高性能バイアを利用する。デバイス/パッケージの半導体ダイス(2)は基体(3)を有し、その前面には集積回路(4)が形成される。金属結合パッド(5)は基体の前面上に位置し、集積回路に電気的に接続される。はんだ隆起部(11)は金属結合パッド上に位置する。導電性のバイア(10)は基体を通って金属結合パッドから基体の裏面へ延び、そこで、バイアはバイア穴の側壁を形成する。複数の基体が互いに重ねられ、1つの基体のはんだ隆起部の外端は隣接する基体のバイア穴に嵌合する。再流れはんだ付け中、溶融はんだ隆起部の表面張力が基体を自動整合させる。
【選択図】 図1
Description
従来の垂直梱包技術はかなり避けたい又は抵抗を受ける組立て自動化及び正規のウエファー製造環境への組み込みを有する。従って、このような従来技術の製品は極めて高価であり、質/一貫性が疑わしく、メモリーチップの場合は、次世代チップにより能力が頻繁に追い越されてしまう。新たなパーソナル電子器具は消費者により要求される機能性の一層大なる配列を可能にするために常にメモリーを必要とする。これらについてのいくつかの例は、携帯電話、カメラ、パーソナルデジタル補助物及びこれらの集合を含む新たな未来の器具である。今は、メモリーチップの梱包密度は、デバイスがもはやその有効な挙動を行わないほどに小さく作られる当業界で既知のその限界に達している。
以下の詳細な説明において、同様の符号及び記号は異なる図面における同一の又は対応する又は類似の素子を示すものとして使用することができる。更に、以下の詳細な説明において、例示的な寸法/モデル/値/範囲が与えられるが、本発明はこれらに限定されない。周知のパワー接続及び他の周知の素子は、図示及び説明を簡略化し、本発明を不明瞭にしないために、図には示さなかった。
2 半導体ダイス
3 基体
4 集積回路
5 金属結合パッド
6 側壁
10 バイア
11 メニスカス
12 はんだ隆起部
14 キャリヤ
Claims (10)
- 半導体デバイスにおいて、
前面上に形成された集積回路を備えた基体を有する半導体ダイスと;
その前面上で上記基体の上に位置し、上記集積回路に電気的に接続された金属結合パッドと;
上記金属結合パッド上のはんだ隆起部と;
上記金属結合パッドに電気的に接続された電気的に導電性のバイアであって、上記基体を通って、当該金属結合パッドから、上記バイアがバイア穴の側壁を形成するような当該基体の裏面まで延びるバイアと;
を有することを特徴とする半導体デバイス。 - 上記基体の裏面のバイア穴の開口の寸法がはんだ隆起部上のメニスカスの直径の程度であることを特徴とする請求項1に記載の半導体デバイス。
- 上記はんだ隆起部及びバイア穴が上記基体の面に垂直な軸線に沿って互いに整合していることを特徴とする請求項1又は2に記載の半導体デバイス。
- 上記半導体ダイスがダイナミックランダム・アクセス・メモリー集積回路チップであることを特徴とする請求項1ないし3のいずれかに記載の半導体デバイス。
- 上記半導体ダイスの前面が上記金属結合剤パッド及び上記はんだ隆起部のまわりで不動態化されることを特徴とする請求項1ないし4のいずれかに記載の半導体デバイス。
- 上記金属結合パッドから上記基体を通って延びる上記バイアが逆ピラミッドの形をしていることを特徴とする請求項1ないし5のいずれかに記載の半導体デバイス。
- 上記バイア穴の側壁が上記基体の異方性エッチング特性面である当該基体の面に対してある角度で延びることを特徴とする請求項1ないし6のいずれかに記載の半導体デバイス。
- 複数の上記半導体ダイスがスタックとして互いに重ねられ、上記スタックの1つのダイスの金属結合パッドが当該スタックの隣接するダイスのバイア穴に対向して位置し、1つのダイスの金属結合パッド上のはんだ隆起部が隣接するバイアにはんだ付けされることを特徴とする請求項1ないし7のいずれかに記載の半導体デバイス。
- 上記隣接するダイスの基体の裏面のバイア穴の開口の寸法が1つのダイスの金属結合パッド上のはんだ隆起部のメニスカスの直径程度であり、上記1つのダイス上のはんだ隆起部の外端が隣接するダイスのバイア穴内へ延びることを特徴とする請求項1ないし8のいずれかに記載の半導体デバイス。
- 重ねられた上記半導体ダイスの底部の半導体ダイスが、上記重ねられた半導体ダイスの底部の半導体ダイスの金属結合パッド及びその上のはんだ隆起部により、キャリヤにフリップ・チップ装着されることを特徴とする請求項1ないし9のいずれかに記載の半導体デバイス。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/317,680 US6936913B2 (en) | 2002-12-11 | 2002-12-11 | High performance vias for vertical IC packaging |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004193557A true JP2004193557A (ja) | 2004-07-08 |
JP3845403B2 JP3845403B2 (ja) | 2006-11-15 |
Family
ID=32325947
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003317885A Expired - Fee Related JP3845403B2 (ja) | 2002-12-11 | 2003-09-10 | 半導体デバイス |
Country Status (4)
Country | Link |
---|---|
US (1) | US6936913B2 (ja) |
EP (1) | EP1429388B1 (ja) |
JP (1) | JP3845403B2 (ja) |
DE (1) | DE60314969T2 (ja) |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6841883B1 (en) * | 2003-03-31 | 2005-01-11 | Micron Technology, Inc. | Multi-dice chip scale semiconductor components and wafer level methods of fabrication |
JP4353845B2 (ja) * | 2004-03-31 | 2009-10-28 | 富士通株式会社 | 半導体装置の製造方法 |
TWI278090B (en) * | 2004-10-21 | 2007-04-01 | Int Rectifier Corp | Solderable top metal for SiC device |
US7812441B2 (en) | 2004-10-21 | 2010-10-12 | Siliconix Technology C.V. | Schottky diode with improved surge capability |
US7834376B2 (en) | 2005-03-04 | 2010-11-16 | Siliconix Technology C. V. | Power semiconductor switch |
US9419092B2 (en) * | 2005-03-04 | 2016-08-16 | Vishay-Siliconix | Termination for SiC trench devices |
US7371676B2 (en) * | 2005-04-08 | 2008-05-13 | Micron Technology, Inc. | Method for fabricating semiconductor components with through wire interconnects |
US7393770B2 (en) * | 2005-05-19 | 2008-07-01 | Micron Technology, Inc. | Backside method for fabricating semiconductor components with conductive interconnects |
US7589406B2 (en) * | 2005-06-27 | 2009-09-15 | Micron Technology, Inc. | Stacked semiconductor component |
US20070070311A1 (en) * | 2005-09-23 | 2007-03-29 | Asml Netherlands B.V. | Contacts to microdevices |
US8368165B2 (en) | 2005-10-20 | 2013-02-05 | Siliconix Technology C. V. | Silicon carbide Schottky diode |
US7307348B2 (en) | 2005-12-07 | 2007-12-11 | Micron Technology, Inc. | Semiconductor components having through wire interconnects (TWI) |
US7990727B1 (en) * | 2006-04-03 | 2011-08-02 | Aprolase Development Co., Llc | Ball grid array stack |
US7659612B2 (en) | 2006-04-24 | 2010-02-09 | Micron Technology, Inc. | Semiconductor components having encapsulated through wire interconnects (TWI) |
US7569920B2 (en) * | 2006-05-10 | 2009-08-04 | Infineon Technologies Ag | Electronic component having at least one vertical semiconductor power transistor |
KR101193453B1 (ko) | 2006-07-31 | 2012-10-24 | 비쉐이-실리코닉스 | 실리콘 카바이드 쇼트키 다이오드를 위한 몰리브덴 장벽 금속 및 제조방법 |
US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
TWI351751B (en) * | 2007-06-22 | 2011-11-01 | Ind Tech Res Inst | Self-aligned wafer or chip structure, self-aligned |
EP2075828A1 (en) * | 2007-12-27 | 2009-07-01 | Interuniversitair Microelektronica Centrum (IMEC) | Semiconductor device and a method for aligining and bonding a first and second element for the fabrication of a semiconductor device |
US7973416B2 (en) * | 2008-05-12 | 2011-07-05 | Texas Instruments Incorporated | Thru silicon enabled die stacking scheme |
JP4601686B2 (ja) * | 2008-06-17 | 2010-12-22 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
US7846772B2 (en) * | 2008-06-23 | 2010-12-07 | Headway Technologies, Inc. | Layered chip package and method of manufacturing same |
US7767494B2 (en) * | 2008-06-30 | 2010-08-03 | Headway Technologies, Inc. | Method of manufacturing layered chip package |
US7868442B2 (en) * | 2008-06-30 | 2011-01-11 | Headway Technologies, Inc. | Layered chip package and method of manufacturing same |
US7872332B2 (en) | 2008-09-11 | 2011-01-18 | Micron Technology, Inc. | Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods |
US8049319B2 (en) * | 2008-10-24 | 2011-11-01 | Electronics And Telecommunications Research Institute | Ultra wideband system-on-package |
EP2273545B1 (en) * | 2009-07-08 | 2016-08-31 | Imec | Method for insertion bonding and kit of parts for use in said method |
US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
US8587126B2 (en) * | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US8736066B2 (en) | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
US11037874B2 (en) * | 2018-10-29 | 2021-06-15 | Intel Corporation | Plane-less voltage reference interconnects |
CN110400787B (zh) * | 2019-06-26 | 2023-04-28 | 中国电子科技集团公司第三十八研究所 | 一种硅基垂直互联结构及制备方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3761782A (en) * | 1971-05-19 | 1973-09-25 | Signetics Corp | Semiconductor structure, assembly and method |
US4807021A (en) * | 1986-03-10 | 1989-02-21 | Kabushiki Kaisha Toshiba | Semiconductor device having stacking structure |
US5229647A (en) * | 1991-03-27 | 1993-07-20 | Micron Technology, Inc. | High density data storage using stacked wafers |
WO1996013062A1 (en) | 1994-10-19 | 1996-05-02 | Ceram Incorporated | Apparatus and method of manufacturing stacked wafer array |
US6219254B1 (en) * | 1999-04-05 | 2001-04-17 | Trw Inc. | Chip-to-board connection assembly and method therefor |
JP3736607B2 (ja) * | 2000-01-21 | 2006-01-18 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP3951091B2 (ja) * | 2000-08-04 | 2007-08-01 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US6674161B1 (en) * | 2000-10-03 | 2004-01-06 | Rambus Inc. | Semiconductor stacked die devices |
-
2002
- 2002-12-11 US US10/317,680 patent/US6936913B2/en not_active Expired - Lifetime
-
2003
- 2003-08-04 EP EP03017796A patent/EP1429388B1/en not_active Expired - Lifetime
- 2003-08-04 DE DE60314969T patent/DE60314969T2/de not_active Expired - Lifetime
- 2003-09-10 JP JP2003317885A patent/JP3845403B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP1429388B1 (en) | 2007-07-18 |
DE60314969D1 (de) | 2007-08-30 |
JP3845403B2 (ja) | 2006-11-15 |
EP1429388A1 (en) | 2004-06-16 |
DE60314969T2 (de) | 2008-04-10 |
US6936913B2 (en) | 2005-08-30 |
US20040113264A1 (en) | 2004-06-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3845403B2 (ja) | 半導体デバイス | |
CN110970407B (zh) | 集成电路封装件和方法 | |
US11791301B2 (en) | Chip package structure | |
US6822316B1 (en) | Integrated circuit with improved interconnect structure and process for making same | |
KR101478875B1 (ko) | 반도체 다이를 패키징하는 패키지 온 패키지 장치 및 방법 | |
US8097955B2 (en) | Interconnect structures and methods | |
TWI695432B (zh) | 封裝及其形成方法 | |
KR101157726B1 (ko) | 극박 적층 칩 패키징 | |
US20060019467A1 (en) | Methods of fabricating integrated circuit chips for multi-chip packaging and wafers and chips formed thereby | |
US20110237004A1 (en) | Chipstack package and manufacturing method thereof | |
US20030227094A1 (en) | Wafer level packaging of micro electromechanical device | |
KR101107858B1 (ko) | 반도체 기판을 위한 도전 필러 구조 및 그 제조 방법 | |
JP2009010312A (ja) | スタックパッケージ及びその製造方法 | |
JP2010245536A (ja) | 半導体装置、及びその製造方法 | |
CN207338360U (zh) | 半导体晶圆 | |
JP2008182224A (ja) | スタック・パッケージ及びスタック・パッケージの製造方法 | |
WO2002101831A1 (fr) | Dispositif a semi-conducteur et son procede de fabrication | |
WO2015184153A1 (en) | Low cte component with wire bond interconnects | |
CN112447642A (zh) | 半导体封装及其制造方法 | |
US20040124513A1 (en) | High-density multichip module package | |
US10249585B2 (en) | Stackable semiconductor package and manufacturing method thereof | |
US8049323B2 (en) | Chip holder with wafer level redistribution layer | |
TW202114089A (zh) | 封裝結構及其製作方法 | |
KR100959606B1 (ko) | 스택 패키지 및 그의 제조 방법 | |
KR101013556B1 (ko) | 스택 패키지의 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20051222 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060105 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20060404 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20060407 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060630 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20060721 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20060818 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100825 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110825 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110825 Year of fee payment: 5 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110825 Year of fee payment: 5 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110825 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120825 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130825 Year of fee payment: 7 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |