JP2008159956A - 電子部品内蔵基板 - Google Patents
電子部品内蔵基板 Download PDFInfo
- Publication number
- JP2008159956A JP2008159956A JP2006348755A JP2006348755A JP2008159956A JP 2008159956 A JP2008159956 A JP 2008159956A JP 2006348755 A JP2006348755 A JP 2006348755A JP 2006348755 A JP2006348755 A JP 2006348755A JP 2008159956 A JP2008159956 A JP 2008159956A
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- Prior art keywords
- electronic component
- substrate
- wiring board
- semiconductor element
- layer side
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- 239000000758 substrate Substances 0.000 title claims abstract description 132
- 239000011347 resin Substances 0.000 claims abstract description 44
- 229920005989 resin Polymers 0.000 claims abstract description 44
- 229910000679 solder Inorganic materials 0.000 claims abstract description 34
- 238000007789 sealing Methods 0.000 claims abstract description 31
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 239000011162 core material Substances 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 14
- 239000004065 semiconductor Substances 0.000 description 88
- 238000000034 method Methods 0.000 description 17
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000007788 liquid Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Images
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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Abstract
【解決手段】一対の配線基板10,20間に、複数段に電子部品30,60が積み重ねて搭載された電子部品内蔵基板100であって、一方の配線基板10と他方の配線基板20同士がはんだボール40を介して電気的に接続され、一方の配線基板10に第1の電子部品30が搭載されると共に、第1の電子部品30の上に第2の電子部品60が搭載され、他方の配線基板20には、第2の電子部品60を収容する開口部24が設けられ、第2の電子部品60は、開口部24内に収容して搭載されると共に、他方の配線基板20にワイヤボンディングによって電気的に接続され、一対の配線基板10,20間が封止樹脂50によって封止されていることを特徴とする。
【選択図】図1
Description
このように、半導体素子等の電子部品を複数段に積み重ねて搭載する場合は、電子部品内蔵基板400は、平面寸法(平面積)が大きくなってしまうという課題や製造コストが嵩むといった課題を有している。
以下、本発明にかかる電子部品内蔵基板の実施の形態について、図面に基づいて説明する。図1は、本実施形態における電子部品内蔵基板の横断面図である。図2は、図1に示す電子部品内蔵基板の開口部付近の平面図である。図3は本実施形態において用いられるはんだボールの構造を示す断面図である。
本実施の形態における電子部品内蔵基板100は、一対の配線基板(下層側配線基板10と上層側配線基板20)の間に第1の電子部品である第1の半導体素子30が搭載され、第1の半導体素子30の上に第2の電子部品である第2の半導体素子60が搭載された構成となっている。第1の半導体素子30は一方の配線基板である下層側配線基板10に電気的に接続されている。第2の半導体素子60は他方の配線基板である上層側配線基板20に電気的に接続されている。また、下層側配線基板10と上層側配線基板20同士は、はんだボール40により電気的に接続され、下層側配線基板10と上層側配線基板20の間に封止樹脂50が充填されている。
銅コア42入りのはんだボール40を用いることにより、下層側配線基板10と上層側配線基板20は、少なくとも下層側配線基板10の接続パッド12Aと上層側配線基板20の接続パッド22Aの離間距離が銅コア42の径寸法となる離間距離を維持した状態で電気的に接続される。
第2の半導体素子60の電気的接続は、他方の配線基板である上層側配線基板20の上面に設けられたワイヤボンディング用接続パッド22Bと、第2の半導体素子60に形成された電極62とをボンディングワイヤ70により接続することにより行われる。
図6に示すように、リフロー後のはんだボールは、銅コア42の外周を被覆していたはんだ44が溶融し、はんだ44および銅コア42により下層側配線基板10の接続パッド12Aと上層側配線基板20の接続パッド22Aとを電気的に接続すると共に、銅コア42がストッパとして作用して互いの配線基板間10,20の離間距離を維持した状態になる。
基板10,20間に封止樹脂50を充填する方法としては、例えば図7に示すように、下層側配線基板10と上層側配線基板20の一方側の側面をダム90により覆い、他方側の下層側配線基板10と上層側配線基板20の側面から下層側配線基板10と上層側配線基板20の間に液状の封止樹脂50を注入する方法がある。液状の封止樹脂50は、毛細管現象により下層側配線基板10と上層側配線基板20の間に注入される。封止樹脂50を注入した後、封止樹脂50を加熱して硬化させる。
最後に下層側配線基板10の下面の接続パッド12Aへはんだボール等の外部接続端子14を接合する。
なお、本製造方法の説明においては、1つの電子部品内蔵基板100を図示して説明しているが、実際の製造方法においては、大判の下層側配線基板10および上層側配線基板20を用いて、複数の電子部品内蔵基板100,100,100,・・・を同時に樹脂封止した後、個々の基板外形に沿って個片に切断することによって個片の電子部品内蔵基板100を得ることができる。
図9は図8に示した状態から上層側配線基板の表面全体を第2の半導体素子を含めて樹脂により封止した状態を示す横断面図である。
図10は本発明にかかる電子部品内蔵基板の第2実施形態における構造を示す横断面図である。具体的には、第1の半導体素子30の裏面側に直接、第2の半導体素子60を搭載して構成された電子部品内蔵基板100である。
図10に示すように、上層側配線基板20で第2の半導体素子60が搭載される領域部分を封止樹脂50によって封止した場合は、上層側配線基板20の上の他の領域にチップコンデンサやチップ抵抗等の回路部品(図示せず)を搭載することもできる。
例えば、以上の実施形態においては、第1の電子部品30,および第2の電子部品60としてそれぞれ半導体素子を用いて説明しているが、第1の電子部品30,および第2の電子部品60は半導体素子に限定されるものではなく、他の電子部品を用いてもよい。
さらにまた、第1の半導体素子30は下層側配線基板10にフリップチップボンディングに替えて、ワイヤボンディングにより下層側配線基板10に電気的に接続しても良い。
例えば、下層側配線基板10の下面側と上層側配線基板20の上面側のそれぞれから下層側配線基板10と上層側配線基板20をクランプする上型と下型からなるトランスファーモールドを用い、トランスファーモールドのゲートから封止樹脂50を下層側配線基板10と上層側配線基板20間に圧入する形態もありうる。この場合上型は、開口部24に対応する部位に入子部分を設け、開口部24部分に封止樹脂50が入り込まないようにしておけばよい。
12,22 配線パターン
12A,22A 接続パッド
13,23 レジスト
14 外部接続端子
20 上層側配線基板
22B ワイヤボンディング用接続パッド
24 開口部
30,60 電子部品(半導体素子)
32,62 電極
36 バンプ
40 はんだボール
42 銅コア
44 はんだ
50,52 樹脂
80 アンダーフィル樹脂
90 ダム
100 電子部品内蔵基板
Claims (6)
- 一対の配線基板間に、複数段に電子部品が積み重ねて搭載された電子部品内蔵基板であって、
一方の配線基板と他方の配線基板同士がはんだボールを介して電気的に接続され、
前記一方の配線基板に第1の電子部品が搭載されると共に、該第1の電子部品の上に第2の電子部品が搭載され、
前記他方の配線基板には、前記第2の電子部品を収容する開口部が設けられ、
前記第2の電子部品は、前記開口部内に収容して搭載されると共に、前記他方の配線基板にワイヤボンディングによって電気的に接続され、
前記一対の配線基板間が封止樹脂によって封止されていることを特徴とする電子部品内蔵基板。 - 前記第2の電子部品は、ワイヤボンディングされる面が前記他方の配線基板の板厚内に位置するように搭載されていることを特徴とする請求項1記載の電子部品内蔵基板。
- 前記第1の電子部品は前記封止樹脂により被覆され、前記第2の電子部品は前記封止樹脂の表面に搭載されていることを特徴とする請求項1または2記載の電子部品内蔵基板。
- 前記第2の電子部品は、前記第1の電子部品に直接接着されていることを特徴とする請求項1または2記載の電子部品内蔵基板。
- 前記はんだボールは、金属を球状体に形成したコア材の外表面にはんだが被覆されてなるコア入りはんだボールが用いられていることを特徴とする請求項1〜4のうちのいずれか一項に記載の電子部品内蔵基板。
- 前記コア材は銅により形成されていることを特徴とする請求項5記載の電子部品内蔵基板。
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JP2006348755A JP5068990B2 (ja) | 2006-12-26 | 2006-12-26 | 電子部品内蔵基板 |
US11/962,749 US7772687B2 (en) | 2006-12-26 | 2007-12-21 | Multiple electronic component containing substrate |
KR1020070134923A KR20080060160A (ko) | 2006-12-26 | 2007-12-21 | 전자 부품 내장 기판 |
TW096150215A TW200830525A (en) | 2006-12-26 | 2007-12-26 | Electronic component contained substrate |
CNA2007101606339A CN101211901A (zh) | 2006-12-26 | 2007-12-26 | 包含电子元件的基板 |
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US (1) | US7772687B2 (ja) |
JP (1) | JP5068990B2 (ja) |
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Also Published As
Publication number | Publication date |
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US20080157329A1 (en) | 2008-07-03 |
KR20080060160A (ko) | 2008-07-01 |
CN101211901A (zh) | 2008-07-02 |
JP5068990B2 (ja) | 2012-11-07 |
TW200830525A (en) | 2008-07-16 |
US7772687B2 (en) | 2010-08-10 |
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