TWI419300B - 內建電子零件之基板及其製造方法 - Google Patents

內建電子零件之基板及其製造方法 Download PDF

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Publication number
TWI419300B
TWI419300B TW96148667A TW96148667A TWI419300B TW I419300 B TWI419300 B TW I419300B TW 96148667 A TW96148667 A TW 96148667A TW 96148667 A TW96148667 A TW 96148667A TW I419300 B TWI419300 B TW I419300B
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Taiwan
Prior art keywords
electronic component
wiring substrate
substrate
built
bonding
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TW96148667A
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English (en)
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TW200828560A (en
Inventor
Inoue Akinobu
Sorimachi Haruo
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Shinko Electric Ind Co
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Publication of TW200828560A publication Critical patent/TW200828560A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
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    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.

Description

內建電子零件之基板及其製造方法
本發明係有關於一種內建電子零件之基板及一種用以製造一內建電子零件之基板的方法。更特別地，本發明係有關於一種內建電子零件之基板，其能減少該基板之高度及平面尺寸及提高一電子零件與一佈線基板間之電性連接的可靠性，以及亦是有關於一種用以製造此一內建電子零件之基板的方法。
隨著電子裝置之性能的提高，已發展出內建電子零件之基板，在每一內建電子零件之基板上緊密地安裝電子零件。配置此等內建電子零件之基板中的一些基板，以便如圖12所述在佈線基板10間安裝電子零件30，以及以一樹脂50密封該等佈線基板10間之間隙(見例如專利文件1之圖1)。
[專利文件1]JP－A－2003－347722
(發明所欲解決之問題)
圖12所述之一內建電子零件之基板使用用以連接上及下佈線基板10及20之焊球40。因此，在使該上及下佈線基板10及20彼此連接前，一像一半導體元件之已安裝於該等佈線基板10及20間的電子零件30遭遇一製造程序諸如一助熔步驟、一焊球迴焊步驟及一清洗步驟的步驟。有時，此不利地影響該電子零件30。
更特別地，當藉由打線接合在一內建電子零件之基板上安裝一像一半導體元件之電子零件時，使該半導體元件之接合墊(亦即，鋁電極)及接合線暴露至外部環境。
此外，發生下面問題。亦即，擔心外力可能造成該等接合線之變形及斷裂。在該迴焊後之一清洗步驟中使用一酸性藥劑之情況中，會造成該半導體元件之接合墊的腐蝕。因此，很難藉由打線接合在一內建電子零件之基板上安裝一半導體元件。
因此，本發明之發明者設計出圖13及圖14所述之結構，其中該等結構係依據以打線接合在一佈線基板上安裝一像一半導體元件之電子零件的第一改良方法所獲得。
如圖13及14所述，藉由轉注成型以一樹脂70密封在一做為一打線接合至一佈線基板10之電子零件30的一接合墊的電極32與一接合線60間之連接部。結果，甚至當藉由一焊球40使一第一佈線基板10電性連接至其上所配置之一第二佈線基板20時，可確保在該電子零件30之電極32與該接合線60間之連接部的電性連接之可靠性。此外，可保護該接合線60。在使用此內建電子零件之基板的情況中，在藉由該焊球40使該第一佈線基板10連接至該第二佈線基板20後，以一密封樹脂50填充該兩個佈線基板10及20間之間隙。
然而，當以該樹脂70轉注成型該整個電子零件30時，一密封部係由圖13及14所述之在該電子零件30之外周圍部及上部的樹脂70所構成。此造成增加了該上佈線基板20與該下佈線基板10間之空隙因而阻礙該內建電子零件之基板100的小型化(或厚度減少)之問題。並且，該上佈線基板20與該下佈線基板10間之空隙的增加導致該用以使該上佈線基板20與該下佈線基板10彼此連接之焊球40的直徑尺寸之增加。因此，會有該焊球40之安裝面積的增加而很難小型化該內建電子零件之基板100的另一問題。
於是，本發明之一目的係要提供一種內建電子零件之基板及其製造方法，其能可靠地保護在一電子零件之側上的一連接部及可藉由保持該電子零件之一以一保護材料來塗佈之打線接合部(相當於一連接部)的塗佈範圍至最小以相當地減少該內建電子零件之基板的平面尺寸(亦即，該平面面積)及高度尺寸。
要達成前述目的，依據本發明之第一觀點，提供一種內建電子零件之基板，包括：至少兩個佈線基板；一電子零件，被提供於該兩個佈線基板之間；以及該電子零件之一電極，該電極電性連接至該等佈線基板中之至少一佈線基板，使該等佈線基板彼此電性連接，以及以一樹脂密封該等佈線基板間之間隙，其中一在該等佈線基板中之一上所形成之接合墊藉由一接合線電性連接至該電子零件之一電極，以及以一保護材料塗佈該電子零件之電極與該接合線間之至少一連接部。
依據本發明之第二觀點，提供依據第一觀點之內建電子零件之基板，其中在暴露該接合線與該等佈線基板間之一連接部及一由該接合線所構成之線環(wire loop)的一最上部之狀態中，以該保護材料塗佈該電子零件之電極與該接合線間之連接部。
結果，可保持該保護材料所塗佈之範圍至最小。於是，可減少該內建電子零件之基板的厚度及平面尺寸。可小型化該內建電子零件之基板。
依據本發明之第三觀點，提供依據第一或第二觀點之內建電子零件之基板，其中一焊球用以電性連接該等佈線基板。
再者，依據本發明之第四觀點，提供第三觀點之內建電子零件之基板，其中該焊球係一藉由以焊料塗佈一由一作為一核心之導電體所構成之球體的外表面所形成之含核心焊球。
結果，可確實地使該上及下佈線基板彼此連接。依據本發明之內建電子零件之基板的一具體例，該焊球係一藉由以焊料塗佈一由一導電體所構成之球體的外表面所形成之含核心焊球。因此，甚至當迴焊處理該焊球時，該導電體持續存在。結果，可藉由以一固定值維持該上及下佈線基板間之空隙以建立該電性連接。可提供一種具有高度平坦之薄結構的內建電子零件之基板。
依據本發明之第五觀點，提供一種內建電子零件之基板的製造方法，包括下列步驟：安裝一電子零件於一第一佈線基板之一預定部分上；實施打線接合以藉由一接合線電性連接一在該第一佈線基板上所形成之接合墊至該電子零件之一電極；以一保護材料塗佈該電子零件之電極與該接合線間之至少一連接部；配置該第一佈線基板及一第二佈線基板，使得以與該第一佈線基板分離之方式所形成之第二佈線基板的一表面面對該第一佈線基板之一表面，以及藉由迴焊處理一焊球以彼此電性連接該第一佈線基板及該第二佈線基板；迴焊處理該焊球以清洗該第一佈線基板與該第二佈線基板間之一部分；以及密封該第一佈線基板與該第二佈線基板間之一部分。
再者，依據本發明之第六觀點，提供依據第五觀點之內建電子零件之基板的製造方法，其中在以一保護材料塗佈該電子零件之電極與該接合線間之連接部的步驟中，在暴露該接合線與該第一佈線基板之接合墊間之一連接部及一由該接合線所構成之線環的一最上部的狀態中，以該保護材料塗佈該電子零件之電極與該接合線間之連接部。
依據本發明之一種內建電子零件之基板及其製造方法，可相當地減少該內建電子零件之基板的平面尺寸(亦即，該平面面積)及高度尺寸。並且，可以低成本提供一種具有高可靠性之電性連接的小內建電子零件之基板。此外，可減少對一用於轉注成型之模子的製造所強加之負荷。
 (第一具體例)
以下，參考所附圖式以描述依據本發明之一內建電子零件之基板的一具體例。圖1係描述依據本發明之具體例的一內建電子零件之基板的橫向剖面圖。圖2係描述在一電子零件與該基板間之一打線接合部的狀態之示意圖。
配置依據本具體例之一內建電子零件之基板100，以便在兩個佈線基板10及20間安裝電子零件30，以及藉由焊球40使一做為一第一佈線基板之下層側佈線基板10電性連接至一上層側佈線基板20。將一密封樹脂50注入該下層側佈線基板10與該上層側佈線基板20間之間隙。附帶地，在此圖式中，省略在該等佈線基板10及20之每一佈線基板上所形成之佈線的表示。
在該下層側佈線基板10之下表面上提供一做為一外部連接端之凸塊14，其中以焊料做為該凸塊14之範例。另一方面，除了像晶片電容器、晶片電阻器及電感器之電路零件之外，在該下層側佈線基板10之上表面上還放置像一半導體晶片之電子零件30。藉由焊接使該等電路零件16附著至在該下層側佈線基板10上所形成之佈線(未顯示)。藉由一黏著劑使該電子零件30附著至該下層側佈線基板10。隨後，藉由一接合線60使該電子零件30之電極32打線接合至該下層側佈線基板10之接合墊12。
藉由在一銅墊上實施金電鍍以形成在該下層側佈線基板10中所提供之接合墊12。一做為在該電子零件30上所提供之連接部的電極32係由鋁所製成。
將該上層側佈線基板20放置在該下層側佈線基板10上。使用在該等佈線基板10及20上所形成之佈線圖案(未顯示)及該等焊球40使該下層側佈線基板10及該上層側佈線基板20彼此電性連接。本具體例使用藉由以焊料44塗佈由導電銅材料所製成且形成球體之銅核心42的外表面所獲得之含銅核心焊球40。藉由迴焊處理該等焊球40之焊料44以經由該等銅核心42使該下層側佈線基板10及該上層側佈線基板20彼此電性連接。在使該等佈線基板10及20彼此分隔有一至少等於該等銅核心42之每一銅核心的直徑尺寸之距離的狀態中使該下層側佈線基板10及該上層側佈線基板20彼此電性連接。
附帶地，為了方便說明，圖1描述甚至在迴焊處理後該等焊球40之外周圍塗佈有該等焊料44，其中每一焊球40包含該銅核心42。然而，當迴焊處理每一具有該銅核心42之實際焊球40時，明顯地，該銅核心42與該焊料44不是同心球。
當熔化該等焊球40之焊料44時，該下層側佈線基板10之上表面，該電子零件30之上表面及側表面以及該上層側佈線基板20之下表面受助熔劑之污染。必需在該下層側佈線基板10與該上層側佈線基板20間注入一密封樹脂50，以便提供具有充分機械強度之內建電子零件之基板100及保護該電子零件30及該等電路零件16。並且，要使一密封樹脂50確實地黏附至該下層側佈線基板10、該電子零件30及該上層側佈線基板20，必需在該等焊料44之迴焊後實施該下層側佈線基板10與該上層側佈線基板20間之清洗。在那個時候，可使用一用以移除助熔劑之酸性物。因而，擔心可能毀損在該像一半導體晶片之電子零件30上所提供之電極32的鋁。因此，必需保護該電子零件30之電極32。
本具體例之特徵在於：一旦完成該電子零件30之電極32與該下層側佈線基板10之接合墊12的打線接合，在該下層側佈線基板10上配置該上層側佈線基板20前，立即以一樹脂70塗佈該電子零件30之電極32。
如圖1及2所述，以該樹脂70塗佈一在該半導體元件30之上表面上包括該打線接合電極部32之區域。藉由灌封(potting)該像環氧樹脂之樹脂以形成一塗佈有該樹脂70之部分。最好，當形成該塗佈有該樹脂70之部分時，從該樹脂70暴露一包括一由該接合線60所構成之線環的上端部(亦即，最上部)之預定部分與該下層側佈線基板10之接合墊12間之連接部。結果，可減少該塗佈有該樹脂70之部分的高度尺寸及平面尺寸。此對於該內建電子零件之基板100的小型化係有用的。此外，該下層側佈線基板10之接合墊12及該接合線60係由金所製成。不擔心因被暴露而降低該連接部之品質及在使用像酸性之化學藥品的情況中可能毀損該打線接合部。
因此，以該對於化學藥品具有抗性的樹脂70塗佈該半導體元件30之電極32。於是，甚至當使用一強清洗溶液實施該等佈線基板間之清洗時，可維持該電極32與該接合線60間之電性連接的可靠性。
並且，可提高該電極32與該接合線60間之連接的機械強度。因為該做為該保護材料之樹脂70只塗佈一包括該電子零件30之電極32的最小範圍(朝高度及寬度方向延伸)，所以相較於依據該相關技藝之藉由該轉注成型而塗佈有該樹脂之範圍的高度及寬度方向之大小，可相當地減少該塗佈有該樹脂70之範圍的高度尺寸及寬度尺寸。
基於相似理由，可由該線環之高度決定該下層側佈線基板10及該上層側佈線基板20之相對表面間的空隙。因此，可減少該等焊球40之每一焊球的直徑尺寸。可藉由使用此等小直徑焊球40減少該內建電子零件之基板100的厚度尺寸。並且，可使供應該等焊球40之間距變窄。結果，可減少該內建電子零件之基板100的平面面積。
此外，由於該塗佈有該樹脂70之範圍的寬度尺寸(亦即，該平面面積)之減少，可在靠近該電子零件30之位置上提供該等焊球40。結果，可進一步減少該整個內建電子零件之基板100的面積。
在以該做為該保護材料之樹脂70塗佈該整個接合線60之情況中，稍微會阻礙該內建電子零件之基板100的厚度尺寸及平面面積尺寸之減少。然而，可防止該接合線60變形及像該接合線之斷裂的意外事故，直到以該密封樹脂50密封該下層側佈線基板10與該上層側佈線基板20間之間隙為止。結果，可提高打線接合之電性連接的可靠性。
因此，在該內建電子零件之基板100中，藉由該樹脂70以保護包括該電子零件30之電極32的最小範圍。於是，可在該做為第一佈線基板之下層側佈線基板10上配置該做為第二佈線基板之上層側佈線基板20而沒有減少該下層側佈線基板10與該電子零件30間之電性連接的可靠性。並且，可相當地減少該內建電子零件之基板100的厚度及面積。雖然在本具體例中大部分的接合線60從該樹脂70突出，但是可充分保護該接合線60。此乃是因為將該密封樹脂50注入該下層側佈線基板10與該上層側佈線基板20間，以便以該密封樹脂50密封該接合線60。
(第二具體例)
圖3係描述依據本發明之第二具體例的一內建電子零件之基板的結構之橫向剖面圖。依據本具體例，配置該內建電子零件之基板100如下。亦即，在厚度之方向上配置3個佈線基板10a、10b及10c。在該等佈線基板10a及10b間安裝一做為一電子零件之半導體元件30a。並且，在該等佈線基板10b及10c間安裝一做為一電子零件之半導體元件30b。使該等半導體元件30a及30b彼此打線接合。因此，藉由焊球40使該等佈線基板10a及10b彼此電性連接。並且，藉由焊球40使該等佈線基板10b及10c彼此電性連接。如此圖式所述，可在該內建電子零件之基板100之最上部上所提供之佈線基板10c的上表面上安裝或提供一半導體元件30c及一電路零件16。雖然如圖3所述該半導體元件30c覆晶連接至該佈線基板10c之上表面，但是可使用打線接合連接以取代該覆晶連接。
藉由打線接合來連接該等半導體元件30a及30b而使該等元件電性連接至該等佈線基板10a及10b。至少，藉由灌封一做為一保護材料之樹脂70以塗佈該等電子零件30a及30b之每一電子零件的接合線60與電極32間之連接。
藉由焊接使在該佈線基板10c之上表面上所提供之電路零件16連接至該佈線基板10c。將一底部填充樹脂80注入該半導體元件30c與該佈線基板10c間。
(第三具體例)
圖4係描述依據本發明之第三具體例的一內建電子零件之基板的結構之橫向剖面圖。
依據本具體例，在第一具體例之前述說明中所述之內建電子零件之基板100的上層側佈線基板20之上表面上安裝一半導體元件30b。使該半導體元件30b打線接合至該上層側佈線基板20。以該密封樹脂50密封該半導體元件30b。
在使用本具體例之情況中，在使該半導體元件30b安裝在該上層側佈線基板20之上表面且打線接合至該上層側佈線基板20後，以該密封樹脂50密封該半導體元件30b。使該焊球40最初地接合至該上層側佈線基板20之下表面(亦即，可使用一BGA(球柵陣列)型之現有半導體裝置)。適當地在該打線接合有該半導體元件30a之下層側佈線基板10的上表面上配置該最初地製造成為一BGA型之半導體裝置之上層側佈線基板20，其中以該樹脂70保護該半導體元件30a之電極32。迴焊處理該等焊球40。然後，建立該下層側佈線基板10與該上層側佈線基板20間之電性連接。隨後，將像環氧樹脂之密封樹脂50注入該下層側佈線基板10與該上層側佈線基板20間，以便密封該下層側佈線基板10與該上層側佈線基板20間之空隙。因此，完成圖4所述之內建電子零件之基板100。
依據本具體例，可使用該已提供之BGA型之半導體裝置之佈線基板做為該上層側佈線基板20。結果，可提供該高密度內建電子零件之基板100。
(第四具體例)
圖5係描述依據本發明之第四具體例的一內建電子零件之基板的結構之橫向剖面圖。更特別地，圖5係描述應用本發明至圖14所述之內建電子零件之基板所獲得之內建電子零件之基板的狀態之示意圖。在本具體例之下面敘述中，使用已描述於第一具體例之敘述中的構件之元件符號。因此，省略此等構件之敘述。
在依據本具體例之內建電子零件之基板100中，使一第一半導體元件30a覆晶連接至一下層側佈線基板10。在該第一半導體元件30a上配置一第二半導體元件30b。使該第二半導體元件30b之一電極32b打線接合至該下層側佈線基板10之接合墊12。藉由一黏著劑使該第一半導體元件30a與該第二半導體元件30b彼此連接。
如圖5所述，以由焊料所製成之凸塊36使該第一半導體元件30a覆晶連接至該下層側佈線基板10。隨後，將一底部填充樹脂80注入該等佈線基板10及20之間。因此，甚至在藉由使用焊球40使該等佈線基板10及20彼此連接後該基板遭遇一清洗步驟之情況中，沒有降低該下層側佈線基板10與該第一半導體元件30a間之電性連接的可靠性。在該第二半導體元件30b之電極32b的材料為該鋁墊(其對於化學藥品之抗性為低)之情況中，相似於前述具體例，該電極32b需要以該對於化學藥品具有抗性之樹脂70來塗佈。在本具體例中，藉由灌封該做為該保護材料之樹脂70以塗佈該第二半導體元件30b之上表面的一部分(包括該第二半導體元件30b之電極32b與一接合線60間之連接部)。依據該灌封樹脂70之量，如圖5所述，不僅可以該樹脂70塗佈該半導體元件30b之上表面，而且可以塗佈該半導體元件30b之一側表面。
甚至在此情況中，可藉由暴露一由連接至該第二半導體元件30b之電極32b及該下層側佈線基板10之接合墊12的接合線60所構成之線環的最上部以減少該樹脂70在高度方向上之尺寸。此促成該內建電子零件之基板100的厚度之減少。
(第五具體例)
雖然在該等前述具體例之每一具體例的先前敘述中已描述該內建電子零件之基板100，但是除了該內建電子零件之基板100之外，本發明可應用至一包含電子零件之PoP(堆疊型封裝)結構的一電子零件封裝體200。圖6係描述使用依據本發明之一內建電子零件之基板的一PoP結構之一電子零件封裝體的配置之橫向剖面圖。藉由在厚度方向上配置第四具體例之先前敘述中所述之內建電子零件之基板(亦即，半導體封裝體)100A及100B以形成該PoP結構之電子零件封裝體200。
可藉由使用本具體例相當地減少該電子封裝體之厚度尺寸及平面尺寸。並且，可提供具有高可靠性之電性連接的PoP結構之電子零件封裝體200。
(內建電子零件之基板的製造方法)接著，下面描述一製造依據第一具體例之內建電子零件之基板100的方法。圖7至11係描述在依據本發明之內建電子零件之基板的製造程序之步驟中該內建電子零件之基板100的狀態之剖面圖。附帶地，可使用已知方法以做為在該下層側佈線基板10及該上層側佈線基板20上形成佈線圖案之方法。因此，在此省略這些方法之詳細敘述。
如圖7所述，在該做為第一佈線基板之下層側佈線基板10上定位及放置一做為一電子零件之半導體元件30。使該半導體元件30經由一黏著劑接合至該下層側佈線基板10。在該下層側佈線基板10上放置該半導體元件30後，藉由該接合線60使該半導體元件30之電極32及與該下層側佈線基板10之接合墊12彼此連接。使該半導體元件30及在該下層側佈線基板10上所形成之佈線圖案彼此電性連接。藉由灌封該像環氧樹脂之樹脂70至該電極32來以該樹脂70塗佈該電極32。在此時硬化該樹脂70。
接下來，如圖8所述，以焊料使該電路零件16連接至該下層側佈線基板10上所形成之佈線圖案的一暴露部分。雖然已藉由打線接合連接在該下層側佈線基板10上安裝該半導體元件30，但是以該做為該保護材料之樹脂70塗佈該電極32。因此，當在該下層側佈線基板10上安裝該電路零件16時，該電極32不受助熔劑及焊料之毀損。亦即，可維持該下層側佈線基板10與該半導體元件30間之電性連接的可靠性。
然後，如圖9所述，在該下層側佈線基板10之上表面上定位及放置該做為第二佈線基板之上層側佈線基板20，其中每一具有該銅核心42之焊球40連接至該上層側佈線基板20之下表面。設定該等焊球40之每一焊球的直徑尺寸，以便一相關銅核心42之直徑尺寸大於該下層側佈線基板10之上表面的高度位置與該接合線60之線環的上端表面(亦即，該最上部)的高度位置間之空隙。
在該下層側佈線基板10上定位及放置該上層側佈線基板20後，迴焊該等焊球40。因此，熔化用以覆蓋該銅核心42之外周圍的焊料，以便使該下層側佈線基板10及該上層側佈線基板20彼此電性連接。一旦完成該等焊球40之迴焊，立即實施一清洗操作，以便移除在該下層側佈線基板10與該上層側佈線基板20間之間隔中所留下之助熔劑。有時，使用酸性物做為清洗化學藥品。然而，以該做為該保護材料之樹脂70塗佈該半導體晶片30之電極32。因此，可使該半導體晶片30之電極32(由鋁所製成)與該接合線60間之電性連接的可靠性維持相同於該接合線60至該電極32之連接的程度。
接著，如圖10所示，將該密封樹脂50注入該下層側佈線基板10與該上層側佈線基板20之間。藉由轉注成型或實施一使用毛細管現象以鑄造一樹脂之方法以將該密封樹脂50注入該下層側佈線基板10與該上層側佈線基板20之間。
因此，以該密封樹脂50填充該下層側佈線基板10與該上層側佈線基板20間之間隔。以該密封樹脂50保護該尚未以該做為該保護材料之樹脂70來塗佈之接合線60。
一旦完成該密封樹脂50之注入，如圖11所述使該等由焊料之類所製成之凸塊14連接至該下層側佈線基板10之下表面。因此，完成該內建電子零件之基板100。
在該先前敘述中，已基於該等具體例之敘述來詳細描述該等內建電子零件之基板100及使用該等內建電子零件之基板100的PoP結構之封裝體。然而，本發明並非侷限於前述具體例。明顯地，在本發明之技術範圍內包括在不脫離本發明之精神下所實施之各種修改。
例如：雖然已藉由使用半導體元件做為該等電子零件30來描述該等具體例，但是該等電子零件30並非侷限於此。明顯地，可使用其它電子零件。
並且，當如第四具體例之先前敘述中所述在該做為第一佈線基板之下層側佈線基板10與該做為第二佈線基板之上層側佈線基板20間之上下方向上配置複數個電子零件30a及30b時，可藉由打線接合使該下層側電子零件(亦即，該半導體元件)30a連接至該下層側佈線基板10以取代覆晶連接。
10．．．佈線基板
10a．．．佈線基板
10b．．．佈線基板
10c．．．佈線基板
12．．．接合墊
14．．．凸塊
16．．．電路零件
20．．．第二佈線基板
30．．．電子零件
30a．．．半導體元件
30b．．．半導體元件
30c．．．半導體元件
32．．．電極
36．．．凸塊
40．．．焊球
42．．．銅核心
44．．．焊料
50．．．密封樹脂
60．．．接合線
70．．．樹脂(保護材料)
80．．．底部填充樹脂
100．．．內建電子零件之基板
100A．．．內建電子零件之基板
100B．．．內建電子零件之基板
200．．．電子零件封裝體
圖1係描述依據本發明之第一具體例的一內建電子零件之基板的橫向剖面圖。
圖2係描述在一電子零件與該基板間之一打線接合部的示意圖。
圖3係描述依據本發明之第二具體例的一內建電子零件之基板的結構之橫向剖面圖。
圖4係描述依據本發明之第三具體例的一內建電子零件之基板的結構之橫向剖面圖。
圖5係描述依據本發明之第四具體例的一內建電子零件之基板的結構之橫向剖面圖。
圖6係描述使用依據本發明之一內建電子零件之基板的一POP結構之一電子零件封裝體的配置之橫向剖面圖。
圖7係描述在依據本發明之一內建電子零件之基板的製造程序之一步驟中該內建電子零件之基板的狀態之剖面圖。
圖8係描述在依據本發明之內建電子零件之基板的製造程序之一步驟中該內建電子零件之基板的狀態之剖面圖。
圖9係描述在依據本發明之內建電子零件之基板的製造程序之一步驟中該內建電子零件之基板的狀態之剖面圖。
圖10係描述在依據本發明之內建電子零件之基板的製造程序之一步驟中該內建電子零件之基板的狀態之剖面圖。
圖11係描述在依據本發明之內建電子零件之基板的製造程序之一步驟中該內建電子零件之基板的狀態之剖面圖。
圖12係描述一內建電子零件之基板的一相關結構之橫向剖面圖，其中在佈線基板間安裝一電子零件及以一樹脂密封該等佈線基板間之間隙。
圖13係描述一內建電子零件之基板的第一改良結構之橫向剖面圖，其中藉由打線接合在一佈線基板上安裝一電子零件。
圖14係描述一內建電子零件之基板的第一改良結構之橫向剖面圖，其中藉由打線接合在一佈線基板上安裝一電子零件。
10．．．佈線基板
12．．．接合墊
14．．．凸塊
16．．．電路零件
20．．．第二佈線基板
30．．．電子零件
32．．．電極
40．．．焊球
42．．．銅核心
44．．．焊料
50．．．密封樹脂
60．．．接合線
70．．．樹脂(保護材料)
100．．．內建電子零件之基板

Claims (10)

  1. 一種內建電子零件之基板的製造方法，包括下列步驟：安裝一電子零件於一第一佈線基板之一預定部分上；實施打線接合以藉由一接合線電性連接一在該第一佈線基板上所形成之接合墊至該電子零件之一電極；以一保護材料塗佈該電子零件之電極與該接合線間之至少一連接部；配置該第一佈線基板及一第二佈線基板，使得以與該第一佈線基板分離之方式所形成之第二佈線基板的一表面面對該第一佈線基板之一表面且該電子零件置於該第一佈線基板與該第二佈線基板之間，以及藉由迴焊處理一焊球以彼此電性連接該第一佈線基板及該第二佈線基板；迴焊處理該焊球以清洗該第一佈線基板與該第二佈線基板間之一部分；以及除該保護材料之外，藉由毛細管現象注入有別該保護材料之一密封材料以密封該第一佈線基板與該第二佈線基板間之一部分，使該密封材料覆蓋並接觸該第二佈線基板之該一表面與該第一佈線基板之該一表面並填充該第一佈線基板與該第二佈線基板間之該部分。
  2. 如申請專利範圍第1項之內建電子零件之基板的製造方法，其中，在以該保護材料塗佈該電子零件之電極與該接合線間之連接部的步驟中， 在暴露一由該接合線所構成之線環的一最上部的狀態中，以該保護材料塗佈該電子零件之電極與該接合線間之連接部。
  3. 如申請專利範圍第1項之內建電子零件之基板的製造方法，其中，該密封材料完整地填充該第一佈線基板與該第二佈線基板間之該部分。
  4. 如申請專利範圍第1項之內建電子零件之基板的製造方法，其中，該密封材料係由樹脂構成。
  5. 如申請專利範圍第1項之內建電子零件之基板的製造方法，其中，該焊球係一藉由以焊料塗佈一由一導電體所構成之球體的外表面所形成之含核心(core-contained)焊球。
  6. 如申請專利範圍第1項之內建電子零件之基板的製造方法，其中，該電子零件包含一第一電子零件及一第二電子零件，及其中，該第一電子零件係配置於該等佈線基板之一者上，且該第二電子零件係配置於該第一電子零件上。
  7. 一種內建電子零件之基板，包含：一第一佈線基板，包含一第一墊及一接合墊於其上；一第二佈線基板，包含一第二墊於其上，且該第二佈線基板面對該第一佈線基板而在二者之間留有一間隙，使得該第一墊與該第二墊彼此相對； 一焊球，包含一核心及覆蓋至少一部分該核心之焊料，該焊球被提供於該第一佈線基板與該第二佈線基板之間，從而電性連接該第一佈線基板與該第二佈線基板，其中該焊料所暴露出的部分該核心直接地接觸該第一墊與該第二墊；一電子零件，包含一電極於其上，且該電子零件設置於該第一佈線板上，使該電極藉由一連接線電性連接至該接合墊；一密封樹脂，密封該第一佈線基板與該第二佈線基板之間的該間隙，使該密封樹脂覆蓋並接觸該第一與第二佈線基板所相對之該等表面並填充該間隙，其中，該電極與該接合線間之至少一連接部係塗佈該密封樹脂以外而與其有別之一保護材料，其中，該第一佈線基板與該第二佈線基板間之該間隙的最小距離實質上等於該焊球之核心的直徑，其中，該接合線具有一線環部，該保護材料曝露出該線環部之一頂部，及其中，該線環部之該頂部與該第一佈線基板之該相對表面的最小距離小於該焊球之該核心的直徑。
  8. 如申請專利範圍第7項之內建電子零件之基板，其中，該密封樹脂完整地填充該間隙。
  9. 如申請專利範圍第7項之內建電子零件之基板，其中，該電子零件包含一第一電子零件及一第二電子零件，及 其中，該第一電子零件係配置於該等佈線基板之一者上，且該第二電子零件係配置於該第一電子零件上。
  10. 如申請專利範圍第7項之內建電子零件之基板，其中，該電極包含複數個電極，該接合墊包含複數個接合墊，該接合線包含複數個接合線，該複數個電極沿該電子零件之一側排成一直線，該複數個接合墊排成一直線，且該複數個電極之每一者藉由該複數個接合線之一對應者電性連接至該複數個接合墊之一對應者。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8115380B2 (en) * 2008-08-14 2012-02-14 Global Oled Technology Llc Display device with chiplets
JP5352437B2 (ja) 2009-11-30 2013-11-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5589462B2 (ja) * 2010-03-16 2014-09-17 カシオ計算機株式会社 半導体装置及び半導体装置の製造方法
WO2012015085A1 (en) * 2010-07-30 2012-02-02 Lg Innotek Co., Ltd. Printed circuit board and method of manufacturing the same
JP6124513B2 (ja) 2012-05-17 2017-05-10 新光電気工業株式会社 半導体装置及びその製造方法
US9299650B1 (en) * 2013-09-25 2016-03-29 Stats Chippac Ltd. Integrated circuit packaging system with single metal layer interposer and method of manufacture thereof
DE112014006563T5 (de) * 2014-04-09 2017-02-16 GM Global Technology Operations LLC Systeme und verfahren zum verstärkten kleben
KR102381428B1 (ko) * 2015-03-02 2022-04-01 삼성디스플레이 주식회사 표시 장치
US10068181B1 (en) * 2015-04-27 2018-09-04 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafer and methods for making the same
FR3044864B1 (fr) * 2015-12-02 2018-01-12 Valeo Systemes De Controle Moteur Dispositif electrique et procede d'assemblage d'un tel dispositif electrique
KR20170138644A (ko) 2016-06-08 2017-12-18 삼성전자주식회사 Pop 구조의 반도체 어셈블리 및 이를 포함하는 전자 장치
US11121301B1 (en) 2017-06-19 2021-09-14 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafers and their methods of manufacture
US11664300B2 (en) * 2019-12-26 2023-05-30 Taiwan Semiconductor Manufacturing Co., Ltd. Fan-out packages and methods of forming the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5861666A (en) * 1995-08-30 1999-01-19 Tessera, Inc. Stacked chip assembly
US6337445B1 (en) * 1998-03-16 2002-01-08 Texas Instruments Incorporated Composite connection structure and method of manufacturing
US6489676B2 (en) * 2000-12-04 2002-12-03 Fujitsu Limited Semiconductor device having an interconnecting post formed on an interposer within a sealing resin
US6828665B2 (en) * 2002-10-18 2004-12-07 Siliconware Precision Industries Co., Ltd. Module device of stacked semiconductor packages and method for fabricating the same
JP2005311019A (ja) * 2004-04-21 2005-11-04 Hitachi Ltd 半導体パワーモジュール
TW200805508A (en) * 2006-07-14 2008-01-16 Au Optronics Corp Method for fabricating thin film transistor

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03295266A (ja) 1990-04-12 1991-12-26 Hitachi Ltd 高集積半導体装置
JP2000286380A (ja) 1999-03-30 2000-10-13 Nec Corp 半導体の実装構造および製造方法
JP2003347722A (ja) 2002-05-23 2003-12-05 Ibiden Co Ltd 多層電子部品搭載用基板及びその製造方法
JP3938071B2 (ja) 2003-02-27 2007-06-27 富士電機デバイステクノロジー株式会社 混成集積回路装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5861666A (en) * 1995-08-30 1999-01-19 Tessera, Inc. Stacked chip assembly
US6337445B1 (en) * 1998-03-16 2002-01-08 Texas Instruments Incorporated Composite connection structure and method of manufacturing
US6489676B2 (en) * 2000-12-04 2002-12-03 Fujitsu Limited Semiconductor device having an interconnecting post formed on an interposer within a sealing resin
US6828665B2 (en) * 2002-10-18 2004-12-07 Siliconware Precision Industries Co., Ltd. Module device of stacked semiconductor packages and method for fabricating the same
JP2005311019A (ja) * 2004-04-21 2005-11-04 Hitachi Ltd 半導体パワーモジュール
TW200805508A (en) * 2006-07-14 2008-01-16 Au Optronics Corp Method for fabricating thin film transistor

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