CN114242698A - 半导体封装结构及其制造方法 - Google Patents

半导体封装结构及其制造方法 Download PDF

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CN114242698A
CN114242698A CN202111385101.1A CN202111385101A CN114242698A CN 114242698 A CN114242698 A CN 114242698A CN 202111385101 A CN202111385101 A CN 202111385101A CN 114242698 A CN114242698 A CN 114242698A
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substrate
semiconductor package
package structure
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郭建利
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Blue Gun Semiconductor Co ltd
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Abstract

本发明公开一种半导体封装结构及其制造方法。所述半导体封装结构包括一基板及n个管芯的一管芯堆叠，其中n≧1。基板具有一第一侧、一第二侧及一开口，所述开口从第一侧延伸至第二侧。管芯堆叠设置在所述开口中。基板的厚度与管芯堆叠的厚度实质上相同。

Description

半导体封装结构及其制造方法
本申请是中国发明专利申请(申请号：201410341647.0，申请日：2014年07月17日，发明名称：半导体封装结构及其制造方法)的分案申请。
技术领域
本发明涉及一种半导体封装结构及其制造方法。特别是涉及一种减薄的半导体封装结构及其制造方法。
背景技术
在消费性电子产品如手机等等的发展过程中，总是追求着更佳的性能、更高的电源效率、更大的密度及更低的厚度。在这些目标中，厚度的降低会受到消费性电子产品中的电子零件的厚度所影响。举例来说，对于具有堆叠式封装(Package-On-Package,POP)结构的应用处理器或动态随机存取存储器来说，最低的厚度可能是两个堆叠的封装件的总厚度，其中每一个封装件的厚度往往是基板的厚度与形成于其上的管芯的厚度的总和。
发明内容
本发明的目的在于提供一种减薄的半导体封装结构及其制造方法。
根据一些实施例，所述半导体封装结构包括一基板及n个管芯的一管芯堆叠，其中n≧1。基板具有一第一侧、一第二侧及一开口，所述开口从第一侧延伸至第二侧。管芯堆叠设置在所述开口中。基板的厚度与管芯堆叠的厚度实质上相同。
根据一些实施例，所述半导体封装结构制造方法包括下列步骤。首先，将一基板贴附至一载板上。所述基板具有一第一侧、一第二侧及一开口，所述开口从第一侧延伸至第二侧。接着，将n个管芯的一管芯堆叠经由所述开口贴附至载板上，其中n≧1。基板的厚度与管芯堆叠的厚度实质上相同。
为了让本发明的上述内容能更明显易懂，下文特举实施例，并配合附图，作详细说明如下：
附图说明
图1A～图9为根据一实施例的半导体封装结构制造方法的示意图。
其中，附图标记
100：半导体封装结构
102：基板
102a：第一侧
102b：第二侧
102o：开口
104：重布层
106：导孔
108：管芯堆叠
110：载板
112：黏着层
114：第一黏着隔离层
116：第二黏着隔离层
118、122：第一电路层
120、124：第二电路层
126：接垫
128：接垫
130：第一钝化层
132：第二钝化层
134：管芯
具体实施方式
以下将说明所述半导体封装结构及其制造方法。图1A～图9绘示根据一实施例的半导体封装结构制造方法。为了清楚起见，元件的一部分可能会从附图中省略。
请参照图1A及图1B，提供一基板102。图1A为基板102的俯视图，图1B为基板102取自图1A的剖面线B-B’的剖面。基板102具有一第一侧102a、一第二侧102b及一开口102o，开口102o从第一侧102a延伸至第二侧102b。基板102可为晶片或平板。在一些例子中，基板102包括硅或玻璃等等。基板102可包括重布层(redistribution layer)104及连接重布层104的导孔(via)106。重布层104可由铜、或铝、或钨、或其组合所形成。
请参照图2，提供n个管芯的一管芯堆叠108，其中n≧1。在图2的例子中，绘示出由二个管芯构成管芯堆叠108。在其他例子中，管芯堆叠108可包括单一个管芯或多于二个管芯。管芯堆叠108的管芯可完全相同、部分相同或完全不同。在一些例子中，管芯堆叠108中的一或多个管芯包括直通硅穿孔(Through-Silicon Via,TSV)。
在此，可调整基板102的厚度或管芯堆叠108中的管芯的厚度，使得基板102的厚度与管芯堆叠108的厚度实质上相同。例如，可从管芯的背面(与集成电路及内连线所在的表面相对的表面)薄化管芯以调整管芯的厚度。
请参照图3，首先，将基板102贴附至一载板110上。接着，将管芯堆叠108经由基板102的开口102o贴附至载板110上。在一些例子中，可选择性地进行一对准步骤。基板102及管芯堆叠108可通过黏着层112暂时性地固定于载板110上。在此，基板102的厚度与管芯堆叠108的厚度实质上相同。
请参照图4，可形成一第一黏着隔离层114于基板102的第一侧102a上及基板102与管芯堆叠108之间。第一黏着隔离层114可包括光敏性黏着剂，例如苯并环丁烯(benzocyclobutene,BCB)或聚苯恶唑(polybenzoxazole,PBO)等等。第一黏着隔离层114可提供在接下来的步骤中所形成的电路层(例如第一电路层118及122)电性隔离。可图案化第一黏着隔离层114。
请参照图5，移除载板110。接着可形成一第二黏着隔离层116于基板102的第二侧102b。第二黏着隔离层116可包括与第一黏着隔离层114相同的材料，例如光敏性黏着剂。第二黏着隔离层116可提供在接下来的步骤中所形成的电路层(例如第二电路层120及124)电性隔离。可图案化第二黏着隔离层116。
请参照图6，可形成一第一电路层118于基板102的第一侧102a上，并可形成一第二电路层120于基板102的第二侧102b上。第一电路层118及第二电路层120可由半加成金属化制作工艺(semi-additive metallization process)形成。半加成金属化制作工艺例如包含下列步骤：在隔离层(114或116)中形成开口(对应至参考图5的图案化隔离层的叙述)；以例如无电镀处理在隔离层表面及开口的侧壁与底部上形成薄的顺形金属层；在隔离层上形成图案化光致抗蚀剂，其中图案化光致抗蚀剂未覆盖的区域为欲形成金属导线的区域；以电镀处理于图案化光致抗蚀剂未覆盖的区域形成金属导线并填满隔离层中的开口；移除图案化光致抗蚀剂；及移除原本被图案化光致抗蚀剂所覆盖的薄的顺形金属层。
请参照图7，可形成另一第一电路层122于第一电路层118上，并可形成另一第二电路层124于第二电路层120上。第一电路层122及第二电路层124可由半加成金属化制作工艺形成。第一电路层122包括接垫126。第二电路层124包括接垫128。
请参照图8，可形成一第一钝化层130于第一电路层122上，并可形成一第二钝化层132于第二电路层124上。第一钝化层130露出第一电路层122的接垫126。第二钝化层132露出第二电路层124的接垫128。
请参照图9，可提供一管芯134于第一钝化层130上。在图9的例子中，例示性地提供三个管芯134。电连接管芯134至第一电路层122的接垫126。管芯134可经由打线连接、球栅阵列连接(Ball Grid Array,BGA)或倒装(flip chip)连接电连接至第一电路层122的接垫126。在图9的例子中，管芯134与接垫126是经由打线连接来连接。在图9的例子中，焊球形成在第二电路层124的接垫128上，以提供电连接。然而，可使用其他连接方法，例如倒装连接。
接着，可进行一切割基板102的步骤。但应注意，此一切割步骤可并入在形成第一黏着隔离层114之后所进行的任一步骤中。
经由上述方法，管芯堆叠108被设置在基板102的开口102o中。此外，基板102的厚度被调整成与管芯堆叠108的厚度实质上相同。因此，可进一步地降低厚度。所减少的厚度至少等于一个基板的厚度。相较于传统的堆叠式封装结构，由上述方法所形成的堆叠式封装结构可减薄约200微米。
由上述方法所形成的一半导体封装结构100包括一基板102及n个管芯的一管芯堆叠108，其中n≧1。基板102具有一第一侧102a、一第二侧102b及一开口102o，开口102o从第一侧102a延伸至第二侧102b。基板102可为晶片或平板。在一些例子中，基板102包括硅或玻璃等等。在一些例子中，n个管芯的其中一者不同于其中另一者。管芯堆叠108设置在开口102o中。基板102的厚度与管芯堆叠108的厚度实质上相同。
半导体封装结构100还可包括一第一黏着隔离层114及一第二黏着隔离层116。第一黏着隔离层114设置在基板102的第一侧102a上及基板102与管芯堆叠108之间。第二黏着隔离层116设置在基板102的第二侧102b上。第一黏着隔离层114及第二黏着隔离层116可包括光敏性黏着剂，例如苯并环丁烯(BCB)或聚苯恶唑(PBO)等等。
半导体封装结构100还可包括至少一第一电路层118/122及至少一第二电路层120/124。所述至少一第一电路层118/122设置在基板102的第一侧102a上。所述至少一第一电路层118/122包括接垫126。所述至少一第二电路层120/124设置在基板102的第二侧102b上。所述至少一第二电路层120/124包括接垫128。
半导体封装结构100还可包括一第一钝化层130及一第二钝化层132。第一钝化层130设置在所述至少一第一电路层118/122上。第一钝化层130露出所述至少一第一电路层118/122的接垫126。第二钝化层132设置在所述至少一第二电路层120/124上。第二钝化层132露出所述至少一第二电路层120/124的接垫128。
半导体封装结构100还可包括一管芯134。管芯134设置在第一钝化层130上，并电连接至所述至少一第一电路层118/122的接垫126。管芯134可经由打线连接、球栅阵列连接或倒装连接电连接至接垫126。在一些例子中，可形成焊球于接垫128上，以提供电连接。在其他例子中，可使用其他连接方法，例如倒装连接。
在此一实施例中，由于管芯堆叠108是设置在基板102的开口102o中，且基板102的厚度被调整成与管芯堆叠108的厚度实质上相同，因此可进一步地减低厚度。如上所述，相较于传统的堆叠式封装结构，半导体封装结构100可减薄约200微米。
综上所述，虽然结合以上优选实施例公开了本发明，然而其并非用以限定本发明。本发明所属技术领域的技术人员，在不脱离本发明精神和范围之内，可作各种的更动与润饰。因此，本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (20)

1.一种半导体封装结构，包括：
基板，具有第一侧、第二侧及开口，所述开口从所述第一侧延伸至所述第二侧；以及
n个管芯的管芯堆叠，其中n≧1，所述管芯堆叠设置在所述开口中；
其中所述基板的厚度与所述管芯堆叠的厚度实质上相同。
2.根据权利要求1所述的半导体封装结构，其中所述基板为晶片或平板。
3.根据权利要求1所述的半导体封装结构，其中所述n个管芯的其中一者不同于其中另一者。
4.根据权利要求1所述的半导体封装结构，还包括：
第一黏着隔离层，设置在所述基板的所述第一侧上及所述基板与所述管芯堆叠之间；以及
第二黏着隔离层，设置在所述基板的所述第二侧上。
5.根据权利要求4所述的半导体封装结构，其中所述第一黏着隔离层及所述第二黏着隔离层包括光敏性黏着剂。
6.根据权利要求4所述的半导体封装结构，还包括：
至少一第一电路层，设置在所述的基板所述第一侧上，所述至少一第一电路层包括多个接垫；以及
至少一第二电路层，设置在所述的基板所述第二侧上，所述至少一第二电路层包括多个接垫。
7.根据权利要求6所述的半导体封装结构，还包括：
第一钝化层，设置在所述至少一第一电路层上，所述第一钝化层露出所述至少一第一电路层的所述接垫；以及
第二钝化层，设置在所述至少一第二电路层上，所述第二钝化层露出所述至少一第二电路层的所述接垫。
8.根据权利要求7所述的半导体封装结构，还包括：
管芯，设置在所述第一钝化层上，并电连接至所述至少一第一电路层的所述接垫。
9.一种半导体封装结构制造方法，包括：
将一基板贴附至一载板上，所述基板具有一第一侧、一第二侧及一开口，所述开口从所述第一侧延伸至所述第二侧；以及
将n个管芯的一管芯堆叠经由所述开口贴附至所述载板上，其中n≧1；
其中所述基板的厚度与所述管芯堆叠的厚度实质上相同。
10.根据权利要求9所述的半导体封装结构制造方法，其中所述基板为晶片或平板。
11.根据权利要求9所述的半导体封装结构制造方法，其中所述n个管芯的其中一者不同于其中另一者。
12.根据权利要求9所述的半导体封装结构制造方法，还包括：
形成一第一黏着隔离层于所述基板的所述第一侧上及所述基板与所述管芯堆叠之间；以及
移除所述载板。
13.根据权利要求12所述的半导体封装结构制造方法，还包括：
形成一第二黏着隔离层于所述基板的所述第二侧上。
14.根据权利要求13所述的半导体封装结构制造方法，其中所述第一黏着隔离层及所述第二黏着隔离层包括光敏性黏着剂。
15.根据权利要求13所述的半导体封装结构制造方法，还包括：
形成至少一第一电路层于所述基板的所述第一侧上，所述至少一第一电路层包括多个接垫；以及
形成至少一第二电路层于所述基板的所述第二侧上，所述至少一第二电路层包括多个接垫。
16.根据权利要求15所述的半导体封装结构制造方法，其中所述至少一第一电路层及所述至少一第二电路层是由半加成金属化制作工艺形成。
17.根据权利要求15所述的半导体封装结构制造方法，还包括：
形成一第一钝化层于所述至少一第一电路层上，所述第一钝化层露出所述至少一第一电路层的所述接垫；以及
形成一第二钝化层于所述至少一第二电路层上，所述第二钝化层露出所述至少一第二电路层的所述接垫。
18.根据权利要求17所述的半导体封装结构制造方法，还包括：
提供一管芯于所述第一钝化层上，并电连接提供于所述第一钝化层上的所述至所述至少一第一电路层的所述接垫。
19.根据权利要求18所述的半导体封装结构制造方法，其中提供于所述第一钝化层上的所述管芯是经由打线连接、球栅阵列连接或倒装连接电连接至所述至少一第一电路层的所述接垫。
20.根据权利要求12所述的半导体封装结构制造方法，还包括：
切割所述基板。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9679842B2 (en) * 2014-10-01 2017-06-13 Mediatek Inc. Semiconductor package assembly
KR102450576B1 (ko) * 2016-01-22 2022-10-07 삼성전자주식회사 전자 부품 패키지 및 그 제조방법
TWI643305B (zh) * 2017-01-16 2018-12-01 力成科技股份有限公司 封裝結構及其製造方法
US20190013214A1 (en) * 2017-07-10 2019-01-10 Powertech Technology Inc. Package structure and manufacturing method thereof
DE102018109433B3 (de) * 2018-04-19 2019-09-19 Infineon Technologies Ag Verfahren zur stabilisierung einer halbleiteranordnung
WO2021025695A1 (en) * 2019-08-08 2021-02-11 Hewlett-Packard Development Company, L.P. Electronic device housings with patterned electrolytic plating layers
KR20210044934A (ko) 2019-10-15 2021-04-26 삼성전자주식회사 반도체 패키지 및 그 제조 방법

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6709897B2 (en) * 2002-01-15 2004-03-23 Unimicron Technology Corp. Method of forming IC package having upward-facing chip cavity
JP4094494B2 (ja) * 2002-08-23 2008-06-04 新光電気工業株式会社 半導体パッケージ
JP2006210402A (ja) * 2005-01-25 2006-08-10 Matsushita Electric Ind Co Ltd 半導体装置
US7973398B2 (en) * 2005-05-12 2011-07-05 Unimicron Technology Corp. Embedded chip package structure with chip support protruding section
US20080116584A1 (en) * 2006-11-21 2008-05-22 Arkalgud Sitaram Self-aligned through vias for chip stacking
US8178964B2 (en) * 2007-03-30 2012-05-15 Advanced Chip Engineering Technology, Inc. Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for WLP and method of the same
US7829998B2 (en) * 2007-05-04 2010-11-09 Stats Chippac, Ltd. Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer
US7723159B2 (en) * 2007-05-04 2010-05-25 Stats Chippac, Ltd. Package-on-package using through-hole via die on saw streets
US7772691B2 (en) * 2007-10-12 2010-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally enhanced wafer level package
US8334170B2 (en) * 2008-06-27 2012-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for stacking devices
US8237257B2 (en) * 2008-09-25 2012-08-07 King Dragon International Inc. Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same
KR20100046760A (ko) * 2008-10-28 2010-05-07 삼성전자주식회사 반도체 패키지
US7986048B2 (en) * 2009-02-18 2011-07-26 Stats Chippac Ltd. Package-on-package system with through vias and method of manufacture thereof
JPWO2010134511A1 (ja) * 2009-05-20 2012-11-12 日本電気株式会社 半導体装置及び半導体装置の製造方法
KR20110054348A (ko) * 2009-11-17 2011-05-25 삼성전기주식회사 전자소자 내장형 인쇄회로기판 및 그 제조방법
TWI409923B (zh) * 2009-12-02 2013-09-21 King Dragon Internat Inc 具有晶粒埋入式以及雙面覆蓋重增層之基板結構及其方法
US8378480B2 (en) 2010-03-04 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy wafers in 3DIC package assemblies
US8455300B2 (en) 2010-05-25 2013-06-04 Stats Chippac Ltd. Integrated circuit package system with embedded die superstructure and method of manufacture thereof
US8872312B2 (en) * 2011-09-30 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. EMI package and method for making same

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