TWI536469B - 微電子封裝體基體用多重表面修整層 - Google Patents

微電子封裝體基體用多重表面修整層 Download PDF

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Publication number
TWI536469B
TWI536469B TW099139337A TW99139337A TWI536469B TW I536469 B TWI536469 B TW I536469B TW 099139337 A TW099139337 A TW 099139337A TW 99139337 A TW99139337 A TW 99139337A TW I536469 B TWI536469 B TW I536469B
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Taiwan
Prior art keywords
substrate
region
connection
layer
conditioning layer
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TW099139337A
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TW201126622A (en
Inventor
吳濤
恰拉法那庫瑪拉 古魯莫西
雷那多Ａ 歐米多
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英特爾公司
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Publication of TW201126622A publication Critical patent/TW201126622A/zh
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    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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Description

微電子封裝體基體用多重表面修整層 發明領域
本說明係有關將表面修整層施加至一微電子封裝體基體之連接區的領域，特別是將多個不同的表面修整層施加至一單一基體之多個不同的連接區。
 發明背景
半導體及微機械裝置典型附接於一基體上。之後一外蓋附接該基體上來密封及保護內側裝置。該外蓋可包括散熱片或散熱管或僅為附接該基體之外側邊緣的一簡單塑膠外蓋。該基體會對一印刷線路板、一插座、或其他某些安裝裝置進行電氣及機械連接。具有該附接外蓋之基體稱為一封裝體。隨著封裝體及內側裝置之日漸複雜，會對該基體以及其到內側裝置與到其外部連接兩者之連接有新需求。
某些情況中，一基體可具有不同的電氣連接類型。該等電氣連接針對大小、密度、電容、阻抗及其他特性可具有不同的電氣需求。一基體上之連接使用絲網印刷、光刻、以及其他類似程序來建立時，使用一單一組合之製造程序很難建立不同的連接類型。
依據本發明之一實施例，係特地提出一種方法，其包含下列步驟：將一第一表面修整層施加於一基體之一第一區的連接襯墊；將該基體之該第一區遮蔽而不遮蔽該基體之一第二區；將一不同的第二表面修整層施加於該基體之該第二區的連接襯墊；以及移除遮罩。
圖式簡單說明
本發明之實施例藉由附圖中之圖形作為範例而非限制來加以繪示，其中相同參考數字用來參照為相同特徵，而其中：第1圖是一根據本發明之一實施例的一疊合式封裝體裝置之側橫截面圖；第2圖是一根據本發明之一實施例，具有兩種不同類型襯墊開口之一封裝體基體的頂視平面圖；第3圖是一根據本發明之一實施例，具有兩種不同類型的襯墊開口以及周圍附近具有一連接條之一替代封裝體基體的頂視平面圖；第4A圖是一根據本發明之一實施例，對一封裝體基體準備兩種不同表面修整層之一程序的橫截面圖；第4B圖顯示根據本發明之一實施例，將一POP襯墊區表面修整層加入第4A圖之封裝體基體；第4C圖顯示根據本發明之一實施例，將一保護遮罩加入該封裝體基體；第4D圖顯示根據本發明之一實施例，將一表面修整層加入該封裝體基體之一C4連接區；第4E圖顯示根據本發明之一實施例，從該封裝體基體移除該保護遮罩；第4F圖顯示根據本發明之一實施例，將C4焊料凸塊加入該封裝體基體；第5A圖是一根據本發明之一實施例，對一封裝體基體準備三種不同表面修整層之一替代程序的橫截面圖；第5B圖顯示根據本發明之一實施例，將一表面修整層加入第5A圖之無核心基體的一C4連接區；第5C圖顯示根據本發明之一實施例，從該無核心基體移除一抗蝕型樣；第5D圖顯示根據本發明之一實施例，將一POP襯墊區之抗蝕型樣化加入該無核心基體；第5E圖顯示根據本發明之一實施例，將一表面修整層加入該無核心基體之該C4連接區；第5F圖顯示根據本發明之一實施例，將多層連接及電介質以及一抗蝕型樣加入該無核心基體；第5G圖顯示根據本發明之一實施例，將一表面修整層加入該無核心基體之一BGA連接區；第5H圖顯示根據本發明之一實施例，於該BGA連接區上施加一保護薄膜以及從該無核心基體之底部蝕刻一銅層；第5I圖顯示根據本發明之一實施例，從該無核心基體移除該保護薄膜；第5J圖顯示根據本發明之一實施例，將C4連接焊料凸塊施加至該無核心基體；第6圖是一根據本發明之一實施例，於一基體上產生多個表面修整層之程序流程圖。
 較佳實施例之詳細說明
某些POP(疊合式封裝體)基體中，C4(受控崩潰晶片連接)及POP互連體區域兩者會存於相同基體上。一單一表面修整層無法使該等互連體之效能最佳化。為改善效能，一無電表面修整層(亦即，鎳鈀金)可施加至該C4襯墊而該POP襯墊遮蔽。一雙C4表面修整層可用來提供C4及POP襯墊互連體兩者良好的焊料接合可靠性(SJR)。一種新的基體製造程序可用來建立兩種不同的表面修整層類型，一位於一HDI(高密度互連體)POP(疊合式封裝體)基體之該C4側而另一位於該POP襯墊側。
一電解表面修整層，亦即，鎳金，已證實針對滴劑效能為一良好的表面修整層。一高效能POP襯墊表面修整層可藉由施加一電解表面修整層以及將所有待連接之POP襯墊安排路由至一電解電鍍條來完成。然而，由於襯墊及軌跡之高密度所以一電解表面修整層無法施加至一C4區。無電表面修整層(亦即，鎳鈀金)在電氣及熱老化的情況下，已證實針對焊料接合可靠性為一完美的表面修整層。
第1圖是一本發明之實施例可施加的一封裝體之簡化橫截面圖。第1圖中，該封裝體10為一疊合式封裝體(POP)類型的封裝體。在一倒裝晶片組態中，該封裝體底部之一基體8承載一第一晶粒6。於一範例中，該第一晶粒為一CPU(中央處理單元)、ASIC(特殊應用積體電路)、微控制器、或其他邏輯裝置。其電氣連接主要位於面對該晶粒之底部並緊密放置一起，使得所有該所需之插針適合位於該晶粒之底部表面上。
該倒裝晶片晶粒6具有一C4連接區7，其具有與該基體8之一對應C4連接區32連接的一密集包裝的焊料凸塊格柵。該晶粒之頂部以一適當的外蓋或塗層9來封裝。
一第二晶粒或晶粒組合16亦包含於該晶粒上之封裝體中，並由一第二基體12來與該晶粒區隔開。該繪示範例中，該上晶粒為具有三種組件16-1、16-2、16-3堆疊一起來形成該晶粒之堆疊記憶體晶粒。然而，亦可使用其他任何類型之晶粒或晶粒群組。於一單一封裝體中一邏輯裝置及記憶體之組合對低功率、小型裝置而言具有顯著的優點。然而，亦可將其他任何兩個或更多晶粒封裝一起，而該等兩晶粒之相對位置可顛倒或調整為適合任何特定的應用。
該上基體12於一側，一頂側12-1直接連接至該第二晶粒16。該連接典型提供電氣及機械支撐並更詳細說明如下。該上基體之相對側，該底側12-2上，該基體連接至一球格柵陣列(BGA)34。該連接由一格柵或一格柵的一部分之格式的一焊料球陣列所組成。該等焊料球18使該封裝體10之上基體12與該封裝體10之下側基體8之間形成電氣連接。該附接可以任何不同的方式來完成。該繪示範例中，該連接使用一球格柵陣列(BGA)，其中顯示該陣列之若干焊料球18。該等焊料球放置於該封裝體之下側基體的連接襯墊21上。
一外蓋23附接於該基體之周圍並蓋住晶粒及所有內部連接兩者。該外蓋提供區隔外部元件的保護而附接該基體 可為一密封封條。該外蓋可包括散熱片、散熱器、散熱管或其他任何不同的冷卻裝置(未顯示)。類似該上外蓋的一第二外蓋9保護該倒裝晶片晶粒6。
該上基體之頂側承載連接22以便與該上晶粒之一底部表面直接接觸。該特別的連接類型可配適成適合任何的特別應用。該繪示範例中使用焊料凸塊。第1圖該繪示橫截面圖中僅顯示五個連接。此為一簡化圖形。可以有數十或數百個連接。該等連接於一側，一頂側與該晶粒接觸，而之後延伸經過孔徑至該上基體底部的接觸襯墊。該等接觸襯墊可連接經過該基體底部上之BGA。此允許與該晶粒16作外部連接。
除了該基體與該記憶體晶片16間之連接22之外，該基體亦承載線路26附接之線路襯墊24來連接至該記憶體晶粒16之頂部上的對應襯墊(未顯示)。該等線路襯墊連接經過孔徑至該基體底部上之BGA。某些應用中，該等線路連接可用來作為電源，而該倒裝晶片晶粒之頂部的其他連接可用來作為高速發信號或資料傳送。
該基體頂側上的額外線路襯墊28用來將線路30連接至該記憶體堆疊之頂層16-1。若該晶粒為一記憶體晶粒，則可使用線路連接而非接觸襯墊22來輕易支援記憶體裝置中典型之較低連接密度。該等額外線路襯墊亦可經由孔徑連接至該BGA。此外，該基體可提供線路層來將某些襯墊，而非其他襯墊連接至該球格柵陣列之不同點。因此，針對一襯墊之陣列會有若干球而該基體之若干襯墊連接至一焊 料球。
如上所述，該下基體於其頂側8-1連接至該下晶粒之C4接觸區以及該上基體之BGA接觸區。其底側8-2上，其連接至一印刷電路板(PCB)、印刷線路板(PWB)、插座20或其他某些介面。該底側具有一BGA19來連接至該PCB之一襯墊陣列。經過該低基體8之孔徑將該頂側之接點連接至該底側之接點。雖然顯示的是C4、線結合及BGA連接，但亦可使用一大範圍的不同連接。該特別低密度及高密度互連體可配適成適合任何的特定應用。
第1圖之範例顯示一HDI(高密度互連體)型POP裝置之示意圖。類似一典型LDI(低密度互連體)型POP，該裝置之頂部，該上晶粒16，為一記憶體晶片封裝體。但該底部封裝體與一典型LDI POP封裝體不同。不使用該晶粒與該基體間之線結合，一HDI型基體12用於該底部封裝體以及線結合。該晶粒與該基體間之互連體可由倒裝晶片形成來取得該HDI區，但亦可使用其他類型之晶片組態。因此，該基體針對該倒裝晶片連接具有一HDI區而針對該線結合連接具有一LDI區。
第2圖顯示第1圖之POP基體8的一頂視平面圖8-1之圖形。其具有兩種類型之襯墊開口。有一HDI區32，本情況為一C4區，來完成與該低晶粒之倒裝晶片連接。在此，該等連接襯墊非常密集而針對晶粒互連體具有微小開口。
該基體邊緣處，環繞該C4區，為該BGA之一LDI區34，其連接至依次連接至該上晶粒之線結合的該上基體。在 此，該等連接為低密度而該等襯墊具有大開口。本文中此稱為POP襯墊，其用於底部及頂部封裝體之互連。於取決於線結合之一習知POP中，所有該等連接為此類型之低密度襯墊。該中央HDI連接32連接至該低晶粒而該周圍LDI連接34透過該封裝體之上基體連接至該上晶粒。
該C4襯墊及該POP襯墊之目的及功能不同，因為其以不同方式來形成不同類型的連接，為達到焊料接合可靠性該襯墊表面修整層之需求會相當不同。該C4區焊料接合點通常以底部填充來保護，但在電氣及熱老化的情況下需很大的可靠性。該焊料連接已完成填入該等連接間之空間並保護其免受物理、化學、及熱效應後，該底部填充為施加該基體及該晶粒間之一電介質。另一方面，該POP襯墊焊料接合點可確保較少的信號或電氣老化需求但需較高的滴劑測試效能。不同的連接類型中之需求及要求會有其他差異。
為提供兩種連接區類型整潔、可靠、耐用的連接，可使用不同的表面修整層。一種表面修整層被用於該C4襯墊而另一表面修整層被用於該POP襯墊區。以下範例將在C4及POP襯墊連接之脈絡中呈現，然而，其他類型的連接以及連接組合亦可從本發明之不同實施例中獲得益處。
針對滴劑效能，一電解表面修整層，亦即，鎳金已證實為一良好的表面修整層。於一範例中，一電解表面修整層，(亦即，鎳金)可被施加來作為一POP襯墊表面修整層。此外，所有該等POP襯墊可受安排路由來連接至一電解電鍍條。然而，由於襯墊及軌跡之高密度，一電解表面修整層亦不需在一C4區中運作。針對在電氣及熱老化的情況下良好的焊料接合可靠性，一無電表面修整層(亦即，鎳鈀金)已證實為一完美的表面修整層。因此該POP襯墊被遮蔽時，一無電表面修整層(亦即，鎳鈀金)可施加至該C4襯墊。
第3圖顯示一替代POP基體之一頂視平面圖的圖形。第3圖之範例中，該基體40具有四個C4區42-1至42-4。其每一個以POP襯墊連接區44-1至44-4環繞。該等POP襯墊耦合經過該基體之線路軌跡或線段46而至靠近該基體之外側邊緣的電解電鍍條48。如第2圖之範例中，該等POP襯墊區環繞該C4接點區。該等電解電鍍條依次環繞該等POP襯墊區。該繪示範例中，該C4連接區形成一正方形。該等POP襯墊於該C4襯墊正方形附近形成一正方形。該等電鍍條於該POP襯墊區附近形成一正方形，而該等線路軌跡將該等POP襯墊連接至該等電鍍條。該等電鍍條之後可連接經過孔徑至BGA或該基體之底部的連接器(未顯示)。該繪示範例中，僅有該等POP襯墊受安排路由來連接至一電解電鍍條。然而，根據該特別的應用亦可使用一大範圍的不同線路及安排路由之變化型態。
第4A圖至第4F圖顯示準備具有雙表面修整層或兩種不同表面修整層之一HDI POP基體的一程序。該規則的HDI增進程序及SR(焊料阻劑)程序後，該POP襯墊表面修整層(亦即，鎳金)會被電解電鍍。之後該POP襯墊被標示而該C4區襯墊表面修整層(亦即，鎳鈀金)會被無電電鍍。該POP襯墊標示移除後，該規則的HDI程序被回復。
該新程序有一明顯優點是可應付於一C4區、一POP襯墊、以及一BGA襯墊上施加不同的表面修整層的挑戰，以符合不同的焊料接合可靠性需求。因為該基體之C4側的雙表面修整層，故不需要一犧牲隔離層。
回到第4A圖，一多層基體51具有電介質區53及經過該電介質區之傳導路徑55以完成該等頂部及底部介面間之連接。為適合第1圖之範例，第4A圖之基體於該底部表面上具有BGA襯墊而該之後圖形中開發來支援該頂部表面之C4及POP襯墊連接。
第4A圖之範例中，該等C4連接位於左側而該等POP襯墊位於右側。該焊料阻劑程序已針對焊料阻劑56之頂層下的C4連接來完成以顯露並定義兩傳導通孔57。針對亦在該焊料阻劑之頂層下的POP襯墊具有兩傳導通孔59。該等POP襯墊連接通過該基體之一線路61至一長條邊緣。此對應第3圖中該等POP襯墊及該電解電鍍條48間之線段46。
第4A圖中，該左側C4連接區受遮蔽。該POP襯墊區接收一表面修整層，而該遮罩58保護該C4連接區。該遮罩可使用光阻或其他各種不同的保護薄膜之任何一種來完成。於一範例中，該遮罩可由一選擇性糊料印刷薄膜來組成。同樣地，該遮罩可使用光刻、印刷或其他技術來型樣化。另一替代方法中，準備該等表面之順序可被顛倒，使得該POP襯墊區首先完成，之後受遮蔽，而之後完成該C4連接區。
第4B圖中，一電解表面修整層已施加至該POP襯墊右 側之孔徑。此範例中，該表面修整層為一鎳金層。首先藉由遮蔽其他區以及施加一濕鎳離子浴來施加一鎳層63。接著藉由施加一濕金浴來形成一金層65。雖然顯示的是電解鎳金，但亦可施加其他各種不同的可用表面修整層來將該等POP襯墊之品質及功能最佳化。或者，亦可使用諸如電解鎳鈀金、電解鈀金、或電解鎳鈀、等等之其他各種不同的表面修整層。
第4C圖中，該左側C4連接區上之遮罩被移除而該右側POP襯墊區被遮蔽。該C4區接收一表面修整層，而該右側遮罩67保護該POP襯墊區。該遮罩可以與第4A圖及第4B圖之遮罩相同的方式來完成。兩種情況中，該遮罩型樣可由光刻技術或選擇性印刷或以其他各種不同的方式之任何一種來建立。
第4D圖中，一鎳、鈀之層69於完成該等C4接點之孔徑57上形成。之後一金之層71於該鎳、鈀層上形成。該鎳、鈀以一無電程序來施加而該金以一浸漬程序來施加。雖然繪示的是一鎳鈀金程序，但亦可根據該應用來使用適合C4連接之其他各種不同的修整層。
第4E圖中，該遮罩67從該POP襯墊區移除，而第4F圖中，C4焊料凸塊73施加於該等C4連接點上。該所生基體現在顯示具有兩種不同表面修整層之兩種不同的連接區類型。該繪示範例中，施加該等焊料凸塊前先移除該保護遮罩。此保護該遮罩免受該焊料凸塊程序的熱能。由於不同的遮罩材料，該遮罩可稍後移除。
上述操作之每一個典型可包括許多上述未提及之額外操作，諸如遮蔽、清除、列印、電鍍、蒸發、乾化、加熱、等等。該等操作不再詳細說明以簡化該說明。根據任何特別應用所用之特別表面修整層，該等操作可以各種不同的方式來修改。
第4A圖至第4F圖之操作可施加至具有兩種不同接點區之許多不同類型的基體。該類基體之另一範例為一無電基體。具有一DLL3(直接層及積層)-D型無電基體之一HDI POP的C4側亦呈現兩種不同的連接區。同時，該程序可促進與該兩連接區相對之該BGA側的一所需表面修整層。雖然各種不同的表面修整層均可用於該BGA側，一種可能性為一直接浸漬金(DIG)表面修整層。
第5A圖至第5J圖顯示一替代程序來達到HDI POP基體雙表面修整層。利用一DLL3-D型封裝程序，一C4區表面修整層(例如，鎳鈀金)可藉由僅將該C4區型樣化來先電解電鍍。該C4區電鍍完成並且該乾薄膜阻劑移除後，該POP襯墊區可針對一不同類型的電解表面修整層電鍍(例如，鎳金)來型樣化。該規則的HDI增進程序及焊料阻劑程序後，一不同的所需BGA襯墊表面修整層，諸如DIG(直接浸漬金)或OSP(有機可焊性防腐劑)可被施加。
參照第5圖，其顯示具有一型樣化乾薄膜阻劑(DFR)層81之一初始銅薄膜或薄片80。如下列圖形中所示，該初始薄片形成用以建立一無核心基體的基礎而最後被移除。該DFR層定義該C4接點焊料凸塊之位置。第5A圖中，該DFR層中之開口填滿一電解金鈀金層83。此可以各種不同的電解程序來完成，而該等層之特別組成可配適成適合不同的應用。第5C圖中，該DFR層被移除而留下該C4連接點位於該無核心基體上。
第5D圖中，於該基體上可型樣化一新的DFR層85。該新層覆蓋並保護該等C4連接區並定義該POP襯墊區之位置。第5E圖中，該型樣化DFR層85中之間隙具有沉積其間之一電解金鎳層87。此可以如上述第4B圖之脈絡中的各種不同方式來執行。該表面修整層之材料及程序的特別選擇可如所需配適成適合任何的特別實施例。
第5F圖中，若干新操作已施加至該無核心基體。首先，該DFR層85已移除。接著，電介層及傳導孔徑89以及互連體91於該C4及POP襯墊連接區上增進。該等層次透過一序列型樣化、沉積、蝕刻、及重複來增進。有各種不同的程序可用來達到該等層次。該等孔徑及互連體形成後，焊料阻劑93於該所生表面上型樣化。該焊料阻劑型樣化來定義該球格柵陣列之最終球的連接位置。最後第5F圖中，該型樣化焊料阻劑中之一球的每一開口以一層銅來覆蓋。該銅尚未具有一表面修整層。
第5G圖中，一適當的表面修整層95已施加至該BGA井。該表面修整層可為一BGA連接襯墊需要並適合的任何修整層。若該連接襯墊為另一類型，則可使用一不同的表面修整層。一DIG或OSP表面修整層可用於一實施例中。
第5H圖中，一保護薄膜99於該BGA井上積層。該薄膜可由PET(聚對苯二甲酸乙二酯)或其他各種不同材料所組成而本實施例中於該井上積層。該底部銅層80從該無核心基體之底側蝕刻時該積層可保護該BGA接點區。移除該底部銅層可曝露該C4襯墊區83及POP襯墊區87之接點區。由於第5F圖中加入之電介隔離層91，該底部接點襯墊位於反向井之內側。
第5I圖中，該保護薄膜99被移除。該圖顯示該無核心基體之頂部上曝露的BGA接點以及兩種不同類型的接點，該無核心基體之底部上的C4及POP襯墊。透過每一個井中之金表面修整層該頂部接點準備與焊料球接觸。該等POP襯墊具有一電解鎳金表面修整層以接收線結合之線路。該等C4襯墊準備供施加至該電解金、鈀、金表面修整層之C4焊料凸塊或微形球使用。第5J圖中，該等C4焊料凸塊101已適當施加於該無核心晶粒之底部表面上。
第5A圖至第5J圖之程序允許不同的表面修整層施加至一C4區、一POP襯墊及一BGA襯墊以符合不同的焊料接合可靠性需求。此外，一電解鎳金表面修整層可施加至該POP襯墊表面而不需將所有待連接之POP襯墊安排路由至一電解電鍍條。此可避免由曝露許多需連接至一共同條之銅軌跡造成的設計上困難及可靠性考量(參見例如第3圖46、48)。
第6圖是根據本發明之一實施例，於一基體上產生多個表面修整層之程序流程圖。第6圖中，方塊103中，一第一表面修整層施加至一基體之一第一區。該基體之第一區可為一低或高密度連接之介面。在一LDI區的情況中，該連接可為一POP襯墊區、一線結合區或一BGA區。該第一表面修整層可根據該連接區之特性來選擇。針對一LDI區，可使用諸如電解鎳金之一電解表面修整層等等。或者，可使用DIG、OSP及類似的修整層。
方塊105中，該基體之第一區受遮蔽。此完成後使得該基體具有一第二不同的連接區之一第二區曝露。該第二連接區可為與該第一連接區相同密度但具有不同的連接需求或者其可為一不同密度。例如，其可為一高密度區，諸如一C4連接區。
方塊107中，該第一區受遮罩時，一第二不同的表面修整層施加至該基體之第二區。在一C4連接區的情況中，可使用一無電表面修整層鎳鈀金。然而C4及其他類型連接區亦可使用其他類型的修整層。
方塊109中，該遮罩被移除，而方塊111中，該等連接區完成。此可藉由加入焊料球或凸塊、線連接額外襯墊、或適合該使用之特別連接區的其他某些結構來完成。
該等兩連接區可彼此相鄰或隔開。其可位於一基體之相同側或該基體之相對側。該低密度區可於該高密度區之前完成，反之亦然。如上述於一範例中，該第一連接層位於該基體之一頂部表面而該第二連接層位於該基體相對該頂部表面之一底部表面。
其他額外區可藉由遮蓋某些連接區並施加表面修整層至其他區來完成。
文中各種不同的操作可以多個分離的操作來說明以協助對本文的了解。然而，該說明順序不應視為暗示該等操作必須為相依順序。特別是，該等操作不需以該呈現順序來執行。說明之操作可以與該說明實施例不同的順序來執行。各種不同的額外操作可被執行而說明之操作可省略。
上述教示中可作許多修改及變化型態。圖中顯示之各種不同組件及操作可作各種不同的等效組合及替換。本發明之範疇不受限於該實施方式，而是由其後附申請專利範圍來設限。
上述之示範分層、覆蓋、蝕刻及型樣化程序僅提供作為示範。可有其他不同程序將不同的表面修整層施加至不同類型基體上之不同類型的連接區。該等特別類型連接區、封裝體、及表面修整層僅提供作為示範而亦可使用不同的選擇來適合不同的應用。
亦可使用比本文顯示及說明的表面修整層、封裝體及製造程序更簡單或更複雜的元件。因此，該組態可根據許多因素，諸如價格限制、效能需求、技術改良、或其他環境而於每個實施態樣中加以變化。本發明之實施例亦可應用在從不同類型的表面修整層受益之其他類型封裝體及連接。此外，本發明之實施例亦可應用在生產半導體、微電子元件、微機械元件及使用光刻技術之其他裝置中。
上述說明中，其提出許多特定細節。然而，應了解在無該等特定細節的情況下，本發明之實施例仍可加以實作。例如，習知的等效材料可替代本文說明之材料，而同樣地，習知的等效技術可替代本文揭示之特別處理技術。此外，某些步驟及操作可被移除或加入本文說明之操作中以改善結果或加入額外功能。其他實例中，習知之電路、架構及技術並不詳細顯示以避免混淆對本發明之了解。
雖然本發明之實施例已針對若干範例來加以說明，業界熟於此技者可體認本發明並不侷限於該說明之實施例中，而在該等後附申請專利範圍之精神及範疇中可以若干修改及交替來加以實作。因此本說明應視為舉例解說而非限制。
6‧‧‧第一晶粒、倒裝晶片晶粒
7、42-1、42-2、42-3、42-4‧‧‧C4連接區
8、40‧‧‧基體
8-1、12-1‧‧‧頂側
8-2、12-2‧‧‧底側
9、23‧‧‧外蓋或塗層
10‧‧‧封裝體
12‧‧‧第二基體
16‧‧‧晶粒或晶粒組合
16-1、16-2、16-3‧‧‧組件
18‧‧‧焊料球
19、34‧‧‧球格柵陣列
20‧‧‧插座
21‧‧‧連接襯墊
22‧‧‧連接、接觸襯墊
24、28‧‧‧線路襯墊
26、30、61‧‧‧線路
32、83‧‧‧C4連接區、HDI區
34‧‧‧LDI區
44-1、44-2、44-3、44-4‧‧‧POP襯墊連接區
46‧‧‧線路軌跡或線段
48‧‧‧電解電鍍條
51‧‧‧多層基體
53‧‧‧電介質區
55‧‧‧傳導路徑、通孔
56、93‧‧‧焊料阻劑
57、59、89‧‧‧傳導通孔
58、67‧‧‧遮罩
63‧‧‧鎳層
65‧‧‧金層
73‧‧‧焊料凸塊
80‧‧‧銅薄膜或薄片
81、85‧‧‧型樣化乾薄膜阻劑
83‧‧‧金鈀金層
87‧‧‧電解金鎳層、POP襯墊區
91‧‧‧互連體、隔離層
95‧‧‧表面修整層
99‧‧‧保護薄膜
101‧‧‧焊料凸塊
103、105、107、109、111‧‧‧方塊
第1圖是一根據本發明之一實施例的一疊合式封裝體裝置之側橫截面圖；
第2圖是一根據本發明之一實施例，具有兩種不同類型襯墊開口之一封裝體基體的頂視平面圖；
第3圖是一根據本發明之一實施例，具有兩種不同類型的襯墊開口以及周圍附近具有一連接條之一替代封裝體基體的頂視平面圖；
第4A圖是一根據本發明之一實施例，對一封裝體基體準備兩種不同表面修整層之一程序的橫截面圖；
第4B圖顯示根據本發明之一實施例，將一POP襯墊區表面修整層加入第4A圖之封裝體基體；
第4C圖顯示根據本發明之一實施例，將一保護遮罩加入該封裝體基體；
第4D圖顯示根據本發明之一實施例，將一表面修整層加入該封裝體基體之一C4連接區；
第4E圖顯示根據本發明之一實施例，從該封裝體基體移除該保護遮罩；
第4F圖顯示根據本發明之一實施例，將C4焊料凸塊加入該封裝體基體；
第5A圖是一根據本發明之一實施例，對一封裝體基體準備三種不同表面修整層之一替代程序的橫截面圖；
第5B圖顯示根據本發明之一實施例，將一表面修整層加入第5A圖之無核心基體的一C4連接區；
第5C圖顯示根據本發明之一實施例，從該無核心基體移除一抗蝕型樣；
第5D圖顯示根據本發明之一實施例，將一POP襯墊區之抗蝕型樣化加入該無核心基體；
第5E圖顯示根據本發明之一實施例，將一表面修整層加入該無核心基體之該C4連接區；
第5F圖顯示根據本發明之一實施例，將多層連接及電介質以及一抗蝕型樣加入該無核心基體；
第5G圖顯示根據本發明之一實施例，將一表面修整層加入該無核心基體之一BGA連接區；
第5H圖顯示根據本發明之一實施例，於該BGA連接區上施加一保護薄膜以及從該無核心基體之底部蝕刻一銅層；
第5I圖顯示根據本發明之一實施例，從該無核心基體移除該保護薄膜；
第5J圖顯示根據本發明之一實施例，將C4連接焊料凸塊施加至該無核心基體；
第6圖是一根據本發明之一實施例，於一基體上產生多個表面修整層之程序流程圖。
103、105、107、109、111．．．方塊

Claims (10)

  1. 一種用於施加微電子封裝體基體用多重表面修整層之方法，其包含下列步驟：將一第一表面修整層施加於一第一類型的連接襯墊，其設在一基體之一表面的一第一區中；在該基體之該第一區上形成一遮罩，而曝露該基體之該相同表面之一第二區，其中該基體之該第二區包含一高密度連接介面；將一不同的第二表面修整層施加於一第二類型的連接襯墊，其設在該基體之該第二區中，其中該第二表面修整層為一無電鎳鈀金表面修整層；以及移除該遮罩。
  2. 如申請專利範圍第1項之方法，其中該基體之該第一區為一低密度連接介面，而其中施加一第一表面修整層之步驟包含施加一電解表面修整層。
  3. 如申請專利範圍第1項之方法，其中該高密度連接介面包含一C4區。
  4. 如申請專利範圍第1項之方法，其更包含下列步驟：在該基體之該等第一及第二區上形成一遮罩；將一不同的第三修整層施加至該基體之一第三區；以及移除該遮罩。
  5. 如申請專利範圍第4項之方法，其中該基體之該等第一及第二區位於該基體之一頂部表面上，而該基體之該第 三區位於該基體與該頂部表面相對立之一底部表面上。
  6. 一種用於施加微電子封裝體基體用多重表面修整層之方法，其包含下列步驟：將一第一表面修整層施加於一第一類型的連接襯墊，其設在一基體之一第一區中；在該基體之該第一區上形成一遮罩，而曝露該基體之一第二區；將一不同的第二表面修整層施加於一第二類型的連接襯墊，其設在該基體之該第二區中；移除該遮罩；在該基體之該等第一及第二區上形成一第二遮罩；將一不同的第三表面修整層施加至該基體之一第三區；以及移除該第二遮罩，其中該第一區位於該基體之一頂部表面上，而該第三區位於該基體與該頂部表面相對立之一底部表面上。
  7. 一種疊合式封裝體用半導體基體，其具有位於一側上之一第一低密度連接區以及位於該一側上之一第二高密度連接區，該第一連接區具有一鎳金的第一表面修整層，該第一表面修整層係施加至該第一低密度連接區之連接襯墊，該第二連接區具有一鎳鈀金的第二表面修整層，該第二表面修整層係施加至該第二高密度連接區之連接 襯墊。
  8. 如申請專利範圍第7項之基體，其中該第一表面修整層為一電解表面修整層，而該第二表面修整層為一無電表面修整層。
  9. 如申請專利範圍第7項之基體，其更包含位於該基體之一第二側上的一第三連接區，該第三連接區具有一不同的第三修整層。
  10. 如申請專利範圍第9項之基體，其中該基體之該等第一及第二區位於一頂部表面上以連接至安裝於該基體之該頂部表面的晶粒，而該基體之該第三區位於該基體之一底部表面上以連接至一印刷電路板。
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JP5269563B2 (ja) * 2008-11-28 2013-08-21 新光電気工業株式会社 配線基板とその製造方法
TW201041105A (en) * 2009-05-13 2010-11-16 Advanced Semiconductor Eng Substrate having single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package

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WO2011087591A2 (en) 2011-07-21
KR20120098857A (ko) 2012-09-05
CN102598258B (zh) 2015-11-25
KR101405884B1 (ko) 2014-06-12
TW201126622A (en) 2011-08-01
WO2011087591A3 (en) 2011-10-20
US20110147933A1 (en) 2011-06-23
US8461036B2 (en) 2013-06-11

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