JP6625660B2 - 二層化された誘電体構造を有するパッケージ - Google Patents
二層化された誘電体構造を有するパッケージ Download PDFInfo
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- JP6625660B2 JP6625660B2 JP2017553263A JP2017553263A JP6625660B2 JP 6625660 B2 JP6625660 B2 JP 6625660B2 JP 2017553263 A JP2017553263 A JP 2017553263A JP 2017553263 A JP2017553263 A JP 2017553263A JP 6625660 B2 JP6625660 B2 JP 6625660B2
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- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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Description
ここに記載された二層誘電体構造(例えば、図1、3、又は4のパッケージアセンブリ121、308、436、又は444)を有する多層パッケージアセンブリ901を含むコンピューティング装置900の一例を模式的に示している。パッケージアセンブリ901は、例えば誘電体構造202などの二層誘電体構造を有する基板904を含み得る。基板904は、例えば図1に関して記述されたダイ102と同様とし得るダイ902と結合され得る。一部の実施形態において、ダイ902は、コンピューティング装置900のプロセッサを含み得る。一部の実施形態において、用語“プロセッサ”は、レジスタ及び/又はメモリからの電子データを処理して、該電子データをレジスタ及び/又はメモリに格納され得る他の電子データへと変換する如何なるデバイス又はデバイス部分をも指し得る。プロセッサは、様々な実施形態において、1つ以上の処理コアを含み得る。
例1は、集積回路(IC)パッケージアセンブリであって、当該ICパッケージアセンブリは、金属層と結合された誘電体構造を有し、前記誘電体構造は、第1の面と該第1の面とは反対側の第2の面とを有する第1の誘電体層であり、当該第1の誘電体層の前記第1の面と前記第2の面との間の距離が第1の厚さを規定し、当該第1の誘電体層は第1の誘電正接を有する、第1の誘電体層と、第1の面と該第1の面とは反対側の第2の面とを有する第2の誘電体層であり、当該第2の誘電体層の前記第1の面と前記第2の面との間の距離が第2の厚さを規定し、当該第2の誘電体層は第2の誘電正接を有する、第2の誘電体層とを含み、前記第1の誘電体層の前記第1の面が前記第2の誘電体層の前記第2の面と結合され、前記金属層が前記第1の誘電体層の前記第2の面と結合され、前記第1の誘電正接は前記第2の誘電正接よりも大きく、前記第1の厚さは前記第2の厚さよりも小さい、ICパッケージアセンブリを含み得る。
Claims (25)
- 集積回路(IC)パッケージアセンブリであって、
当該ICパッケージアセンブリは、金属層と結合された誘電体構造を有し、
前記誘電体構造は、
第1の面と該第1の面とは反対側の第2の面とを有する第1の誘電体層であり、当該第1の誘電体層の前記第1の面と前記第2の面との間の距離が第1の厚さを規定し、当該第1の誘電体層は第1の誘電正接を有する、第1の誘電体層と、
第1の面と該第1の面とは反対側の第2の面とを有する第2の誘電体層であり、当該第2の誘電体層の前記第1の面と前記第2の面との間の距離が第2の厚さを規定し、当該第2の誘電体層は第2の誘電正接を有する、第2の誘電体層と
を含み、
前記第1の誘電体層の前記第1の面が前記第2の誘電体層の前記第2の面と、これらの間の境界面に沿ったトレースを有さずに直に結合され、前記金属層が前記第1の誘電体層の前記第2の面と結合され、前記第1の誘電正接は前記第2の誘電正接よりも大きく、前記第1の厚さは前記第2の厚さよりも小さい、
ICパッケージアセンブリ。 - 前記第1の厚さは、1ミクロン以上且つ5ミクロン以下である、請求項1に記載のICパッケージアセンブリ。
- 前記第1の誘電体層は第1の分子セットで形成され、前記第2の誘電体層は第2の分子セットで形成され、且つ
前記第1の分子セット内の分子は、前記第2の分子セット内の分子よりも大きい電気的な分子双極子モーメントを有する、
請求項1に記載のICパッケージアセンブリ。 - 前記第1の誘電体層は、1ギガヘルツ以上且つ50ギガヘルツ以下の範囲での動作のために、0.005よりも大きい誘電正接を有する、請求項1乃至3の何れか一項に記載のICパッケージアセンブリ。
- 前記第2の誘電体層は、1ギガヘルツ以上且つ50ギガヘルツ以下の範囲での動作のために、0.003よりも小さい誘電正接を有する、請求項1乃至3の何れか一項に記載のICパッケージアセンブリ。
- 前記誘電体構造の前記第1の誘電体層及び前記第2の誘電体層を貫いて延在するビア構造、を更に有する請求項1乃至3の何れか一項に記載のICパッケージアセンブリ。
- 前記金属層は第1の金属層であり、当該ICパッケージアセンブリは更に、前記第2の誘電体層の前記第1の面と結合された第1の面を有する第2の金属層を有する、請求項6に記載のICパッケージアセンブリ。
- 前記誘電体構造は第1の誘電体構造であり、当該ICパッケージアセンブリは更に第2の誘電体構造を有し、当該第2の誘電体構造は、
第1の面と該第1の面とは反対側の第2の面とを有する第1の誘電体層であり、当該第2の誘電体構造の当該第1の誘電体層の前記第1の面と前記第2の面との間の距離が第1の厚さを規定し、当該第2の誘電体構造の当該第1の誘電体層は第1の誘電正接を有する、第1の誘電体層と、
第1の面と該第1の面とは反対側の第2の面とを有する第2の誘電体層であり、当該第2の誘電体構造の当該第2の誘電体層の前記第1の面と前記第2の面との間の距離が第2の厚さを規定し、当該第2の誘電体構造の当該第2の誘電体層は第2の誘電正接を有する、第2の誘電体層と
を含み、
前記第2の誘電体構造の前記第1の誘電体層の前記第1の面が、前記第2の誘電体構造の前記第2の誘電体層の前記第2の面と結合され、
前記第2の誘電体構造の前記第1の誘電体層の前記第2の面が、前記第2の金属層の第2の面と結合され、
前記第2の誘電体構造の前記第1の誘電正接は、前記第2の誘電体構造の前記第2の誘電正接よりも大きく、且つ
前記第2の誘電体構造の前記第1の厚さは、前記第2の誘電体構造の前記第2の厚さよりも小さい、
請求項7に記載のICパッケージアセンブリ。 - 前記ビア構造は、前記第1の誘電体構造の前記第1の誘電体層及び前記第2の誘電体層を貫いて延在する第1のビア構造であり、且つ
当該ICパッケージアセンブリは更に、前記第2の誘電体構造の前記第1の誘電体層及び前記第2の誘電体層を貫いて延在する第2のビア構造を有する、
請求項8に記載のICパッケージアセンブリ。 - 前記第1のビア構造は、前記第2のビア構造と電気的に結合されている、請求項9に記載のICパッケージアセンブリ。
- 集積回路(IC)パッケージアセンブリを製造する方法であって、当該方法は、
第1の面と該第1の面とは反対側の第2の面とを有する第1の誘電体層を含む誘電体構造を設けることであり、該誘電体構造は第2の誘電体層を含み、該第2の誘電体層は、第1の面と該第1の面とは反対側の第2の面とを有する、設けることと、
前記第1の誘電体層の前記第2の面に金属層を結合することと
を有し、
前記第1の誘電体層の前記第1の面と前記第2の面との間の距離が第1の厚さを規定し、
前記第1の誘電体層は第1の誘電正接を有し、
前記第2の誘電体層の前記第1の面と前記第2の面との間の距離が第2の厚さを規定し、
前記第2の誘電体層は第2の誘電正接を有し、
前記第1の誘電体層の前記第1の面が前記第2の誘電体層の前記第2の面と、これらの間の境界面に沿ったトレースを有さずに直に結合され、
前記第1の厚さは前記第2の厚さよりも小さく、且つ
前記第1の誘電正接は前記第2の誘電正接よりも大きい、
方法。 - 前記第1の誘電体層は、1ミクロン以上且つ5ミクロン以下の厚さを有する、請求項11に記載の方法。
- 前記第1の誘電体層は第1の分子セットで形成され、
前記第2の誘電体層は第2の分子セットで形成され、且つ
前記第1の分子セット内の分子は、前記第2の分子セット内の分子よりも大きい電気的な分子双極子モーメントを有する、
請求項11に記載の方法。 - 前記第1の誘電体層は、1ギガヘルツ以上且つ50ギガヘルツ以下の範囲での動作のために、0.005よりも大きい誘電正接を有する、請求項11乃至13の何れか一項に記載の方法。
- 前記第2の誘電体層は、1ギガヘルツ以上且つ50ギガヘルツ以下の範囲での動作のために、0.003よりも小さい誘電正接を有する、請求項11乃至13の何れか一項に記載の方法。
- 前記誘電体構造を貫くビア用の開口を形成すること、を更に有する請求項11乃至13の何れか一項に記載の方法。
- 前記開口を形成することは、レーザ穿孔プロセスを実行することを含む、請求項16に記載の方法。
- 前記開口をデスミア処理すること、を更に有する請求項16に記載の方法。
- 前記開口を充填するように金属を堆積すること、を更に有する請求項16に記載の方法。
- 前記誘電体構造は第1の誘電体構造であり、前記金属層は第1の金属層であり、当該方法は更に、
前記第1の誘電体構造の前記第2の誘電体層に第2の金属層を結合することと、
前記第2の金属層に第2の誘電体構造の第1の誘電体層を結合することと
を有し、
前記第2の誘電体構造の前記第1の誘電体層は、第1の面と該第1の面とは反対側の第2の面とを有し、
前記第2の誘電体構造の前記第1の誘電体層の前記第1の面と前記第2の面との間の距離が第1の厚さを規定し、
前記第2の誘電体構造の前記第1の誘電体層は第1の誘電正接を有し、
前記第2の誘電体構造は、第1の面と該第1の面とは反対側の第2の面とを有する第2の誘電体層を含み、
前記第2の誘電体構造の前記第2の誘電体層の前記第1の面と前記第2の面との間の距離が第2の厚さを規定し、
前記第2の誘電体構造の前記第2の誘電体層は第2の誘電正接を有し、
前記第2の誘電体構造の前記第1の誘電体層の前記第1の面が、前記第2の誘電体構造の前記第2の誘電体層の前記第2の面と結合され、
前記第2の誘電体構造の前記第1の誘電体層の前記第2の面が、前記第2の金属層の第2の面と結合され、
前記第2の誘電体構造の前記第1の誘電正接は、前記第2の誘電体構造の前記第2の誘電正接よりも大きく、且つ
前記第2の誘電体構造の前記第1の厚さは、前記第2の誘電体構造の前記第2の厚さよりも小さい、
請求項19に記載の方法。 - コンピューティング装置であって、
回路ボードと、
ダイと、
前記ダイと結合された第1の面と、前記回路ボードと結合された、前記第1の面とは反対側の第2の面と、を含む集積回路(IC)パッケージアセンブリと
を有し、
前記ICパッケージアセンブリは、金属層と結合された誘電体構造を有し、
前記誘電体構造は、
第1の面と該第1の面とは反対側の第2の面とを有する第1の誘電体層であり、当該第1の誘電体層の前記第1の面と前記第2の面との間の距離が第1の厚さを規定し、当該第1の誘電体層は第1の誘電正接を有する、第1の誘電体層と、
第1の面と該第1の面とは反対側の第2の面とを有する第2の誘電体層であり、当該第2の誘電体層の前記第1の面と前記第2の面との間の距離が第2の厚さを規定し、当該第2の誘電体層は第2の誘電正接を有する、第2の誘電体層と
を含み、
前記第1の誘電体層の前記第1の面が前記第2の誘電体層の前記第2の面と、これらの間の境界面に沿ったトレースを有さずに直に結合され、
前記金属層が前記第1の誘電体層の前記第2の面と結合され、
前記第1の誘電正接は前記第2の誘電正接よりも大きく、且つ
前記第1の厚さは前記第2の厚さよりも小さい、
コンピューティング装置。 - 前記第1の誘電体層は、1ミクロン以上且つ5ミクロン以下の厚さを有する、請求項21に記載のコンピューティング装置。
- 前記第1の誘電体層は第1の分子セットで形成され、前記第2の誘電体層は第2の分子セットで形成され、且つ
前記第1の分子セット内の分子は、前記第2の分子セット内の分子よりも大きい電気的な分子双極子モーメントを有する、
請求項21に記載のコンピューティング装置。 - 前記ICパッケージアセンブリは更に、前記誘電体構造の前記第1の誘電体層及び前記第2の誘電体層を貫いて延在するビア構造を有する、請求項21に記載のコンピューティング装置。
- 当該コンピューティング装置は、前記回路ボードと結合してディスプレイ、タッチスクリーンディスプレイ、タッチスクリーンコントローラ、バッテリー、グローバルポジショニングシステムデバイス、方位計、スピーカ、又はカメラを含んだモバイルコンピューティング装置である、請求項21に記載のコンピューティング装置。
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