CN111883513A - 芯片封装结构及电子设备 - Google Patents

芯片封装结构及电子设备 Download PDF

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Publication number
CN111883513A
CN111883513A CN202010565873.2A CN202010565873A CN111883513A CN 111883513 A CN111883513 A CN 111883513A CN 202010565873 A CN202010565873 A CN 202010565873A CN 111883513 A CN111883513 A CN 111883513A
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China
Prior art keywords
chip
pins
group
substrate
semiconductor substrate
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CN202010565873.2A
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English (en)
Inventor
武正辉
顾沧海
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Beijing Baidu Netcom Science and Technology Co Ltd
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Beijing Baidu Netcom Science and Technology Co Ltd
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Application filed by Beijing Baidu Netcom Science and Technology Co Ltd filed Critical Beijing Baidu Netcom Science and Technology Co Ltd
Priority to CN202010565873.2A priority Critical patent/CN111883513A/zh
Publication of CN111883513A publication Critical patent/CN111883513A/zh
Priority to US17/211,104 priority patent/US11594465B2/en
Priority to EP21164761.5A priority patent/EP3826051A3/en
Priority to JP2021077625A priority patent/JP2021119630A/ja
Priority to KR1020210076851A priority patent/KR20210082131A/ko
Pending legal-status Critical Current

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    • H01L2924/15332—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a pin array, e.g. PGA

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Abstract

本申请公开了芯片封装结构及电子设备，涉及人工智能芯片技术领域。具体方案为：通过在封装基板上设置半导体基板，并在半导体基板上设置第一组管脚和第二组管脚，且第一组管脚与第二组管脚之间通过连接层上的多个连接通道相连，设置在半导体基板上的第一芯片所具有的第三组管脚与第一组管脚相连，设置在半导体基板上的第二芯片所具有的第四组管脚与第二组管脚相连，由于第一组管脚和第二组管脚是相连的，从而，使得第一芯片的第三组管脚和第二芯片的第四组管脚是相连的，由此，实现了第一芯片与第二芯片的互联，解决了现有封装技术中在封装基板上封装芯片，难以实现芯片之间的互联的技术问题。

Description

芯片封装结构及电子设备
技术领域
本申请的实施例总体上涉及电子设备领域，并且更具体地，涉及人工智能芯片技术领域。
背景技术
人工智能(Artificial Intelligence，AI)芯片，也被称为AI加速器或计算卡，是专门用于处理人工智能应用中的大量计算任务的模块。
随着电子技术的发展，电子设备的更新换代越来越快，市场端对电子设备中使用的芯片的要求也越来越高。目前，对于芯片的封装，通常是将所需的芯片直接安装在封装基板上，实现多芯片的模块化。但是，在封装基板上封装芯片，难以实现芯片之间的互联。
发明内容
本申请提供了一种芯片封装结构及电子设备。
根据第一方面，提供了一种芯片封装结构，包括：
封装基板；
设置在所述封装基板之上的半导体基板，其中，所述半导体基板包括：
设置在所述半导体基板之上的第一组管脚和第二组管脚；
连接在所述第一组管脚和所述第二组管脚之间的连接层，其中，所述连接层具有多个连接通道，所述第一组管脚和所述第二组管脚之间通过所述多个连接通道相连；
设置在所述半导体基板之上的第一芯片和第二芯片，其中，所述第一芯片具有第三组管脚，所述第二芯片具有第四组管脚，所述第三组管脚分别与所述第一组管脚相连，所述第四组管脚分别与所述第二组管脚相连。
根据第二方面，提供了一种电子设备，包括：如前述第一方面实施例所述的芯片封装结构。
本申请提供的芯片封装结构及电子设备，存在如下有益效果：
通过在封装基板上设置半导体基板，并在半导体基板上设置第一组管脚和第二组管脚，且第一组管脚与第二组管脚之间通过连接层上的多个连接通道相连，设置在半导体基板上的第一芯片所具有的第三组管脚与第一组管脚相连，设置在半导体基板上的第二芯片所具有的第四组管脚与第二组管脚相连，由于第一组管脚和第二组管脚是相连的，从而，使得第一芯片的第三组管脚和第二芯片的第四组管脚是相连的，由此，实现了第一芯片与第二芯片的互联，解决了现有封装技术中在封装基板上封装芯片，难以实现芯片之间的互联的技术问题。
应当理解，本部分所描述的内容并非旨在标识本公开的实施例的关键或重要特征，也不用于限制本公开的范围。本公开的其它特征将通过以下的说明书而变得容易理解。
附图说明
附图用于更好地理解本方案，不构成对本申请的限定。其中：
图1是根据本申请第一实施例的芯片封装结构的结构示意图；
图2是根据本申请第二实施例的芯片封装结构的结构示意图；
图3是本申请一具体实施例的芯片封装结构的示例图。
具体实施方式
以下结合附图对本申请的示范性实施例做出说明，其中包括本申请实施例的各种细节以助于理解，应当将它们认为仅仅是示范性的。因此，本领域普通技术人员应当认识到，可以对这里描述的实施例做出各种改变和修改，而不会背离本申请的范围和精神。同样，为了清楚和简明，以下的描述中省略了对公知功能和结构的描述。
下面参考附图描述本申请的芯片封装结构及电子设备。
在芯片封装技术中，2D封装工艺将具有不同功能的有源电子元件与无源器件，以及诸如微机电系统(Micro Electromechanical System，MEMS)、光学器件等其他器件组装到一起，实现具有一定功能的单个标准封装件，形成一个系统或者子系统。2D封装工艺具有封装精度要求低、封装技术挑战小的特点，通过2D封装工艺得到的封装件尺寸较大。
摩尔定律对芯片性能的提升提出了要求，指出每18-24个月，芯片的尺寸缩小一半，性能提升一倍。随着电子技术和互联网技术的不断发展，市场端需要高性能、低功耗、小尺寸、低时延的芯片产品来满足大数据、人工智能等的需求。然而，2D封装工艺由于采用封装基板，将所需的芯片(即电子元件)直接放置在封装基板上，难以实现芯片之间的互联，并且，对于需求上万甚至更多的晶体管的设计，2D封装工艺得到的芯片尺寸越来越大，信号传输时延也越来越高，也无法满足芯片高密度、低功耗的设计要求。因此，现有的2D封装工艺无法满足摩尔定律的高性能、小尺寸要求。
针对上述问题，本申请公开了一种芯片封装结构，通过在封装基板上设置半导体基板，并在半导体基板上设置第一组管脚和第二组管脚，且第一组管脚与第二组管脚之间通过连接层上的多个连接通道相连，设置在半导体基板上的第一芯片所具有的第三组管脚与第一组管脚相连，设置在半导体基板上的第二芯片所具有的第四组管脚与第二组管脚相连，由于第一组管脚和第二组管脚是相连的，从而，第一芯片的第三组管脚和第二芯片的第四组管脚是相连的，由此，实现了第一芯片与第二芯片的互联。并且，通过将第一芯片和第二芯片设置在同一个半导体基板上且进行互联，缩短了两个芯片之间的距离，从而减少了信号的传输时间，使得信号传输的时延较小，而时延小反映过来即是信号传输速度比较快，相当于整个链路的吞吐量比较大，使得信号带宽更高。此外，当本申请的芯片封装结构包括多个半导体基板时，多个半导体基板之间可以叠加并连接，以在有限空间中满足芯片的高密度封装要求，节约封装面积，减小封装尺寸。因此，本申请提供的芯片封装结构，能够满足摩尔定律的高性能、小尺寸要求。
图1是根据本申请第一实施例的芯片封装结构的结构示意图。如图1所示，该芯片封装结构10包括：封装基板110、设置在封装基板110之上的半导体基板120，以及，设置在半导体基板120之上的第一芯片130和第二芯片140。
其中，如图1所示，半导体基板120之上设置有两组管脚，分别为第一组管脚和第二组管脚。半导体基板120上还包括连接层，该连接层连接在第一组管脚和第二组管脚之间，并且，该连接层具有多个连接通道，第一组管脚和第二组管脚之间通过多个连接通道相连。
本实施例中，设置在半导体基板120之上的第一芯片130具有第三组管脚(图1中未示出)，设置在半导体基板120之上的第二芯片140具有第四组管脚(图1中未示出)，其中，第三组管脚分别与第一组管脚相连，第四组管脚分别与第二组管脚相连。由于半导体基板120上的第一组管脚和第二组管脚之间是相连的，从而，第三组管脚分别与第一组管脚相连，第四组管脚分别与第二组管脚相连，使得第三组管脚与第四组管脚之间也是相连的，由此，实现了第一芯片与第二芯片之间的互联。
由于第一芯片130和第二芯片140互联且设置在同一个半导体基板120上，缩短了第一芯片130和第二芯片140之间的通信距离，一个芯片输出的信号能够快速地传输至另一芯片，减少了信号的传输时间，使得信号传输的时延较小，而时延小反映过来即是信号传输速度比较快，相当于整个链路的吞吐量比较大，使得信号带宽更高。因此，本申请实施例的芯片封装结构，相较于通过传统的2D封装工艺得到的封装件，不仅实现了芯片间的互联，还降低了时延，节约了能耗，带宽也更高。
需要说明的是，图1中仅以在半导体基板上设置第一芯片和第二芯片作为示例来解释说明本申请，而不能作为对本申请的限制。实际应用中，可以根据需要在半导体基板上设置多个芯片，实现多芯片的互联。
此外，图1中仅以芯片封装结构包括一个半导体基板作为示例来解释说明本申请，而不能作为对本申请的限制。实际应用中，可以根据需要设置多个半导体基板，每个半导体基板上可以设置多个芯片，多个半导体基板之间可以通过芯片工艺的重布线层技术连接，实现多个半导体基板之间的互联。重布线层技术是在晶圆表面沉积金属层和介质层并形成相应的金属布线图形，来对芯片的输入输出端口进行重新布局，将其布置在新的、节距占位可更为宽松的区域。通过采用重布线层技术连接多个半导体基板，使得多个半导体基板之间可以像累积木那样叠加，在有限空间中满足芯片的高密度封装要求，节约封装面积，减小封装尺寸，实现了芯片封装结构的小尺寸、高密度设计。
本申请实施例中，封装基板110可以是但不限于是焊球阵列封装(Ball GridArray，BGA)基板、多芯片模块(Multichip Module，MCM)基板等。
在本申请实施例一种可能的实现方式中，封装基板110可以为陶瓷基板。
陶瓷基板是指铜箔在高温下直接键合到氧化铝或氮化铝陶瓷基片表面上的特殊工艺板，具有优良的电绝缘性能和高导热特性，以及具有较高的附着强度和较大的载流能力。因此本申请实施例中，通过采用陶瓷基板作为封装基板来承载半导体基板，能够使得半导体基板牢固地附着在陶瓷基板上，并能够提高芯片封装结构的导热能力和电绝缘能力，提高芯片封装结构的可用性。
本申请实施例中，对于封装基板110和半导体基板120之间的连接，可以采用传统的芯片和封装基板的连接方式进行连接，复用目前成熟的封装工艺进行封装，能够降低封装难度，提高封装成功率。
在本申请实施例一种可能的实现方式中，第三组管脚分别通过多个第一金属球与第一组管脚相连，第四组管脚分别通过多个第二金属球与第二组管脚相连。
比如，对于第三组管脚中的每个管脚，该管脚通过一个第一金属球与第一组管脚中对应的一个管脚相连；对于第四组管脚中的每个管脚，该管脚通过一个第二金属球与第二组管脚中对应的一个管脚相连。
通过采用第一金属球连接第三组管脚和第一组管脚，采用第二金属球连接第四组管脚和第二组管脚，不仅实现了管脚之间的互联，从而实现芯片的互联，还提高了管脚连接的灵活性。
本申请实施例中，第一金属球和第二金属球的材质可以相同，也可以不同。比如，第一金属球可以是银，第二金属球可以是锡，或者，第一金属球和第二金属球可以都是银或锡。
在本申请实施例一种可能的实现方式中，多个第一金属球和多个第二金属球可以为锡。比如，可以采用体积很小的锡球作为第一金属球和第二金属球，分别连接第一组管脚与第三组管脚、第二组管脚与第四组管脚。由于采用的是体积很小的锡球，从而使得第一芯片130和第二芯片140与半导体基板120之间的缝隙较小，增加了芯片与半导体基板之间的连接密度。此外，由于金属锡的熔点较低，因此采用锡连接芯片和半导体基板，有利于保护半导体基板120不会在焊接时被损坏。
在本申请实施例一种可能的实现方式中，半导体基板120可以通过芯片工艺形成，连接层的多个连接通道可以通过布线工艺形成。
其中，芯片工艺的流程包括芯片设计、晶片制作、封装制作和测试几个环节。芯片设计即根据实际设计需求生成芯片图样；晶片制作包括晶圆制作、晶圆涂膜、晶圆光刻显影和蚀刻、掺加杂质和晶圆测试；在封装制作部分，将制作完成的晶圆固定，绑定引脚，按需制作成不同的封装形式；最后，对封装得到的芯片进行测试，剔除不良品，芯片制作完成。
本申请中，通过采用芯片工艺形成半导体基板，简化了半导体基板的制作过程，通过采用布线工艺形成多个连接通道，为通过半导体基板实现芯片之间的互联提供了条件。
在本申请实施例一种可能的实现方式中，半导体基板120采用的材质可以是硅，即使用硅基板作为承载第一芯片130和第二芯片140的载体。本实施例中，硅基板可以采用标准的数字芯片生产工艺制作而成，与其他芯片的制作不同的是，硅基板仅采用标准数字芯片生产工艺的有限几层金属层即可制作完成，也就是说，在硅晶圆外层镀少量几层的金属层，比如镀金，即可得到寿命较高的硅基板，制作工艺简单，成本低。由于硅基板的制作采用的是芯片生产工艺，硅基板的绕线资源非常丰富，可以预留多个接口，有利于扩展多个芯片，从而可以在硅基板上扩展多个芯片并实现芯片的互联，有利于提高芯片密度，节约成本。
封装好的芯片在使用过程中会发热，若散热能力不好，可能会损坏芯片，因此，在本申请实施例一种可能的实现方式中，芯片封装结构10还可以包括散热层(图1中未示出)，该散热层覆盖第一芯片130和第二芯片140。由此，通过在芯片封装结构中设置覆盖第一芯片130和第二芯片140的散热层，有利于芯片散热，从而延长芯片的使用寿命。
进一步地，在本申请实施例一种可能的实现方式中，散热层可以为散热胶。散热胶具有高导热率的优点，因此采用散热胶作为散热层来覆盖第一芯片和第二芯片，能够提高芯片封装结构的散热效率，从而提高芯片的易用性。
图2是根据本申请第二实施例的芯片封装结构的结构示意图。如图2所示，在如图1所示实施例的基础上，该芯片封装结构10还包括：
覆盖封装基板110的封装壳体150，以及，填充在封装壳体150之中的填充介质。
其中，图2中，灰色阴影区域表示填充介质，利用填充介质填充封装壳体150与封装基板110之间的区域，能够提高芯片封装结构的抗压能力，避免因压力过大导致封装基板110上的半导体基板120受损。
本实施例中，封装壳体150可以采用金属铁制成，并且制作成的封装壳体150可以较薄，以提高导热效率。
本申请实施例中，通过使用封装壳体覆盖封装基板，并在封装壳体中填充填充介质，能够提高芯片封装结构在安装、使用过程中的抗压能力。
图3是本申请一具体实施例的芯片封装结构的示例图。本示例中，第一芯片为专用集成电路(Application Specific Integrated Circuits，ASIC)，第二芯片为高带宽存储器(High Bandwidth Memory，HBM)。图3中，虚线围成的区域内为硅基板，硅基板上的白色条带即为本申请实施例中的管脚，ASIC和HBM通过管脚安装在硅基板上，通过硅基板实现ASIC和HBM之间的互联。在连接时，ASIC和HBM与硅基板之间采用微型的锡球来连接，以增加芯片与硅基板之间的连接密度，减小对空间的占用。图3中，封装基板上面的白色条带为过孔，硅基板与封装基板之间可以采用锡并通过过孔连接，以将硅基板封装在封装基板上，封装基板下方的锡球还可以用于与其他基板连接。如图3所示，硅基板上覆盖有高导热的散热胶，以提高散热效率，采用封装盖子(即本申请实施例中的封装壳体)覆盖封装基板，封装盖子可以采用超薄的铁盖来提高导热效率，同时还可以提高芯片安装、使用时的抗压能力。
需要说明的是，实际制作的芯片封装结构中，硅基板上的管脚、硅基板与封装基板之间的过孔，以及封装基板下方的锡球是无法看见的，图3中将其示出仅是为了方便理解芯片封装结构的组成，而不能作为对本申请的限制。
根据本申请的实施例，本申请还提供了一种电子设备。该电子设备包括前述实施例所述的芯片封装结构。
应该理解，可以使用上面所示的各种形式的流程，重新排序、增加或删除步骤。例如，本发申请中记载的各步骤可以并行地执行也可以顺序地执行也可以不同的次序执行，只要能够实现本申请公开的技术方案所期望的结果，本文在此不进行限制。
上述具体实施方式，并不构成对本申请保护范围的限制。本领域技术人员应该明白的是，根据设计要求和其他因素，可以进行各种修改、组合、子组合和替代。任何在本申请的精神和原则之内所作的修改、等同替换和改进等，均应包含在本申请保护范围之内。

Claims (10)

1.一种芯片封装结构，包括：
封装基板；
设置在所述封装基板之上的半导体基板，其中，所述半导体基板包括：
设置在所述半导体基板之上的第一组管脚和第二组管脚；
连接在所述第一组管脚和所述第二组管脚之间的连接层，其中，所述连接层具有多个连接通道，所述第一组管脚和所述第二组管脚之间通过所述多个连接通道相连；
设置在所述半导体基板之上的第一芯片和第二芯片，其中，所述第一芯片具有第三组管脚，所述第二芯片具有第四组管脚，所述第三组管脚分别与所述第一组管脚相连，所述第四组管脚分别与所述第二组管脚相连。
2.如权利要求1所述的芯片封装结构，其中，所述第三组管脚分别通过多个第一金属球与所述第一组管脚相连，所述第四组管脚分别通过多个第二金属球与所述第二组管脚相连。
3.如权利要求2所述的芯片封装结构，其中，所述多个第一金属球和所述多个第二金属球为锡。
4.如权利要求1所述的芯片封装结构，其中，所述半导体基板为硅。
5.如权利要求1所述的芯片封装结构，其中，还包括：
覆盖所述第一芯片和所述第二芯片的散热层。
6.如权利要求5所述的芯片封装结构，其中，所述散热层为散热胶。
7.如权利要求1所述的芯片封装结构，其中，所述半导体基板通过芯片工艺形成，所述多个连接通道通过布线工艺形成。
8.如权利要求1所述的芯片封装结构，其中，还包括：
覆盖所述封装基板的封装壳体；以及
填充在所述封装壳体之中的填充介质。
9.如权利要求1所述的芯片封装结构，其中，所述封装基板为陶瓷基板。
10.一种电子设备，其中，包括：
如权利要求1-9任一项所述的芯片封装结构。
CN202010565873.2A 2020-06-19 2020-06-19 芯片封装结构及电子设备 Pending CN111883513A (zh)

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