WO2022170775A1 - 一种功率结构体和制备方法以及设备 - Google Patents

一种功率结构体和制备方法以及设备 Download PDF

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Publication number
WO2022170775A1
WO2022170775A1 PCT/CN2021/122998 CN2021122998W WO2022170775A1 WO 2022170775 A1 WO2022170775 A1 WO 2022170775A1 CN 2021122998 W CN2021122998 W CN 2021122998W WO 2022170775 A1 WO2022170775 A1 WO 2022170775A1
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substrate
power
chip
power structure
disposed
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PCT/CN2021/122998
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English (en)
French (fr)
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张凯
徐佳慧
陈百友
姚伟伟
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华为技术有限公司
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Publication of WO2022170775A1 publication Critical patent/WO2022170775A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48229—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/117—Stacked arrangements of devices

Definitions

  • the present application relates to the field of circuit technology, and in particular, to a power structure, a preparation method, and a device.
  • Power management is constantly facing various demands of users. For example, users need more functions and higher performance, and users need to reduce the geometric size of power supply products to obtain reduced power supply products. Sometimes the multiple needs of users are conflicting, which requires better power solutions, such as conversion efficiency, transient response, noise power density, to meet stringent performance requirements and final product form factor requirements.
  • Power products can be applied in various fields, such as data center power supply, adapter power supply, inverter power supply, etc.
  • the power supply product may be a power supply in a package (PSIP).
  • PSIP can provide better performance without compromising conversion efficiency, transient response, and noise power density.
  • Power products have higher and higher requirements for power and application frequency, making power products continue to evolve towards high power, high frequency, and high power density.
  • PSIP continues to evolve towards high power, high frequency, and high power density.
  • the current power supply products cannot achieve the level of integration required by the industry, and it is difficult to adapt to the development trend of product miniaturization.
  • the parasitic parameters of the current power supply products are large, which cannot meet the needs of the high-frequency and high-power fields above megahertz.
  • Embodiments of the present application provide a power structure, a preparation method, and equipment, which are used to provide a power structure with a high degree of integration to meet the needs of the high-frequency and high-power field.
  • an embodiment of the present application provides a power structure, including: a first substrate, a second substrate, a driver chip, a power chip, and a conductive component, wherein a first surface of the first substrate and a second surface of the second substrate The surfaces are oppositely arranged; the first end of the conductive component is connected to the first surface, and the second end of the conductive component is connected to the second surface; the driving chip is arranged on the first substrate; the power chip is arranged on the second substrate.
  • the first substrate has a first surface
  • the second substrate has a second surface
  • the first surface and the second surface are disposed opposite to each other
  • the power chip is disposed on the second substrate, so that the power chip is located between the first substrate and the second substrate
  • the driver chip is disposed on the first substrate, so the power chip and the driver chip are disposed on the two substrates, and the power chip and the driver chip belong to the stack structure based on the two substrates, which improves the integration degree of the power structure.
  • the conductive member has a first end and a second end, the first end is connected to the first surface, the second end is connected to the second surface, the conductive member can connect the first substrate and the second substrate, and the conductive member conducts the first
  • the substrate and the second substrate can realize electrical transmission between the first substrate and the second substrate through the conductive parts, reduce the parasitic parameters of the power structure, and meet the requirements in the field of high frequency and high power.
  • the power structure body further includes: a package body, wherein the package body covers the first surface of the first substrate, the second substrate, the driver chip, and the power chip and the conductive parts.
  • the package body plays a role of encapsulating the internal structure of the power structure body.
  • the driver chip, the power chip and the conductive parts are all packaged into the package, so that a sealed power structure can be obtained.
  • the power structure may be a three-dimensional high-sealed package structure in which two substrates are interconnected by conductive members.
  • the driver chip is disposed on the first surface of the first substrate, or embedded in the first substrate; the power chip is disposed on the second surface of the second substrate.
  • the driver chip is located on the first surface and faces the second surface.
  • the driving chip and the power chip are arranged between the first substrate and the second substrate, the driving chip and the power chip are arranged on different planes, and the power structure is a three-dimensional structure. Device miniaturization and high integration of the power structure can be achieved.
  • the driving chip is disposed on the second surface of the second substrate; the power chip is disposed on the second surface of the second substrate.
  • the power structure includes a plurality of driver chips, some driver chips are arranged on the first substrate, some driver chips are arranged on the second substrate, and the driver chips and the power chips are arranged between the first substrate and the second substrate , the driving chip and the power chip are arranged on different planes, and the power structure is a three-dimensional structure. Device miniaturization and high integration of the power structure can be achieved.
  • the conductive member is located between the first surface and the second surface.
  • the conductive member may be a conductive post, and the conductive post is located between the first surface and the second surface.
  • the conductive member can also play a supporting role in addition to conducting electricity, so that the power chip and the driving chip can be arranged in the space between the first substrate and the second substrate.
  • the power structure further includes electronic components, and the electronic components may also be disposed in the space between the first substrate and the second substrate.
  • the first end is welded to the first surface, and the second end is welded to the second surface.
  • the first end is connected to the first surface by a first solder
  • the second end is connected to the second surface by a second solder.
  • the conductive member can be connected to the first substrate and the second substrate by solder, and the conductive member can be fixed with the first substrate and the second substrate by using the solder, so that the first substrate and the second substrate can be formed. space between substrates.
  • the power structure further includes: electronic components, wherein the electronic components are disposed on the first surface of the first substrate and/or the second surface of the second substrate.
  • the electronic component is specifically a first electronic component, wherein the first electronic component is disposed on the first surface and faces the second surface.
  • the first electronic component and the driving chip may be arranged side by side on the first surface of the first substrate, the first electronic component may be arranged in the space between the first substrate and the second substrate, the first electronic component It can be distributed on a different plane from the power chip, so the power structure is a three-dimensional structure, which is beneficial to the miniaturized design of the power structure.
  • the electronic component is specifically a second electronic component, and the second electronic component is disposed on the second surface and faces the first surface.
  • the second electronic component may be arranged side by side with the power chip on the second surface of the second substrate, the second electronic component may be arranged in the space between the first substrate and the second substrate, the second electronic component It can be distributed on a different plane from the driver chip, so the power structure is a three-dimensional structure, which is beneficial to the miniaturization design of the power structure.
  • there are multiple electronic components some electronic components are arranged on the first surface, and some electronic components are arranged on the second surface.
  • the electronic components can be arranged in the space between the first substrate and the second substrate, and the electronic components and the driver chips can be distributed on different planes. Therefore, the power structure is a three-dimensional structure, which is beneficial to the power structure. miniaturized design.
  • the power structure further includes: a heat dissipation module, wherein the heat dissipation module is disposed on the backside of the second substrate.
  • the second substrate includes a third surface
  • the second surface and the third surface of the second substrate are two opposite surfaces
  • the third surface of the second substrate is the opposite surface of the second substrate, for example, the third surface is used for setting cooling module.
  • the power chip and the heat dissipation module are respectively disposed on different surfaces of the second substrate.
  • the power chip is packaged by the package body, but the heat dissipation module is not packaged by the package body. Therefore, the heat dissipation module can be used to dissipate heat to a power structure, such as the power structure. It can be a three-dimensional high-density and high-thermal-conductivity package structure in which two substrates are interconnected through conductive parts.
  • the power structure further includes: a pad, wherein the pad is located on a fourth surface of the first substrate, and the fourth surface is a backside of the first surface.
  • the fourth surface and the first surface of the first substrate are opposite surfaces, and the fourth surface of the first substrate is the opposite surface of the first substrate, for example, the fourth surface is used for arranging the pads.
  • the driver chip and the pad are respectively disposed on different surfaces of the first substrate, the driver chip is packaged by the package body, but the pad is not packaged by the package body, and the pad can be used for electrical connection between the power structure and other external devices.
  • the first substrate is a first embedded substrate, wherein a driver chip is provided in the first embedded substrate.
  • the driver chip is embedded in the first embedded substrate, so only the power chip and conductive components need to be arranged between the first embedded substrate and the second substrate, which can further reduce the size of the power structure.
  • the volume is conducive to the miniaturized design of the power structure.
  • the power chip in which the "power chip is disposed on the second substrate" is referred to as the first power chip
  • the power structure further includes: a first power chip.
  • the first substrate is a second embedded substrate, wherein a second power chip is arranged in the second embedded substrate.
  • the driver chip can be disposed on the first surface of the second embedded substrate, and the second power chip can be disposed in the second embedded substrate, so the second embedded substrate and the second substrate Only a power chip, a conductive component and a driving chip need to be arranged in between, which can further reduce the volume of the power structure, which is beneficial to the miniaturized design of the power structure.
  • the power structure further includes: a third electronic element, the first substrate is a third embedded substrate, wherein a third electronic element is provided in the third embedded substrate.
  • the driver chip can be disposed on the first surface of the third embedded substrate, and the third electronic component is disposed in the third embedded substrate, so the third embedded substrate and the second substrate are Only a power chip, a conductive component and a driving chip need to be arranged in between, which can further reduce the volume of the power structure, which is beneficial to the miniaturized design of the power structure.
  • the power structure further includes: a third power chip, wherein the third power chip is located on the first surface and faces the second surface.
  • the power structure may include multiple power chips, for example, the power structure includes a power chip and a third power chip, the power chips are disposed on the second substrate, and the third power chip is disposed on the first substrate.
  • the third power chip may be disposed on the first surface of the first substrate side by side with the driving chip, the third power chip may be disposed in the space between the first substrate and the second substrate, and the third power chip may be distributed with the power chip
  • the power structure is a three-dimensional structure, which is beneficial to the miniaturized design of the power structure.
  • the second substrate is a ceramic copper clad laminate.
  • an embodiment of the present application further provides a power structure, comprising: a first substrate, a second substrate, a driver chip, a power chip, a conductive wire, a first package body, and an adhesive mold, wherein the power chip is located in the the second surface of the second substrate; the first package covers the second surface of the second substrate and the power chip; the first substrate is pasted on the first substrate by the adhesive mold on the package body; the driving chip is arranged on the first substrate; one end of the conductive wire is connected to the first substrate, and the other end of the conductive wire is connected to the second substrate.
  • the second substrate has a second surface
  • the power chip is located on the second surface
  • the first substrate is pasted on the first package body by an adhesive mold, so that the power chip is located between the first substrate and the second substrate, and the drive
  • the chip is arranged on the first substrate, so the power chip and the driver chip are arranged on the two substrates, and the power chip and the driver chip belong to a stack structure based on the two substrates, which improves the integration degree of the power structure.
  • the two ends of the conductive wire are respectively connected to the first substrate and the second substrate, and the electrical transmission between the first substrate and the second substrate can be realized through the conductive wire, so as to reduce the parasitic parameters of the power structure and meet the requirements in the field of high frequency and high power.
  • the power structure further includes: a conductive member, wherein a first end of the conductive member is connected to the second surface of the second substrate. The first end of the conductive member is connected to the second surface of the second substrate, so that the second substrate can output electrical signals through the conductive member.
  • the power structure further includes: a second package body, wherein the second package body covers the first substrate, the second surface of the second substrate, the driver chip, The power chip and the conductive member, wherein the second end of the conductive member exposes the second package body.
  • the second package plays a role of encapsulating the internal structure of the power structure.
  • the second package encapsulates the first substrate, the second surface, the driving chip, the power chip and the conductive wire, so that the The packaged power structure is obtained.
  • the package body encapsulates the space between the first substrate and the second substrate. Both the power chip and the conductive wires are packaged into the package, so that a sealed power structure can be obtained.
  • the ends of the conductive member are exposed to the second package body, so the conductive member can be used for electrical connection between the power structure and external devices.
  • the driving chip is disposed on the first surface of the first substrate, or embedded in the first substrate; the power chip is disposed on the second surface of the second substrate surface.
  • the driver chip is located on the first surface and faces the second surface.
  • the first surface is a surface of the first substrate away from the first package body.
  • the driving chip and the power chip are arranged between the first substrate and the second substrate, the driving chip and the power chip are arranged on different planes, and the power structure is a three-dimensional structure. Device miniaturization and high integration of the power structure can be achieved.
  • the driving chip is disposed on the second surface of the second substrate; the power chip is disposed on the second surface of the second substrate.
  • the power structure includes a plurality of driver chips, some driver chips are arranged on the first substrate, some driver chips are arranged on the second substrate, and the driver chips and the power chips are arranged between the first substrate and the second substrate , the driving chip and the power chip are arranged on different planes, and the power structure is a three-dimensional structure. Device miniaturization and high integration of the power structure can be achieved.
  • the power structure further includes: electronic components, wherein the electronic components are disposed on the first surface of the first substrate and/or the second surface of the second substrate , wherein the first surface is a surface of the first substrate away from the first package body.
  • the first electronic component is disposed on the first surface and faces the second surface.
  • the first electronic component and the driving chip may be arranged side by side on the first surface of the first substrate, the first electronic component may be arranged in the space between the first substrate and the second substrate, the first electronic component It can be distributed on a different plane from the power chip, so the power structure is a three-dimensional structure, which is beneficial to the miniaturized design of the power structure.
  • the electronic component is specifically a second electronic component, and the second electronic component is disposed on the second surface and faces the first surface.
  • the second electronic component may be arranged side by side with the power chip on the second surface of the second substrate, the second electronic component may be arranged in the space between the first substrate and the second substrate, the second electronic component It can be distributed on a different plane from the driver chip, so the power structure is a three-dimensional structure, which is beneficial to the miniaturization design of the power structure.
  • the electronic components are disposed on the first surface of the first substrate and the second surface of the second substrate.
  • there are multiple electronic components some electronic components are arranged on the first surface, and some electronic components are arranged on the second surface.
  • the electronic components can be arranged in the space between the first substrate and the second substrate, and the electronic components and the driver chips can be distributed on different planes. Therefore, the power structure is a three-dimensional structure, which is beneficial to the power structure. miniaturized design.
  • the power structure further includes: a heat dissipation module, wherein the heat dissipation module is disposed on the backside of the second surface of the second substrate.
  • the second substrate has a third surface
  • the second surface and the third surface of the second substrate are opposite surfaces
  • the third surface of the second substrate is the opposite surface of the second substrate, for example, the third surface is used for heat dissipation module.
  • the power chip and the heat dissipation module are respectively disposed on different surfaces of the second substrate.
  • the power chip is packaged by the package body, but the heat dissipation module is not packaged by the package body.
  • the heat dissipation module can be used to dissipate heat to a power structure, such as the power structure. It can be a three-dimensional high-density and high-thermal-conductivity package structure in which two substrates are interconnected through conductive parts.
  • the first substrate is a first embedded substrate, wherein a driver chip is provided in the first embedded substrate.
  • the driver chip is embedded in the first embedded substrate, so only the power chip and conductive components need to be arranged between the first embedded substrate and the second substrate, which can further reduce the size of the power structure.
  • the volume is conducive to the miniaturized design of the power structure.
  • the power chip in which the "power chip is disposed on the second substrate" is referred to as the first power chip
  • the power structure further includes: a first power chip.
  • the first substrate is a second embedded substrate, wherein a second power chip is arranged in the second embedded substrate.
  • the driver chip can be disposed on the first surface of the second embedded substrate, and the second power chip can be disposed in the second embedded substrate, so the second embedded substrate and the second substrate Only the power chip and the conductive member need to be arranged between, which can further reduce the volume of the power structure, which is beneficial to the miniaturized design of the power structure.
  • the power structure further includes: a third electronic element, the first substrate is a third embedded substrate, wherein a third electronic element is provided in the third embedded substrate.
  • the driver chip can be disposed on the first surface of the third embedded substrate, and the third electronic component is disposed in the third embedded substrate, so the third embedded substrate and the second substrate are Only the power chip and the conductive member need to be arranged between, which can further reduce the volume of the power structure, which is beneficial to the miniaturized design of the power structure.
  • the power structure further includes: a fourth electronic element, wherein the fourth electronic element is disposed on the first surface of the first substrate.
  • the fourth surface and the first surface of the first substrate are opposite surfaces, and the first surface of the first substrate is the opposite surface of the first substrate, for example, the fourth surface is used for arranging fourth electronic components.
  • the fourth electronic component can be arranged on the first surface of the first substrate, and the fourth electronic component and the power chip are distributed on different planes, so the power structure is a three-dimensional structure, which is conducive to the miniaturization design of the power structure.
  • the driver chip is located on the first surface of the first substrate.
  • the fourth surface and the first surface of the first substrate are opposite surfaces, the driver chip can be arranged on the first surface of the first substrate, and the driver chip and the power chip are distributed on different planes, Therefore, the power structure is a three-dimensional structure, which is beneficial to the miniaturized design of the power structure.
  • the power structure further includes: a third power chip, wherein the third power chip is located on the fourth surface and faces the second surface.
  • the power structure may include multiple power chips, for example, the power structure includes a power chip and a third power chip, the power chips are disposed on the second substrate, and the third power chip is disposed on the first substrate.
  • the third power chip is disposed on the fourth surface of the first substrate, the third power chip may be disposed in the space between the first substrate and the second substrate, and the third power chip may be distributed on a different plane from the power chip , so the power structure is a three-dimensional structure, which is beneficial to the miniaturized design of the power structure.
  • the second substrate is a ceramic copper clad laminate.
  • an embodiment of the present application further provides a method for preparing a power structure, including: placing a power chip on a second surface of a second substrate; wrapping a first package on a second surface of the second substrate the surface and the power chip; the first substrate is pasted on the first package body by an adhesive mold; the driving chip is placed on the first substrate; one end of the conductive wire is connected to the first substrate, so The other end of the conductive wire is connected to the second substrate.
  • the method further includes: connecting the first end of the conductive member with the second surface of the second substrate.
  • the method further includes: wrapping a second package body on the first substrate, the second surface of the second substrate, the driving chip, the power chip and the conductive component, wherein the second end of the conductive component exposes the second package body.
  • the placing the driver chip on the first substrate includes: arranging the driver chip on the first surface of the first substrate, or embedded in the first substrate Inside;
  • the placing the power chip on the second surface of the second substrate includes: placing the power chip on the second surface of the second substrate.
  • the method further includes: placing electronic components on the first surface of the first substrate, and/or placing the electronic components on the second surface of the second substrate, wherein the The first surface is a surface of the first substrate away from the first package body.
  • the method further includes: placing a heat dissipation module on the back of the second surface of the second substrate.
  • the power structure prepared in the method for preparing a power structure includes the steps described in the foregoing second aspect and various possible implementation manners. For details, see the foregoing for the second aspect and various possible implementations. Description of possible implementations.
  • an embodiment of the present application further provides an alternating current (AC) module, including: the power structure described in the first aspect or the second aspect.
  • AC alternating current
  • the embodiments of the present application further provide an energy device, including: the power structure described in the first aspect or the second aspect; or,
  • the energy equipment includes: the alternating current module according to the fourth aspect.
  • energy devices may include: site energy, network energy, data center energy, on board charger (OBC) energy, inverter energy (ie, photovoltaic energy), adapter energy, and the like.
  • OBC on board charger
  • inverter energy ie, photovoltaic energy
  • adapter energy and the like.
  • an embodiment of the present application further provides a remote radio unit (remote radio unit, RRU), including: the alternating current module described in the fourth aspect.
  • RRU remote radio unit
  • the embodiments of the present application have the following advantages:
  • the power structure includes: a first substrate, a second substrate, a driving chip, a power chip, and a conductive member.
  • the first substrate has a first surface
  • the second substrate has a second surface
  • the first surface and the second surface are arranged oppositely
  • the power chip is arranged on the second substrate, so that the power chip is located between the first substrate and the second substrate
  • the driver chip is disposed on the first substrate, so the power chip and the driver chip are disposed on two substrates, and the power chip and the driver chip belong to a stack structure based on two substrates, which improves the integration degree of the power structure.
  • the conductive member has a first end and a second end, the first end is connected to the first surface, the second end is connected to the second surface, the conductive member can connect the first substrate and the second substrate, and the conductive member conducts the first
  • the substrate and the second substrate can realize electrical transmission between the first substrate and the second substrate through the conductive parts, reduce the parasitic parameters of the power structure, and meet the requirements in the field of high frequency and high power.
  • the second substrate has a second surface
  • the power chip is located on the second surface
  • the first substrate is pasted on the first package body by an adhesive mold, so that the power chip is located between the first substrate and the second substrate
  • the driver chip is disposed on the first substrate, so the power chip and the driver chip are disposed on two substrates, and the power chip and the driver chip belong to a stack structure based on two substrates, which improves the integration degree of the power structure.
  • the two ends of the conductive wire are respectively connected to the first substrate and the second substrate, and the electrical transmission between the first substrate and the second substrate can be realized through the conductive wire, so as to reduce the parasitic parameters of the power structure and meet the requirements in the field of high frequency and high power.
  • FIG. 1 is a schematic structural diagram of a power structure provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a power structure including two conductive components provided by an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a power structure including a package provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a power structure including solder provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a power structure including a first electronic component provided by an embodiment of the present application
  • FIG. 6 is a schematic structural diagram of a power structure including a plurality of first electronic components provided by an embodiment of the present application
  • FIG. 7 is a schematic structural diagram of a power structure including a second electronic component provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a power structure including a plurality of second electronic components according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a power structure including a ceramic layer and a copper layer provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a power structure including a heat dissipation module provided by an embodiment of the present application;
  • FIG. 11 is a schematic structural diagram of a power structure including a pad provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a power structure including a first embedded substrate provided by an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a power structure including a second power chip provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a power structure including a third electronic element provided by an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of a power structure including a second power chip provided by an embodiment of the present application.
  • 16 is a schematic structural diagram of assembling a first power chip on a second substrate according to an embodiment of the present application
  • 17 is a schematic structural diagram of assembling a driving chip and a conductive component on a first substrate provided by an embodiment of the present application;
  • FIG. 18 is a schematic structural diagram including another power structure provided by an embodiment of the present application.
  • FIG. 19 is a schematic structural diagram of a power structure including a second package and a first package provided by an embodiment of the present application;
  • 20 is a schematic structural diagram of a power structure including a conductive component provided by an embodiment of the present application.
  • FIG. 21 is a schematic structural diagram of a power structure including a first electronic element provided by an embodiment of the present application.
  • 22 is a schematic structural diagram of a power structure including a second electronic component provided by an embodiment of the present application.
  • FIG. 23 is a schematic structural diagram of a power structure including a heat dissipation module provided by an embodiment of the present application.
  • 24 is a schematic structural diagram of a power structure including a first embedded substrate provided by an embodiment of the present application.
  • 25 is a schematic structural diagram of a power structure including a second power chip provided by an embodiment of the present application.
  • 26 is a schematic structural diagram of a power structure including a third electronic component provided by an embodiment of the present application.
  • FIG. 27 is a schematic structural diagram of a power structure including a fourth electronic component provided by an embodiment of the present application.
  • FIG. 28 is a schematic structural diagram of a power structure including a third power chip provided by an embodiment of the present application.
  • 29 is a schematic diagram of a method for preparing a power structure provided by an embodiment of the present application.
  • FIG. 30 is a schematic structural diagram of assembling a first power chip on a second substrate according to an embodiment of the present application.
  • FIG. 31 is a schematic structural diagram of a first package body packaged on a second substrate according to an embodiment of the present application.
  • the ceramic layer 1022 of the second substrate is the ceramic layer 1022 of the second substrate
  • Fourth electronic component 119 is a fourth electronic component.
  • Embodiments of the present application provide a power structure, a preparation method, and equipment, which are used to provide a power structure with a high degree of integration to meet the needs of the high-frequency and high-power field.
  • first, second and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, and this is only a way of distinguishing objects with the same attributes in the description of the embodiments of the present application.
  • the first substrate and the second substrate represent different two For each substrate, the first and the second do not depend on each other. In the case where the "first” is not described, the “second” can be described in the embodiment. Similarly, in the case where the "first” is described in the embodiment , you may not record "second".
  • An embodiment of the present application provides a power structure, and the power structure refers to a structural unit including a power chip.
  • the power structure may be a power module, a power component, a power structural unit, etc.
  • the power A structure can also be defined as a structural unit with other names, for example, a power structure can be a module, an apparatus, a device, a terminal, a device, etc., and the specific implementation is not limited.
  • the power structure provided by the embodiments of the present application includes a power chip, wherein the power chip may also be referred to as a "power semiconductor chip", and a power chip refers to a chip that can generate power in a power-on state.
  • the specific implementation of the power chip is related to the application scenario of the power structure.
  • the type of power chips included in the power structure the number of power chips, and the arrangement of the power chips in the power structure.
  • the connection method of the power chip with other electronic components and other chips in the power structure body needs to be determined in combination with the specific application scenario of the power structure body.
  • the power structure may be a power supply in a package (PSIP)
  • the power chip may be a metal-oxide-semiconductor field-effect transistor (MOSFET).
  • the power structure provided by the embodiments of the present application includes a dual substrate, a driver chip, a power chip, and a conductive component.
  • the substrate in the embodiment of the present application may be a printed circuit board (printed circuit board, PCB).
  • Double substrate refers to two substrates, which are respectively defined as a first substrate and a second substrate.
  • the first substrate and the second substrate can be two substrates arranged opposite to each other, and there is a certain space between the two substrates, that is, the two substrates There is a certain distance between them, and the value of the distance is not limited here.
  • the first substrate and the second substrate are respectively substrates with circuit functions, and the first substrate and the second substrate are also used for fixing chips.
  • one of the first substrate and the second substrate may be referred to as an upper substrate, and the other substrate of the first substrate and the second substrate may be referred to as a lower substrate.
  • the first substrate may be a lower substrate, and the second substrate may be an upper substrate.
  • the upper substrate and the lower substrate are defined based on the distribution positions of the space where the substrates are located, and are not limited to the embodiments of the present application.
  • the second substrate may be a substrate with a heat dissipation function, for example, the second substrate may be a ceramic direct bonding copper (DBC), for example, the DBC includes a ceramic layer and a copper layer.
  • DBC is a substrate made by directly sintering copper foil on the ceramic surface. DBC can be used in high-power power semiconductor modules, power control circuits, power hybrid circuits, intelligent power components, high-frequency switching power supplies, solid state relays, solar panel components, etc.
  • a driver chip may be disposed on the first substrate, for example, the driver chip may be disposed on the surface of the first substrate.
  • the first substrate may be an embedded substrate, and the embedded substrate adopts an embedded component packaging (ECP) to embed electronic components and chips (eg, driver chips, power chips) inside the substrate.
  • ECP embedded component packaging
  • the power structure includes a driver chip.
  • the driver chip refers to a chip component used to drive the power chip.
  • the driver chip stores a driver program. After the driver chip is powered on and runs, the driver chip can run. The driver, through which the operation of the power chip is driven.
  • the power structure includes one or more power chips, and specifically, the power chips in the power structure need to be determined according to the application scenario.
  • the power structure includes a first power chip.
  • the first power chip and the driving chip are respectively disposed on different substrates in the power structure.
  • the power structure body includes double substrates, and the first power chip and the driving chip are respectively arranged on one substrate. It can be seen from the foregoing description of the dual substrates that the two substrates in the dual substrate are arranged opposite to each other, and the first power chip and the driver chip are arranged on different substrates, so the first power chip and the driver chip are not distributed on the same plane. The first power chip and the driver chip are distributed on different planes.
  • the power structure provided in the embodiment of the present application is a three-dimensional structure.
  • This distribution of the first power chip and the driver chip can improve the integration of the power structure. , which reduces the space volume of the power structure and can adapt to the development trend of device miniaturization.
  • the power structure includes a first power chip and a second power chip, and the substrates on which the first power chip and the second power chip are located are different.
  • the power structure includes a conductive member, and the conductive member can conduct the first substrate and the second substrate, that is, the conductive member can interconnect the dual substrates, so that the chips mounted on the dual substrates can be electrically transmitted, for example The signal transmission between the chips mounted on the dual substrates can be realized through the conductive parts.
  • the material of the conductive member may be copper or other conductive metal material, which is not limited here.
  • the conductive components provided in the embodiments of the present application have various shapes, as long as the conductive components can realize the function of dual-substrate interconnection.
  • the cross-section of the conductive member has various shapes, for example, the cross-section of the conductive member may be L-shaped, mouth-shaped, circular, rhombus, and the like.
  • the conductive member in addition to the conductive function, may also have a supporting function.
  • the conductive member is supported between the two substrates, so that a space of a certain size can be formed between the two substrates. Parts can be accommodated in this space.
  • the power structure may include one or more packages.
  • the power structure includes multiple packages, for example, two packages, the two packages are respectively defined as second packages body and the first package body.
  • the chips in the power structure need to be packaged to obtain a package, which can encapsulate the surface of the substrate, the power chip, the driver chip, and the conductive components.
  • the package refers to a housing for mounting semiconductor integrated circuit chips. It can play the role of placing, fixing, sealing, protecting the chip and enhancing the thermal conductivity.
  • the package may be a plastic package obtained by plastic-encapsulating the surface of the substrate, the power chip, the driving chip, and the conductive component.
  • the encapsulation body may be an encapsulation layer.
  • the power structure may include electronic components, and the electronic components are required components in the power structure.
  • the electronic components in the power structure may be one or more.
  • the electronic components may be at least one of the following components: resistors, capacitors, and inductors.
  • the implementation manner of the electronic components is not limited in the embodiments of the present application.
  • the power structure includes a plurality of electronic components, for example, includes two electronic components, the two electronic components are respectively defined as a first electronic component and a second electronic component.
  • the deployment positions and roles of the first electronic component and the second electronic component in the power structure are different, as described in the following embodiments for details.
  • the second substrate is a substrate with a heat dissipation function
  • a heat dissipation module is disposed on the second substrate, and the heat dissipation module can be used for heat dissipation of the power chip.
  • the heat dissipation module can provide heat dissipation channels for the chips assembled on the upper substrate.
  • the heat dissipation module in the embodiment of the present application includes, but is not limited to, the heat dissipation module is a heat dissipation material, or the heat dissipation module is provided with a heat dissipation channel, and the like.
  • a power structure provided in an embodiment of the present application includes: a first substrate, a second substrate, a driver chip, a power chip, and a conductive component, wherein,
  • the first surface of the first substrate and the second surface of the second substrate are arranged oppositely;
  • the first end of the conductive part is connected to the first surface, and the second end of the conductive part is connected to the second surface;
  • the driving chip is disposed on the first substrate
  • the power chip is arranged on the second substrate.
  • the power chip in which the "power chip is disposed on the second substrate" is referred to as the first power chip.
  • the first power chip is located on the second surface and faces the first surface.
  • the conductive parts play the role of conducting and supporting, and the first surface of the first substrate is the main surface where the chips are arranged, for example, the first substrate The first surface faces up.
  • the driver chip is disposed on the first substrate, for example, the driver chip is located on the first surface and faces the second surface.
  • the second surface of the second substrate is the main surface on which the chips are disposed, for example, the second surface of the second substrate faces downward, there is a space between the first surface and the second surface, and the driving chip and the first power chip are disposed on the first substrate and the second surface. between the second substrates.
  • the first power chip may be connected to the second substrate by solder.
  • the conductive part has a first end and a second end, the first end and the second end are the upper and lower ends of the conductive part, the first end is connected to the first surface, and the second end is connected to the second surface, so that the conductive part can be connected a first substrate and a second substrate.
  • the driving chip and the first power chip are arranged on different planes, and the power structure is a three-dimensional structure.
  • the conductive member can conduct the first substrate and the second substrate, thereby reducing the transmission path between the first substrate and the second substrate, and reducing the parasitic parameters of the power structure. Based on the power structure shown in FIG. 1 , device miniaturization and high integration of the power structure can be achieved.
  • the driving chip is disposed on the first surface of the first substrate, or is embedded in the first substrate; the power chip is disposed on the second surface of the second substrate.
  • the driver chip is located on the first surface and faces the second surface.
  • the driving chip may be embedded in the first substrate, as described in the subsequent embodiments for details.
  • the driving chip and the power chip are arranged between the first substrate and the second substrate, the driving chip and the power chip are arranged on different planes, and the power structure is a three-dimensional structure. Device miniaturization and high integration of the power structure can be achieved.
  • the embodiments of the present application do not limit the number and distribution positions of the conductive components in the power structure, do not limit the number and distribution positions of the driver chips in the power structure, and do not limit the first
  • the number and distribution position of a power chip can be specifically determined in combination with the application scenario, and this is just an example.
  • the power structure includes two conductive parts, and each of the two conductive parts plays a role of conducting and supporting the first substrate and the second substrate.
  • the two conductive members have a left-right symmetrical structure.
  • the power structure includes one conductive member, and the one conductive member plays the role of conducting and supporting the first substrate and the second substrate. It is not limited that, in the embodiment of the present application, the conductive components included in the power structure body may also be other numbers.
  • the power structure further includes: a package, wherein,
  • the package body covers the first surface of the first substrate, the second substrate, the driving chip, the power chip and the conductive parts.
  • the encapsulation body plays a role in encapsulating the internal structure of the power structure.
  • the encapsulation body encapsulates the first surface of the first substrate, the second substrate, the driving chip, the power chip and the conductive components, so that the packaged body can be obtained after encapsulation. power structure.
  • the encapsulation of the second substrate may cover one surface or multiple surfaces of the second substrate, for example, the encapsulation may encapsulate the first surface of the first substrate, the second surface of the second substrate, and the drive Chips, power chips and conductive parts.
  • the package body covers the second surface and the side surface of the second substrate. In another example, the package body encapsulates the space between the first substrate and the second substrate.
  • the driving chip, the first power chip and the conductive components are all packaged into the package, so that a sealed power structure can be obtained.
  • the power structure may be a three-dimensional high-sealed package structure in which two substrates are interconnected by conductive members.
  • the conductive member conducts the first substrate and the second substrate.
  • the conductive member can also play a supporting role for the substrate, and the conductive member is located between the first surface and the second surface.
  • the conductive features may be conductive pillars located between the first surface and the second surface.
  • the conductive member can also play a supporting role in addition to conducting electricity, so that the power chip and the driving chip can be arranged in the space between the first substrate and the second substrate.
  • the power structure further includes electronic components, and the electronic components may also be disposed in the space between the first substrate and the second substrate.
  • the power structure further includes solder, wherein the first end is soldered to the first surface by solder, and the second end is soldered to the second surface by solder.
  • solders are referred to as the first solder and the second solder according to the different positions of the solder.
  • the first end is connected to the first surface by the first solder
  • the second end is Solder is connected to the second surface. Therefore, the conductive member can be connected to the first substrate and the second substrate through solder, and the conductive member can be fixed to the first substrate and the second substrate by using the solder, so that the connection between the first substrate and the second substrate can be formed. space.
  • the power structure further includes: electronic components, wherein the electronic components are disposed on the first surface of the first substrate and/or the second surface of the second substrate.
  • the electronic components are respectively referred to as a first electronic component, a second electronic component, and a third electronic component according to the different distribution positions and connection relationships of the electronic components.
  • the electronic component is specifically a first electronic component.
  • the power structure further includes: a first electronic component, wherein,
  • the first electronic element is disposed on the first surface and faces the second surface.
  • the first electronic component and the driving chip may be arranged side by side on the first surface of the first substrate, the first electronic component may be arranged in the space between the first substrate and the second substrate, and the first electronic component may be arranged with the first substrate
  • a power chip is distributed on different planes, so the power structure is a three-dimensional structure, which is beneficial to the miniaturization design of the power structure.
  • the number of the first electronic components is not limited.
  • the package body covers the first surface of the first substrate, the second substrate, the driver chip, the first power chip, the conductive component and the first electronic element.
  • the power structure body includes four first electronic components for illustration.
  • the four first electronic components may be arranged side by side with the driver chip.
  • the distribution mode on the first surface of the first substrate is not limited, and the types of the four first electronic components are not limited.
  • the package body covers the first surface of the first substrate, the second substrate, the driver chip, the first power chip, the conductive member and the 4 first electronic components.
  • Electronic component when the power structure further includes 4 first electronic components, the package body covers the first surface of the first substrate, the second substrate, the driver chip, the first power chip, the conductive member and the 4 first electronic components.
  • the power structure further includes: a second electronic component, wherein,
  • the second electronic element is disposed on the second surface and faces the first surface.
  • the second electronic component may be arranged side by side with the first power chip on the second surface of the second substrate, the second electronic component may be arranged in the space between the first substrate and the second substrate, and the second electronic component may be
  • the power structure and the driver chip are distributed on different planes, so the power structure is a three-dimensional structure, which is beneficial to the miniaturization design of the power structure.
  • the number of the second electronic components is not limited.
  • the package body covers the first surface of the first substrate, the second substrate, the driver chip, the first power chip, the conductive component and the second electronic component.
  • FIG. 7 differs between FIG. 7 and FIG. 5.
  • the first electronic components are distributed on the first substrate, and the second electronic components are distributed in the second substrate.
  • the power structure body includes four second electronic components for illustration.
  • the four second electronic components may be arranged side by side with the driver chip.
  • the distribution mode on the second surface of the second substrate is not limited, and the types of the four second electronic components are not limited.
  • the package body covers the first surface of the first substrate, the second substrate, the driver chip, the first power chip, the conductive member and the 4 second electronic components.
  • Electronic component when the power structure further includes 4 second electronic components, the package body covers the first surface of the first substrate, the second substrate, the driver chip, the first power chip, the conductive member and the 4 second electronic components.
  • the second substrate may be a substrate with a heat dissipation function
  • the second substrate may be DBC
  • the DBC includes a ceramic layer and a copper layer.
  • the ceramic layer can be encapsulated by the package body, and the surface of the copper layer is not encapsulated by the package body, so the DBC can realize the heat dissipation function.
  • the power structure further includes: a heat dissipation module, wherein,
  • the heat dissipation module is disposed on the back of the second surface of the second substrate.
  • the second substrate has a third surface
  • the second surface and the third surface of the second substrate are two opposite surfaces
  • the third surface of the second substrate is the opposite surface of the second substrate, for example, the third surface is used for setting cooling module.
  • the first power chip and the heat dissipation module are respectively disposed on different surfaces of the second substrate, the first power chip is packaged by the package body, but the heat dissipation module is not packaged by the package body, so the heat dissipation module can be used for heat dissipation of the power structure, for example
  • the power structure may be a three-dimensional high-density and high-thermal-conductivity package structure interconnecting two substrates through conductive parts.
  • the power structure further includes: a pad, wherein,
  • the pad is located on the fourth surface of the first substrate
  • the fourth surface is the backside of the first surface.
  • the fourth surface and the first surface of the first substrate are opposite surfaces, and the fourth surface of the first substrate is the opposite surface of the first substrate, for example, the fourth surface is used for arranging pads.
  • the driver chip and the pad are respectively arranged on different surfaces of the first substrate, the driver chip is encapsulated by the package body, but the pad is not encapsulated by the package body, and the pad can be used for electrical connection between the power structure and other external devices.
  • the distribution positions of the pads on the fourth surface and the number of the pads are not limited.
  • the driver chip may be embedded in the first substrate.
  • the first substrate is a first embedded substrate, wherein,
  • a driver chip is arranged in the first embedded substrate.
  • the driver chip is embedded in the first embedded substrate, so only the first power chip and the conductive component need to be arranged between the first embedded substrate and the second substrate, and further Reducing the volume of the power structure is beneficial to the miniaturized design of the power structure.
  • the power chip may be embedded in the first substrate.
  • the power structure further includes: a second power chip,
  • the first substrate is a second embedded substrate, wherein,
  • a second power chip is arranged in the second embedded substrate.
  • the driver chip can be disposed on the first surface of the second embedded substrate, and the second power chip is disposed in the second embedded substrate, so the second embedded substrate and the Only the first power chip, the conductive component and the driving chip need to be arranged between the second substrates, which can further reduce the volume of the power structure, which is beneficial to the miniaturized design of the power structure.
  • FIG. 12 the difference between FIG. 12 and FIG. 13 is that the units embedded in the embedded substrate are different.
  • a driver chip is provided in the first embedded substrate
  • a second power chip is provided in the second embedded substrate. It is not limited that the driver chip and the second power chip can also be embedded in the embedded substrate in the power structure, which is not limited here.
  • the power structure further includes: a third electronic component,
  • the first substrate is a third embedded substrate, wherein,
  • a third electronic component is arranged in the third embedded substrate.
  • the driver chip can be disposed on the first surface of the third embedded substrate, and the third electronic component is disposed in the third embedded substrate, so the third embedded substrate and the Only the first power chip, the conductive component and the driving chip need to be arranged between the second substrates, which can further reduce the volume of the power structure, which is beneficial to the miniaturized design of the power structure.
  • FIG. 13 the difference between FIG. 13 and FIG. 14 is that the units embedded in the embedded substrate are different.
  • the second power chip is provided in the second embedded substrate
  • the third electronic component is provided in the third embedded substrate. It is not limited that the second power chip and the third electronic component may be embedded in the embedded substrate in the power structure, which is not limited here.
  • the power structure further includes: a third power chip, wherein,
  • the third power chip is located on the first surface and faces the second surface.
  • the power structure may include multiple power chips, for example, the power structure includes a first power chip and a third power chip, the first power chip is disposed on the second substrate, and the third power chip is disposed on the first substrate .
  • the third power chip may be disposed on the first surface of the first substrate side by side with the driving chip, the third power chip may be disposed in the space between the first substrate and the second substrate, and the third power chip may be disposed with the first power chip
  • the chips are distributed on different planes, so the power structure is a three-dimensional structure, which is beneficial to the miniaturized design of the power structure.
  • the power structure is described in the foregoing embodiments, and the alternating current module provided by the embodiment of the present application is described next.
  • the alternating current module includes the power structure shown in FIG. 1 to FIG. 15 .
  • the alternating current module has the advantages of small size, high integration and small parasitic parameters.
  • the energy device includes: based on the power structure shown in FIG. 1 to FIG. 15 ;
  • the energy equipment includes the aforementioned alternating current module.
  • the energy device has the advantages of small size, high integration and small parasitic parameters.
  • the remote radio unit includes: the aforementioned alternating current module.
  • the remote radio unit has the advantages of small size, high integration and small parasitic parameters.
  • the first substrate has a first surface
  • the second substrate has a second surface
  • the first surface and the second surface are disposed opposite to each other
  • the power chip is disposed on the second substrate, so that the power chip is located on the first substrate
  • the driver chip is arranged on the first substrate, so the power chip and the driver chip are arranged on the two substrates.
  • the power chip and the driver chip belong to the stack structure based on the two substrates, which improves the integration of the power structure. Spend.
  • the conductive member has a first end and a second end, the first end is connected to the first surface, the second end is connected to the second surface, the conductive member can connect the first substrate and the second substrate, and the conductive member conducts the first
  • the substrate and the second substrate can realize electrical transmission between the first substrate and the second substrate through the conductive parts, reduce the parasitic parameters of the power structure, and meet the requirements in the field of high frequency and high power.
  • the power structure provided by the embodiments of the present application can be applied to wireless 5G enhanced multiple-input multiple-output (massive multiple-input multiple-output) products, so as to improve the packaging integration of the power structure and solve the problem of heat dissipation of high-frequency and high-power devices at the same time. and large parasitic parameters.
  • the power structure provided by the embodiments of the present application is a three-dimensional high-density and high-thermal-conductivity packaging structure using conductive components to interconnect two substrates, stacking and sealing multiple chips, improving the packaging integration, and the upper-lower interconnection structure reduces the signal transmission path.
  • the upper substrate of the stack structure is designed with a heat dissipation structure, which is suitable for the field of high frequency and high power.
  • the power structure of the embodiment of the present application includes: a lower substrate with a circuit function, an upper substrate with a heat dissipation function, a driver chip (or a driver function chip), a power chip, and a conductive column.
  • the power structure may further include: other required electronic components and a package.
  • a plurality of chips are assembled on the upper substrate.
  • one side of the lower substrate is equipped with a driver chip.
  • the other side of the lower substrate is provided with pads to realize the electrical connection between the power structure and other components, and other components can be assembled on the upper and lower substrates as needed.
  • the upper and lower substrates with heat dissipation function are interconnected by conductive pillars. The electrical transmission of the chip on the upper substrate is realized by the conductive column, and the three-dimensional multi-chip stacking and sealing is completed after plastic sealing.
  • the upper substrate has a heat dissipation function, which can provide a heat dissipation channel for the power chips assembled on the upper substrate.
  • the use of conductive pillars to interconnect the upper and lower substrates shortens the transmission path of each signal, reduces parasitic parameters applied in the high frequency field, and the stacked power structure simultaneously improves the integration degree of the package.
  • the upper and lower substrates are assembled by using conductive pillars in an inverted manner.
  • the processing technology of this packaging form includes three parts: the respective assembly of the upper and lower substrates and the assembly of the double substrates.
  • the assembly of the upper and lower substrates is done through interconnection processes, such as D die attach, wire bonding, and surface mount technology (SMT) to complete the assembly of chips, components and substrates.
  • SMT surface mount technology
  • the electrical connection between the upper and lower substrates is realized through conductive pillars (such as copper pillars) and interconnect structures (such as solder), and a power structure is formed by plastic molding at the last time.
  • a heat dissipation module can be assembled on the upper substrate.
  • the lower substrate may be a substrate embedded with chips or other electronic components.
  • the power structure is a multi-chip stacked two-substrate three-dimensional packaging structure, which improves the packaging density and reduces the packaging size.
  • the upper substrate with heat dissipation function provides a good heat dissipation channel, which solves the difficulty of 3D packaging heat dissipation; the package structure stacked up and down reduces parasitic parameters and expands the application in the high-frequency field, and there is no direct signal transmission between the upper substrate and the outside world. , has the function of electrical isolation.
  • An embodiment of the present application further provides a power structure body, the power structure body includes: a first substrate, a second substrate, a driving chip, a power chip and a conductive component, wherein,
  • the first surface of the first substrate and the second surface of the second substrate are disposed opposite to each other;
  • the first end of the conductive member is connected to the first surface, and the second end of the conductive member is connected to the second surface;
  • the power chip is disposed on the second substrate
  • the driving chip is disposed on the second substrate.
  • the driver chip may be disposed on the second substrate, for example, the driver chip is located on the second surface and faces the first surface.
  • the power structure includes: a first substrate, a second substrate, a driving chip, a power chip and a conductive member.
  • the second substrate has a second surface
  • the power chip is located on the second surface and faces the first surface, so that the power chip is located between the first substrate and the second substrate, and the driving chip is arranged on the second substrate, which improves the power structure body integration.
  • the conductive member has a first end and a second end, the first end is connected to the first surface, the second end is connected to the second surface, the conductive member can connect the first substrate and the second substrate, and the conductive member conducts the first
  • the substrate and the second substrate can realize electrical transmission between the first substrate and the second substrate through the conductive parts, reduce the parasitic parameters of the power structure, and meet the requirements in the field of high frequency and high power.
  • the power structure includes: a first substrate, a second substrate , the driver chip, the power chip, the conductive wire, the first package body and the adhesive mold, wherein,
  • the power chip is located on the second surface of the second substrate
  • a conductive wire for conducting the first substrate and the second substrate
  • the driving chip is disposed on the first substrate.
  • the power structure further includes: a conductive member, wherein a first end of the conductive member is connected to the second surface of the second substrate. The first end of the conductive member is connected to the second surface of the second substrate, so that the second substrate can output electrical signals through the conductive member.
  • the power chip in which the "power chip is located on the second surface of the second substrate" is referred to as the first power chip.
  • the first power chip is located on the second surface.
  • the conductive member plays a conductive role
  • the first surface is the surface of the first substrate away from the first package body, for example, the first surface of the first substrate face down.
  • the fourth surface is a surface of the first substrate close to the first package body, for example, the fourth surface of the fourth substrate faces upward.
  • the second surface of the second substrate is the main surface for arranging the chips, for example, the second surface of the second substrate faces downward, there is a space between the fourth surface and the second surface, and the first power chip is disposed on the first substrate and the second surface. Between the two substrates, the first substrate and the first power chip are fixed together.
  • the first substrate and the first power chip are directly fixed together, or the first power chip is packaged and then fixed to the first substrate.
  • the first power chip may be connected to the second substrate by solder.
  • the conductive member may conduct the first substrate and the second substrate.
  • the driving chip and the first power chip are arranged on different planes, and the power structure is a three-dimensional structure.
  • the conductive member can conduct the first substrate and the second substrate, thereby reducing the transmission path between the first substrate and the second substrate, and reducing the parasitic parameters of the power structure. Based on the power structure shown in FIG. 18 , device miniaturization and high integration of the power structure can be achieved.
  • the first package body covers the second surface of the second substrate and the first power chip, and the packaging process of the first package body and the aforementioned second package body may be the same or different.
  • a first package body is obtained, and the first substrate is pasted on the first package body through an adhesive mold, so the first substrate can pass through the first package body and the adhesive mold.
  • the first power chips are fixed together, and the material and thickness of the adhesive mold are not limited.
  • the embodiments of the present application do not limit the number and distribution positions of the conductive components in the power structure, do not limit the number and distribution positions of the driver chips in the power structure, and do not limit the first
  • the number and distribution position of a power chip can be specifically determined in combination with the application scenario, and this is just an example.
  • the power structure further includes: a second package body, wherein the second package body covers the first substrate, the second surface of the second substrate, the driver chip and the power chip.
  • the power structure further includes: a conductive member, wherein a first end of the conductive member is connected to the second surface of the second substrate.
  • the second package body covers the first substrate, the second surface of the second substrate, the driving chip, the power chip and the conductive member. Wherein, the second end of the conductive member is exposed to the second package body.
  • the second package plays a role of encapsulating the internal structure of the power structure.
  • the second package encapsulates the first substrate, the second surface of the second substrate, the driver chip, the first power chip and the conductive wires , so that the packaged power structure can be obtained.
  • the second package body encapsulates the space between the first substrate and the second substrate. Both the first power chip and the conductive wires are packaged into the second package, so that a sealed power structure can be obtained.
  • the power structure may be a three-dimensional high-sealed package structure in which two substrates are interconnected by conductive members. After being encapsulated by the second package body, the ends of the conductive member are exposed to the second package body, so the conductive member can be used for electrical connection between the power structure and external devices.
  • the power structure body includes two conductive components as an example. It is not limited that the number of conductive components may also be one or more, which is not limited here.
  • the power structure further includes: electronic components, wherein the electronic components are disposed on the first surface of the first substrate and/or the second surface of the second substrate.
  • the electronic components are respectively referred to as the first electronic component, the second electronic component, and the third electronic component according to the different distribution positions and connection relationships of the electronic components.
  • the electronic component is specifically a first electronic component.
  • the power structure further includes: a first electronic component, wherein,
  • the first electronic element is disposed on the fourth surface and faces the second surface.
  • the first electronic component is arranged on the fourth surface of the first substrate
  • the driving chip is arranged on the first surface of the first substrate
  • the first electronic component may be arranged in the space between the first substrate and the second substrate , the first electronic element and the first power chip can be distributed on different planes, so the power structure is a three-dimensional structure, which is beneficial to the miniaturized design of the power structure.
  • the number of the first electronic components is not limited.
  • the second package covers the first substrate, the second surface, the driver chip, the first power chip, the conductive wire, the conductive component and the first electronic component.
  • the driver chip is disposed on the first surface of the first substrate, or embedded in the first substrate; the power chip is disposed on the second surface of the second substrate .
  • the driver chip is located on the first surface and faces the second surface.
  • the first surface is a surface of the first substrate away from the first package body.
  • the driving chip and the power chip are arranged between the first substrate and the second substrate, the driving chip and the power chip are arranged on different planes, and the power structure is a three-dimensional structure. Device miniaturization and high integration of the power structure can be achieved.
  • the driving chip is disposed on the second surface of the second substrate; the power chip is disposed on the second surface of the second substrate.
  • the power structure includes a plurality of driver chips, some driver chips are arranged on the first substrate, some driver chips are arranged on the second substrate, and the driver chips and the power chips are arranged between the first substrate and the second substrate , the driving chip and the power chip are arranged on different planes, and the power structure is a three-dimensional structure. Device miniaturization and high integration of the power structure can be achieved.
  • the power structure further includes: a second electronic component, wherein,
  • the second electronic element is disposed on the second surface and faces the fourth surface.
  • the second electronic component may be arranged side by side with the first power chip on the second surface of the second substrate, the second electronic component may be arranged in the space between the first substrate and the second substrate, and the second electronic component may be
  • the power structure and the driver chip are distributed on different planes, so the power structure is a three-dimensional structure, which is beneficial to the miniaturization design of the power structure.
  • the number of the second electronic components is not limited.
  • the second package covers the first substrate, the second surface, the driving chip, the first power chip, the conductive component and the second electronic element.
  • the power structure further includes: a heat dissipation module, wherein,
  • the heat dissipation module is disposed on the back of the second surface of the second substrate.
  • the second substrate has a third surface
  • the second surface and the third surface of the second substrate are two opposite surfaces
  • the third surface of the second substrate is the opposite surface of the second substrate, for example, the third surface is used for setting cooling module.
  • the first power chip and the heat dissipation module are respectively disposed on different surfaces of the second substrate, the first power chip is packaged by the package body, but the heat dissipation module is not packaged by the package body, so the heat dissipation module can be used for heat dissipation of the power structure, for example
  • the power structure may be a three-dimensional high-density and high-thermal-conductivity package structure interconnecting two substrates through conductive parts.
  • the driver chip may be embedded in the first substrate.
  • the first substrate is a first embedded substrate, wherein,
  • a driver chip is arranged in the first embedded substrate.
  • the driver chip is embedded in the first embedded substrate, so only the first power chip and the conductive member need to be arranged between the first embedded substrate and the second substrate, and further Reducing the volume of the power structure is beneficial to the miniaturized design of the power structure.
  • the power chip may be embedded in the first substrate.
  • the power structure further includes: a second power chip,
  • the first substrate is a second embedded substrate, wherein,
  • a second power chip is arranged in the second embedded substrate.
  • the driver chip can be disposed on the first surface of the second embedded substrate, and the second power chip is disposed in the second embedded substrate, so the second embedded substrate and the Only the first power chip and the conductive member need to be arranged between the second substrates, which can further reduce the volume of the power structure, which is beneficial to the miniaturized design of the power structure.
  • FIG. 25 the difference between FIG. 25 and FIG. 24 is that the units embedded in the embedded substrate are different.
  • a driver chip is provided in the first embedded substrate
  • a second power chip is provided in the second embedded substrate. It is not limited that the driver chip and the second power chip can also be embedded in the embedded substrate in the power structure, which is not limited here.
  • the power structure further includes: a third electronic component,
  • the first substrate is a third embedded substrate, wherein,
  • a third electronic component is arranged in the third embedded substrate.
  • the driver chip can be arranged on the first surface of the third embedded substrate, and the third electronic component is arranged in the third embedded substrate, so the third embedded substrate and the Only the first power chip and the conductive member need to be arranged between the second substrates, which can further reduce the volume of the power structure, which is beneficial to the miniaturized design of the power structure.
  • FIG. 25 the difference between FIG. 25 and FIG. 26 is that the units embedded in the embedded substrate are different.
  • the second power chip is provided in the second embedded substrate
  • the third electronic component is provided in the third embedded substrate. It is not limited that the second power chip and the third electronic component may be embedded in the embedded substrate in the power structure, which is not limited here.
  • the power structure further includes: a fourth electronic component, wherein,
  • the fourth electronic element is disposed on the first surface of the first substrate.
  • the fourth surface and the first surface of the first substrate are opposite surfaces, and the first surface of the first substrate is the opposite surface of the first substrate, for example, the fourth surface is used for arranging fourth electronic components.
  • the fourth electronic component can be arranged on the first surface of the first substrate, and the fourth electronic component and the first power chip are distributed on different planes, so the power structure is a three-dimensional structure, which is beneficial to the miniaturization design of the power structure .
  • the driving chip is located on the first surface of the first substrate.
  • the fourth surface and the first surface of the first substrate are opposite surfaces, the driver chip can be arranged on the first surface of the first substrate, and the driver chip and the first power chip are distributed on different planes, therefore
  • the power structure is a three-dimensional structure, which is beneficial to the miniaturized design of the power structure.
  • the power structure further includes: a third power chip, wherein,
  • the third power chip is located on the fourth surface and faces the second surface.
  • the power structure may include multiple power chips, for example, the power structure includes a first power chip and a third power chip, the first power chip is disposed on the second substrate, and the third power chip is disposed on the first substrate .
  • the third power chip is disposed on the fourth surface of the first substrate, the third power chip may be disposed in the space between the first substrate and the second substrate, and the third power chip may be distributed in a different place from the first power chip Therefore, the power structure is a three-dimensional structure, which is beneficial to the miniaturized design of the power structure.
  • the power structure is described in the foregoing embodiments, and the alternating current module provided by the embodiment of the present application is described next.
  • the alternating current module includes: based on the power structure shown in FIGS. 18 to 28 .
  • the alternating current module has the advantages of small size, high integration and small parasitic parameters.
  • the energy device includes: based on the power structure shown in FIG. 18 to FIG. 28 ;
  • the energy device includes the aforementioned alternating current module.
  • the energy device has the advantages of small size, high integration and small parasitic parameters.
  • the remote radio unit includes: the aforementioned alternating current module.
  • the remote radio unit has the advantages of small size, high integration and small parasitic parameters.
  • the second substrate has a second surface
  • the power chip is located on the second surface
  • the first substrate is pasted on the first package body by an adhesive mold, so that the power chip is located between the first substrate and the second substrate.
  • the driver chip is disposed on the first substrate, so the power chip and the driver chip are disposed on the two substrates, and the power chip and the driver chip belong to the stack structure based on the two substrates, which improves the integration degree of the power structure.
  • the two ends of the conductive wire are respectively connected to the first substrate and the second substrate, and the electrical transmission between the first substrate and the second substrate can be realized through the conductive wire, so as to reduce the parasitic parameters of the power structure and meet the requirements in the field of high frequency and high power.
  • the method for preparing the power structure shown in FIG. 18 to FIG. 28 is introduced. As shown in FIG. 29, the method mainly includes the following processes:
  • the first substrate is pasted on the first package body by an adhesive mold
  • One end of the conductive wire is connected to the first substrate, and the other end of the conductive wire is connected to the second substrate.
  • the method further includes:
  • the first end of the conductive member is connected to the second surface of the second substrate.
  • the method further includes:
  • the second end of the conductive member is exposed to the second package body.
  • placing the driver chip on the first substrate includes:
  • the placing the power chip on the second surface of the second substrate includes:
  • the power chip is disposed on the second surface of the second substrate.
  • the method further includes:
  • the first surface is a surface of the first substrate away from the first package body.
  • the heat dissipation module is placed on the back of the second surface of the second substrate.
  • FIG. 29 can manufacture the power structures shown in FIGS. 18 to 28 .
  • the method shown in FIG. 29 can manufacture the power structures shown in FIGS. 18 to 28 .
  • the manufacturing process of the power structures in the embodiments of the present application please refer to the foregoing embodiments for details. It is not repeated in the method embodiment hereof.
  • the second substrate has a second surface
  • the power chip is located on the second surface
  • the first substrate is pasted on the first package body by an adhesive mold, so that the power chip is located between the first substrate and the second substrate.
  • the driver chip is disposed on the first substrate, so the power chip and the driver chip are disposed on the two substrates, and the power chip and the driver chip belong to the stack structure based on the two substrates, which improves the integration degree of the power structure.
  • the two ends of the conductive wire are respectively connected to the first substrate and the second substrate, and the electrical transmission between the first substrate and the second substrate can be realized through the conductive wire, so as to reduce the parasitic parameters of the power structure and meet the requirements in the field of high frequency and high power.
  • the power structure provided by the embodiments of the present application can be applied to wireless 5G enhanced multiple-input multiple-output (massive multiple-input multiple-output) products, so as to improve the packaging integration of the power structure and solve the problem of heat dissipation of high-frequency and high-power devices at the same time. and large parasitic parameters.
  • the power structure provided by the embodiments of the present application is a three-dimensional high-density and high-thermal-conductivity packaging structure using conductive components to interconnect two substrates, stacking and sealing multiple chips, improving the packaging integration, and the upper-lower interconnection structure reduces the signal transmission path.
  • the upper substrate of the stack structure is designed with a heat dissipation structure, which is suitable for the field of high frequency and high power.
  • the power structure of the embodiment of the present application includes: a lower substrate with circuit function, an upper substrate with heat dissipation function, a driver chip (or driver function chip), a power chip, and conductive wires.
  • the power structure may further include: other required electronic components, as well as a second package body, a first package body, and conductive components.
  • this embodiment changes the double-substrate upside-down packaging mode, the substrates are stacked and assembled, and the power chips are assembled on the upper substrate with heat dissipation function. Then, plastic sealing of the power chip part is performed to obtain a first package body, as shown in FIG. 31 . And stick a layer of adhesive film on the surface of the first package body, and then assemble the lower substrate with the driver chip mounted on the first package body, complete the electrical interconnection process as needed, and finally use the second package body for packaging to obtain The power structure shown in Fig. 18.
  • the conductive parts assembled on the upper substrate are used for signal transmission of the power chip, and the conductive parts exposed after plastic encapsulation are used for the electrical interconnection between the power structure and the outside.
  • the power structure is a multi-chip stacked two-substrate three-dimensional packaging structure, which improves the packaging density and reduces the packaging size.
  • the upper substrate with heat dissipation function provides a good heat dissipation channel, which solves the difficulty of 3D packaging heat dissipation; the package structure stacked up and down reduces parasitic parameters and expands the application in the high-frequency field, and there is no direct signal transmission between the upper substrate and the outside world. , has the function of electrical isolation.
  • the device embodiments described above are only schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be A physical unit, which can be located in one place or distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • the connection relationship between the modules indicates that there is a communication connection between them, which can be specifically implemented as one or more communication buses or signal lines.
  • U disk mobile hard disk
  • ROM read-only memory
  • RAM magnetic disk or optical disk
  • a computer device which may be a personal computer, server, or network device, etc.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general purpose computer, special purpose computer, computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server, or data center Transmission to another website site, computer, server, or data center is by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.).
  • wire eg, coaxial cable, fiber optic, digital subscriber line (DSL)
  • wireless eg, infrared, wireless, microwave, etc.
  • the computer-readable storage medium may be any available medium that can be stored by a computer, or a data storage device such as a server, data center, etc., which includes one or more available media integrated.
  • the usable media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, DVD), or semiconductor media (eg, Solid State Disk (SSD)), and the like.

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Abstract

本申请实施例公开了一种功率结构体和制备方法以及设备，用于提供集成度高的功率结构体，满足高频大功率领域的需求。本申请实施例提供一种功率结构体，包括：第一基板，第二基板，驱动芯片，功率芯片和导电部件，其中，第一基板的第一表面和第二基板的第二表面相对设置；导电部件的第一端与第一表面连接，导电部件的第二端与第二表面连接；驱动芯片设置于第一基板；功率芯片设置于第二基板。

Description

一种功率结构体和制备方法以及设备
本申请要求于2021年02月10日提交中国专利局、申请号为202110184049.7、发明名称为“一种功率结构体和制备方法以及设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电路技术领域，尤其涉及一种功率结构体和制备方法以及设备。
背景技术
电源管理中不断面向用户的多种需求，例如用户需要更多的功能和更高的性能，用户需要减小电源产品的几何尺寸，以获得缩小的电源产品。有时用户的多种需求又是相互冲突的，这就需要更优的电源解决方案，例如转换效率，瞬态响应，噪声功率密度，以满足严格的性能要求和最终产品的外形尺寸需求。
电源产品可以应用于多种领域，例如数据中心电源，适配器电源，逆变器电源等。例如电源产品可以是封装级电源(power supply in a package，PSIP)。PSIP可以提供较优的性能，无需在转换效率，瞬态响应，噪声功率密度方面进行折衷。
电源产品对功率和应用频率的要求越来越高，使得电源产品不断的向大功率，高频率，高功率密度的方向演进。例如，PSIP不断的朝着大功率，高频率，高功率密度的方向演进。
目前的电源产品无法做到业界所需的集成度，难以适应产品小型化的发展趋势。另外，目前的电源产品的寄生参数大，不能满足兆赫兹以上的高频大功率领域的需求。
发明内容
本申请实施例提供了一种功率结构体和制备方法以及设备，用于提供集成度高的功率结构体，满足高频大功率领域的需求。
为解决上述技术问题，本申请实施例提供以下技术方案：
第一方面，本申请实施例提供一种功率结构体，包括：第一基板，第二基板，驱动芯片，功率芯片和导电部件，其中，第一基板的第一表面和第二基板的第二表面相对设置；导电部件的第一端与第一表面连接，导电部件的第二端与第二表面连接；驱动芯片设置于第一基板；功率芯片设置于第二基板。
在上述方案中，第一基板具有第一表面，第二基板具有第二表面，第一表面和第二表面相对设置，功率芯片设置于第二基板，从而功率芯片处于第一基板和第二基板之间，另外驱动芯片设置于第一基板，因此功率芯片和驱动芯片设置在两个基板上，功率芯片和驱动芯片属于基于两个基板的堆叠结构，提高了功率结构体的集成度。导电部件具有第一端和第二端，第一端与第一表面连接，第二端与第二表面连接，该导电部件可以将第一基板和第二基板连接起来，导电部件导通第一基板与第二基板，通过导电部件可实现第一基板和第二基板之间的电气传输，降低功率结构体的寄生参数，满足高频大功率领域的需求。
在一种可能的实现方式中，功率结构体还包括：封装体，其中，封装体包覆于所述第一基板的第一表面，所述第二基板，所述驱动芯片，所述功率芯片和所述导电部件。在上 述方案中，封装体起到对功率结构体的内部结构的封装作用。驱动芯片，功率芯片和导电部件都被封装到该封装体中，从而可以得到密封的功率结构体。例如该功率结构体可以是通过导电部件互连双基板的三维高密封装结构。
在一种可能的实现方式中，驱动芯片设置于所述第一基板的第一表面，或者嵌入于所述第一基板之内；所述功率芯片设置于所述第二基板的第二表面。例如，驱动芯片位于第一表面，且朝向第二表面。在上述方案中，驱动芯片和功率芯片设置在第一基板和第二基板之间，驱动芯片和功率芯片设置在不同的平面上，该功率结构体为三维结构体。可以实现功率结构体的器件小型化和高集成度。
在一种可能的实现方式中，驱动芯片设置于所述第二基板的第二表面；所述功率芯片设置于所述第二基板的第二表面。在上述方案中，功率结构体包括多个驱动芯片，有的驱动芯片设置于第一基板，有的驱动芯片设置于第二基板，驱动芯片和功率芯片设置在第一基板和第二基板之间，驱动芯片和功率芯片设置在不同的平面上，该功率结构体为三维结构体。可以实现功率结构体的器件小型化和高集成度。
在一种可能的实现方式中，导电部件位于第一表面和第二表面之间。在上述方案中，该导电部件可以是导电柱，导电柱位于第一表面和第二表面之间。本申请实施例中导电部件除了导电还可以起到支撑作用，使得功率芯片和驱动芯片可以设置在该第一基板和第二基板之间的空间中。又如，功率结构体还包括电子元件，该电子元件也可以设置在第一基板和第二基板之间的空间中。
在一种可能的实现方式中，所述第一端与所述第一表面焊接，所述第二端与所述第二表面焊接。例如，第一端通过第一焊料与第一表面连接，第二端通过第二焊料与第二表面连接。在上述方案中，导电部件可以通过焊料实现与第一基板、第二基板的连接，通过使用焊料可以使得导电部件与第一基板、第二基板固定在一起，从而可以形成第一基板和第二基板之间的空间。
在一种可能的实现方式中，功率结构体还包括：电子元件，其中，所述电子元件设置于所述第一基板的第一表面，和/或所述第二基板的第二表面。例如，该电子元件具体为第一电子元件，其中，第一电子元件设置于第一表面，且朝向第二表面。在上述方案中，第一电子元件可以和驱动芯片并排设置在第一基板的第一表面上，该第一电子元件可以设置在第一基板和第二基板之间的空间中，第一电子元件可以和功率芯片分布在不同的平面上，因此功率结构体为三维结构体，有利于功率结构体的小型化设计。例如，该电子元件具体为第二电子元件，第二电子元件设置于第二表面，且朝向第一表面。在上述方案中，第二电子元件可以和功率芯片并排设置在第二基板的第二表面上，该第二电子元件可以设置在第一基板和第二基板之间的空间中，第二电子元件可以和驱动芯片分布在不同的平面上，因此功率结构体为三维结构体，有利于功率结构体的小型化设计。例如，该电子元件有多个，有的电子元件设置于第一表面，有的电子元件设置于第二表面。在上述方案中，电子元件可以设置在第一基板和第二基板之间的空间中，电子元件可以和驱动芯片分布在不同的平面上，因此功率结构体为三维结构体，有利于功率结构体的小型化设计。
在一种可能的实现方式中，功率结构体还包括：散热模块，其中，散热模块设置于第二基板的背面。例如，第二基板包括第三表面，第二基板的第二表面和第三表面是相背的 两个表面，第二基板的第三表面是第二基板的反面，例如第三表面用于设置散热模块。功率芯片和散热模块分别设置在第二基板的不同表面上，功率芯片被封装体封装，但是散热模块没有被封装体封装，因此散热模块可以用于对功率结构体的散热，例如该功率结构体可以是通过导电部件互连双基板的三维高密高导热封装结构。
在一种可能的实现方式中，功率结构体还包括：焊盘，其中，焊盘位于第一基板的第四表面，第四表面为第一表面的背面。在上述方案中，第一基板的第四表面和第一表面是相背的两个表面，第一基板的第四表面是第一基板的反面，例如第四表面用于设置焊盘。驱动芯片和焊盘分别设置在第一基板的不同表面上，驱动芯片被封装体封装，但是焊盘没有被封装体封装，该焊盘可用于功率结构体与外界其它设备的电气连接。
在一种可能的实现方式中，第一基板为第一埋嵌式基板，其中，在第一埋嵌式基板之内设有驱动芯片。在上述方案中，驱动芯片埋设在第一埋嵌式基板中，因此在第一埋嵌式基板和第二基板之间只需要设置功率芯片和导电部件即可，可以进一步的缩小功率结构体的体积，有利于功率结构体的小型化设计。
在一种可能的实现方式中，为了区别本申请实施例中的多个功率芯片，将“功率芯片设置于第二基板”中的功率芯片称为第一功率芯片，功率结构体还包括：第二功率芯片，第一基板为第二埋嵌式基板，其中，在第二埋嵌式基板之内设有第二功率芯片。在上述方案中，驱动芯片可以设置在第二埋嵌式基板的第一表面上，在第二埋嵌式基板之内设有第二功率芯片，因此在第二埋嵌式基板和第二基板之间只需要设置功率芯片、导电部件和驱动芯片即可，可以进一步的缩小功率结构体的体积，有利于功率结构体的小型化设计。
在一种可能的实现方式中，功率结构体还包括：第三电子元件，第一基板为第三埋嵌式基板，其中，在第三埋嵌式基板之内设有第三电子元件。在上述方案中，驱动芯片可以设置在第三埋嵌式基板的第一表面上，在第三埋嵌式基板之内设有第三电子元件，因此在第三埋嵌式基板和第二基板之间只需要设置功率芯片、导电部件和驱动芯片即可，可以进一步的缩小功率结构体的体积，有利于功率结构体的小型化设计。
在一种可能的实现方式中，功率结构体还包括：第三功率芯片，其中，第三功率芯片位于第一表面，且朝向第二表面。在上述方案中，功率结构体中可以包括多个功率芯片，例如功率结构体中包括功率芯片和第三功率芯片，功率芯片设置在第二基板上，第三功率芯片设置在第一基板上。第三功率芯片可以和驱动芯片并排设置在第一基板的第一表面上，该第三功率芯片可以设置在第一基板和第二基板之间的空间中，第三功率芯片可以和功率芯片分布在不同的平面上，因此功率结构体为三维结构体，有利于功率结构体的小型化设计。
在一种可能的实现方式中，第二基板为陶瓷覆铜板。
第二方面，本申请实施例还提供一种功率结构体，包括：第一基板，第二基板，驱动芯片，功率芯片，导电线，第一封装体和粘性模，其中，所述功率芯片位于所述第二基板的第二表面；所述第一封装体包覆于所述第二基板的第二表面和所述功率芯片；所述第一基板通过所述粘性模粘贴于所述第一封装体上；所述驱动芯片设置于所述第一基板；所述导电线的一端连接所述第一基板，所述导电线的另一端连接所述第二基板。
在上述方案中，第二基板具有第二表面，功率芯片位于第二表面，第一基板通过粘性 模粘贴于第一封装体上，从而功率芯片处于第一基板和第二基板之间，另外驱动芯片设置于第一基板，因此功率芯片和驱动芯片设置在两个基板上，功率芯片和驱动芯片属于基于两个基板的堆叠结构，提高了功率结构体的集成度。导电线的两端分别连接第一基板与第二基板，通过导电线可实现第一基板和第二基板之间的电气传输，降低功率结构体的寄生参数，满足高频大功率领域的需求。
在一种可能的实现方式中，功率结构体还包括：导电部件，其中，所述导电部件的第一端与所述第二基板的第二表面连接。导电部件的第一端与第二基板的第二表面连接，从而第二基板可以通过导电部件进行电信号的输出。
在一种可能的实现方式中，功率结构体还包括：第二封装体，其中，第二封装体包覆于所述第一基板，所述第二基板的第二表面，所述驱动芯片，所述功率芯片和所述导电部件，其中，所述导电部件的第二端露出所述第二封装体。在上述方案中，第二封装体起到对功率结构体的内部结构的封装作用，例如，第二封装体对第一基板，第二表面，驱动芯片，功率芯片和导电线进行封装，从而可以得到封装后的功率结构体。又如该封装体对第一基板和第二基板之间的空间进行封装。功率芯片和导电线都被封装到该封装体中，从而可以得到密封的功率结构体。通过第二封装体的封装之后，导电部件的末端露出于第二封装体，因此导电部件可以用于功率结构体与外部器件的电气连接。
在一种可能的实现方式中，所述驱动芯片设置于所述第一基板的第一表面，或者嵌入于所述第一基板之内；所述功率芯片设置于所述第二基板的第二表面。例如，驱动芯片位于第一表面，且朝向第二表面。第一表面为所述第一基板远离所述第一封装体的表面。在上述方案中，驱动芯片和功率芯片设置在第一基板和第二基板之间，驱动芯片和功率芯片设置在不同的平面上，该功率结构体为三维结构体。可以实现功率结构体的器件小型化和高集成度。
在一种可能的实现方式中，驱动芯片设置于所述第二基板的第二表面；所述功率芯片设置于所述第二基板的第二表面。在上述方案中，功率结构体包括多个驱动芯片，有的驱动芯片设置于第一基板，有的驱动芯片设置于第二基板，驱动芯片和功率芯片设置在第一基板和第二基板之间，驱动芯片和功率芯片设置在不同的平面上，该功率结构体为三维结构体。可以实现功率结构体的器件小型化和高集成度。
在一种可能的实现方式中，所述功率结构体还包括：电子元件，其中，所述电子元件设置于所述第一基板的第一表面，和/或所述第二基板的第二表面，其中，所述第一表面为所述第一基板远离所述第一封装体的表面。例如第一电子元件设置于第一表面，且朝向第二表面。在上述方案中，第一电子元件可以和驱动芯片并排设置在第一基板的第一表面上，该第一电子元件可以设置在第一基板和第二基板之间的空间中，第一电子元件可以和功率芯片分布在不同的平面上，因此功率结构体为三维结构体，有利于功率结构体的小型化设计。例如，该电子元件具体为第二电子元件，第二电子元件设置于第二表面，且朝向第一表面。在上述方案中，第二电子元件可以和功率芯片并排设置在第二基板的第二表面上，该第二电子元件可以设置在第一基板和第二基板之间的空间中，第二电子元件可以和驱动芯片分布在不同的平面上，因此功率结构体为三维结构体，有利于功率结构体的小型化设计。例如，所述电子元件设置于所述第一基板的第一表面和所述第二基板的第二表面。例 如，该电子元件有多个，有的电子元件设置于第一表面，有的电子元件设置于第二表面。在上述方案中，电子元件可以设置在第一基板和第二基板之间的空间中，电子元件可以和驱动芯片分布在不同的平面上，因此功率结构体为三维结构体，有利于功率结构体的小型化设计。
在一种可能的实现方式中，功率结构体还包括：散热模块，其中，散热模块设置于第二基板的第二表面的背面。例如第二基板具有第三表面，第二基板的第二表面和第三表面是相背的两个表面，第二基板的第三表面是第二基板的反面，例如第三表面用于设置散热模块。功率芯片和散热模块分别设置在第二基板的不同表面上，功率芯片被封装体封装，但是散热模块没有被封装体封装，因此散热模块可以用于对功率结构体的散热，例如该功率结构体可以是通过导电部件互连双基板的三维高密高导热封装结构。
在一种可能的实现方式中，第一基板为第一埋嵌式基板，其中，在第一埋嵌式基板之内设有驱动芯片。在上述方案中，驱动芯片埋设在第一埋嵌式基板中，因此在第一埋嵌式基板和第二基板之间只需要设置功率芯片和导电部件即可，可以进一步的缩小功率结构体的体积，有利于功率结构体的小型化设计。
在一种可能的实现方式中，为了区别本申请实施例中的多个功率芯片，将“功率芯片设置于第二基板”中的功率芯片称为第一功率芯片，功率结构体还包括：第二功率芯片，第一基板为第二埋嵌式基板，其中，在第二埋嵌式基板之内设有第二功率芯片。在上述方案中，驱动芯片可以设置在第二埋嵌式基板的第一表面上，在第二埋嵌式基板之内设有第二功率芯片，因此在第二埋嵌式基板和第二基板之间只需要设置功率芯片和导电部件即可，可以进一步的缩小功率结构体的体积，有利于功率结构体的小型化设计。
在一种可能的实现方式中，功率结构体还包括：第三电子元件，第一基板为第三埋嵌式基板，其中，在第三埋嵌式基板之内设有第三电子元件。在上述方案中，驱动芯片可以设置在第三埋嵌式基板的第一表面上，在第三埋嵌式基板之内设有第三电子元件，因此在第三埋嵌式基板和第二基板之间只需要设置功率芯片和导电部件即可，可以进一步的缩小功率结构体的体积，有利于功率结构体的小型化设计。
在一种可能的实现方式中，功率结构体还包括：第四电子元件，其中，第四电子元件设置于第一基板的第一表面。在上述方案中，第一基板的第四表面和第一表面是相背的两个表面，第一基板的第一表面是第一基板的反面，例如第四表面用于设置第四电子元件。第四电子元件可以设置在第一基板的第一表面上，第四电子元件和功率芯片分布在不同的平面上，因此功率结构体为三维结构体，有利于功率结构体的小型化设计。
在一种可能的实现方式中，驱动芯片位于第一基板的第一表面。在上述方案中，第一基板的第四表面和第一表面是相背的两个表面，驱动芯片可以设置在第一基板的第一表面上，驱动芯片和功率芯片分布在不同的平面上，因此功率结构体为三维结构体，有利于功率结构体的小型化设计。
在一种可能的实现方式中，功率结构体还包括：第三功率芯片，其中，第三功率芯片位于第四表面，且朝向第二表面。在上述方案中，功率结构体中可以包括多个功率芯片，例如功率结构体中包括功率芯片和第三功率芯片，功率芯片设置在第二基板上，第三功率芯片设置在第一基板上。第三功率芯片设置在第一基板的第四表面上，该第三功率芯片可 以设置在第一基板和第二基板之间的空间中，第三功率芯片可以和功率芯片分布在不同的平面上，因此功率结构体为三维结构体，有利于功率结构体的小型化设计。
在一种可能的实现方式中，第二基板为陶瓷覆铜板。
第三方面，本申请实施例还提供一种功率结构体的制备方法，包括：将功率芯片置于第二基板的第二表面；将第一封装体包覆于所述第二基板的第二表面和所述功率芯片；通过粘性模将所述第一基板粘贴于所述第一封装体上；将驱动芯片置于所述第一基板；将导电线的一端连接所述第一基板，所述导电线的另一端连接所述第二基板。
在一种可能的实现方式中，所述方法还包括：将导电部件的第一端与所述第二基板的第二表面连接。
在一种可能的实现方式中，方法还包括：将第二封装体包覆于所述第一基板，所述第二基板的第二表面，所述驱动芯片，所述功率芯片和所述导电部件，其中，所述导电部件的第二端露出所述第二封装体。
在一种可能的实现方式中，所述将驱动芯片置于所述第一基板，包括：将所述驱动芯片设置于所述第一基板的第一表面，或者嵌入于所述第一基板之内；
所述将功率芯片置于第二基板的第二表面，包括：将所述功率芯片设置于所述第二基板的第二表面。
在一种可能的实现方式中，方法还包括：将电子元件置于所述第一基板的第一表面，和/或所述电子元件设置于所述第二基板的第二表面，其中，所述第一表面为所述第一基板远离所述第一封装体的表面。
在一种可能的实现方式中，方法还包括：将散热模块置于所述第二基板的第二表面的背面。
在本申请的第三方面中，功率结构体的制备方法中制备得到的功率结构体包括前述第二方面以及各种可能的实现方式中所描述的步骤，详见前述对第二方面以及各种可能的实现方式中的说明。
第四方面，本申请实施例还提供一种交变电流(alternating current，AC)模组，包括：如第一方面或第二方面所述的功率结构体。
第五方面，本申请实施例还提供一种能源设备，包括：如前述第一方面或第二方面所述的功率结构体；或者，
所述能源设备包括：如第四方面所述的交变电流模组。
例如，能源设备可以包括：站点能源，网络能源，数据中心能源，车载充电(on board charger，OBC)能源，逆变器能源(即光伏能源)，适配器能源等。
第六方面，本申请实施例还提供一种射频拉远单元(remote radio unit，RRU)，包括：如第四方面所述的交变电流模组。
从以上技术方案可以看出，本申请实施例具有以下优点：
在本申请实施例中，功率结构体包括：第一基板，第二基板，驱动芯片，功率芯片和导电部件。其中，第一基板具有第一表面，第二基板具有第二表面，第一表面和第二表面相对设置，功率芯片设置于第二基板，从而功率芯片处于第一基板和第二基板之间，另外驱动芯片设置于第一基板，因此功率芯片和驱动芯片设置在两个基板上，功率芯片和驱动 芯片属于基于两个基板的堆叠结构，提高了功率结构体的集成度。导电部件具有第一端和第二端，第一端与第一表面连接，第二端与第二表面连接，该导电部件可以将第一基板和第二基板连接起来，导电部件导通第一基板与第二基板，通过导电部件可实现第一基板和第二基板之间的电气传输，降低功率结构体的寄生参数，满足高频大功率领域的需求。
在本申请实施例中，第二基板具有第二表面，功率芯片位于第二表面，第一基板通过粘性模粘贴于第一封装体上，从而功率芯片处于第一基板和第二基板之间，另外驱动芯片设置于第一基板，因此功率芯片和驱动芯片设置在两个基板上，功率芯片和驱动芯片属于基于两个基板的堆叠结构，提高了功率结构体的集成度。导电线的两端分别连接第一基板与第二基板，通过导电线可实现第一基板和第二基板之间的电气传输，降低功率结构体的寄生参数，满足高频大功率领域的需求。
附图说明
图1为本申请实施例提供的一种功率结构体的结构示意图；
图2为本申请实施例提供的包括两个导电部件的功率结构体的结构示意图；
图3为本申请实施例提供的包括封装体的功率结构体的结构示意图；
图4为本申请实施例提供的包括焊料的功率结构体的结构示意图；
图5为本申请实施例提供的包括一个第一电子元件的功率结构体的结构示意图；
图6为本申请实施例提供的包括多个第一电子元件的功率结构体的结构示意图；
图7为本申请实施例提供的包括一个第二电子元件的功率结构体的结构示意图；
图8为本申请实施例提供的包括多个第二电子元件的功率结构体的结构示意图；
图9为本申请实施例提供的包括陶瓷层和铜层的功率结构体的结构示意图；
图10为本申请实施例提供的包括散热模块的功率结构体的结构示意图；
图11为本申请实施例提供的包括焊盘的功率结构体的结构示意图；
图12为本申请实施例提供的包括第一嵌入式基板的功率结构体的结构示意图；
图13为本申请实施例提供的包括第二功率芯片的功率结构体的结构示意图；
图14为本申请实施例提供的包括第三电子元件的功率结构体的结构示意图；
图15为本申请实施例提供的包括第二功率芯片的功率结构体的结构示意图；
图16为本申请实施例提供的第二基板上组装第一功率芯片的结构示意图；
图17为本申请实施例提供的第一基板上组装驱动芯片和导电部件的结构示意图；
图18为本申请实施例提供的包括另一种功率结构体的结构示意图；
图19为本申请实施例提供的包括第二封装体和第一封装体的功率结构体的结构示意图；
图20为本申请实施例提供的包括导电部件的功率结构体的结构示意图；
图21为本申请实施例提供的包括第一电子元件的功率结构体的结构示意图；
图22为本申请实施例提供的包括第二电子元件的功率结构体的结构示意图；
图23为本申请实施例提供的包括散热模块的功率结构体的结构示意图；
图24为本申请实施例提供的包括第一埋嵌式基板的功率结构体的结构示意图；
图25为本申请实施例提供的包括第二功率芯片的功率结构体的结构示意图；
图26为本申请实施例提供的包括第三电子元件的功率结构体的结构示意图；
图27为本申请实施例提供的包括第四电子元件的功率结构体的结构示意图；
图28为本申请实施例提供的包括第三功率芯片的功率结构体的结构示意图；
图29为本申请实施例提供的功率结构体的制备方法的示意图；
图30为本申请实施例提供的第二基板上组装第一功率芯片的结构示意图；
图31为本申请实施例提供的第二基板上封装第一封装体的结构示意图。
另外，在本申请的说明书附图中，附图标记如下，在后续具体实施方式中不再引用各个装置部件的附图标记。
第一基板101，
第一基板的第一表面1011，
第二基板102，
第二基板的第二表面1021，
驱动芯片103，
第一功率芯片104，
导电部件105，
导电部件的第一端1051，
导电部件的第二端1052，
封装体106，
第一焊料1071，
第二焊料1072，
第一电子元件108，
第二电子元件109，
散热模块110，
第二基板的陶瓷层1022，
第二基板的铜层1023，
第二基板的第三表面1024，
第一基板的第四表面1012，
焊盘111，
第二功率芯片112，
第三电子元件113，
第三功率芯片114，
导电线115，
第二封装体116，
第一封装体117，
粘性模118，
第四电子元件119。
具体实施方式
本申请实施例提供了一种功率结构体和制备方法以及设备，用于提供集成度高的功率结构体，满足高频大功率领域的需求。
下面结合附图，对本申请的实施例进行描述。
本申请的说明书和权利要求书及上述附图中的术语“第一”，“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的术语在适当情况下可以互换，这仅仅是描述本申请的实施例中对相同属性的对象在描述时所采用的区分方式，例如第一基板和第二基板表示不同的两个基板，第一和第二并不相互依赖，在没有记载“第一”的情况下，实施例中可以记载“第二”，同样的，在实施例中记载有“第一”的情况下，也可以不记载“第二”。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，以便包含一系列单元的过程，方法，系统，产品或设备不必限于那些单元，而是可包括没有清楚地列出的或对于这些过程，方法，产品或设备固有的其它单元。
本申请实施例提供一种功率结构体，该功率结构体是指一种包括功率芯片的组成结构单元，例如功率结构体可以是功率模块，功率组件，功率结构单元等，本申请实施例中功率结构体也可以定义为其它名称的结构单元，例如功率结构体可以是模块，装置，设备，终端，器件等，具体实现方式不做限定。本申请实施例提供的功率结构体中包括功率芯片，其中，功率芯片又可以称为“功率半导体芯片”，功率芯片是指在通电状态下能够产生功率的芯片。功率芯片的具体实现方式与功率结构体的应用场景有关，对于不同的功率结构体，该功率结构体所包括的功率芯片的类型，功率芯片的个数，功率芯片在功率结构体内的排布方式，功率芯片在功率结构体内与其它电子元件，其它芯片的连接方式，都需要结合功率结构体的具体应用场景确定。例如功率结构体可以是封装级电源(power supply in a package，PSIP)，功率芯片可以是金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor，MOSFET)。
接下来对首先对本申请实施例中涉及到的功率结构体的组成部分所涉及的术语进行说明：
本申请实施例提供的功率结构体包括双基板、驱动芯片、功率芯片和导电部件。其中，本申请实施例中的基板可以是印制电路板(printed circuit board，PCB)。双基板是指两个基板，分别定义为第一基板和第二基板，第一基板和第二基板可以是相对设置的两个基板，这两个基板之间存在一定的空间，即两个基板之间间隔一定的距离，对于所间隔的距离值此处不做限定。第一基板和第二基板分别是具有电路功能的基板，第一基板和第二基板还用于固定芯片。根据第一基板和第二基板在空间中的分布位置，第一基板和第二基板中的一个基板可以称为上基板，第一基板和第二基板中的另一个基板可以称为下基板。为便于描述，后续实施例中第一基板可以是下基板，第二基板可以是上基板。上基板和下基板是基于基板所在空间的分布位置而定义的，并不做为对本申请实施例的限定。
本申请的一些实施例中，第二基板可以是带有散热功能的基板，例如第二基板可以是陶瓷覆铜板(direct bonding copper，DBC)，例如DBC包括陶瓷层和铜层。DBC是将铜箔直接烧结在陶瓷表面而制成的基板。DBC可用于大功率电力半导体模块，功率控制电路，功率混合电路、智能功率组件，高频开关电源、固态继电器，太阳能电池板组件等。
本申请的一些实施例中，第一基板上可以设置驱动芯片，例如驱动芯片可以设置在第一基板的表面上。又如，第一基板可以是埋嵌式基板，埋嵌式基板采用嵌入式元件封装(embedded component packaging，ECP)，将电子元件、芯片(例如驱动芯片、功率芯片)埋嵌入基板内部。
本申请实施例中功率结构体中包括驱动芯片，该驱动芯片是指用于对功率芯片进行驱动的芯片部件，其中驱动芯片中存储有驱动程序，在驱动芯片上电运行之后，驱动芯片可以运行该驱动程序，通过该驱动程序驱动功率芯片的运行。
本申请实施例中功率结构体中包括一个或多个功率芯片，具体需要结合应用场景确定功率结构体中的功率芯片。例如功率结构体中包括第一功率芯片。第一功率芯片和驱动芯片在功率结构体中分别设置在不同的基板上。功率结构体中包括双基板，第一功率芯片和驱动芯片分别设置在一个基板上。由前述对双基板的说明可知，双基板中两个基板是相对设置的，第一功率芯片和驱动芯片设置在不同的基板上，因此第一功率芯片和驱动芯片并不是分布在同一个平面，第一功率芯片和驱动芯片是分布在不同的平面上，因此本申请实施例提供的功率结构体是三维结构体，第一功率芯片和驱动芯片的这种分布方式能够提高功率结构体的集成度，减少了功率结构体的空间体积，可以适应器件小型化的发展趋势。
本申请的一些实施例中，功率结构体中包括第一功率芯片和第二功率芯片，第一功率芯片和第二功率芯片所在的基板不同。
本申请实施例中功率结构体中包括导电部件，该导电部件可以导通第一基板和第二基板，即导电部件可以互连双基板，使得双基板上各自安装的芯片能够进行电气传输，例如通过导电部件可以实现双基板上各自安装的芯片之间的信号传输。
本申请的一些实施例中，导电部件的材质可以是铜，或者是其它导电金属材料，此处不做限定。另外，本申请实施例提供的导电部件的形状具有多种，只要该导电部件能够实现双基板互连的功能即可，例如导电部件为如下其中一种形状：柱状、板状、片状等。例如导电部件的横截面具有多种形状，例如导电部件的横截面可以是L形、口字形、圆形、菱形等。
本申请的一些实施例中，导电部件除了具有导电功能，还可以具有支撑功能，例如导电部件支撑在双基板之间，从而在双基板之间可以形成一定大小的空间，功率结构体中的组成部分都可以容置在该空间中。
本申请的一些实施例中，功率结构体可以包括一个或多个封装体，当功率结构体中包括多个封装体，例如包括两个封装体时，这两个封装体分别定义为第二封装体和第一封装体。其中，功率结构体中的芯片需要进行封装，以得到封装体，该封装体可以对基板的表面、功率芯片、驱动芯片、导电部件进行封装，封装体是指安装半导体集成电路芯片用的外壳，可以起到安放，固定，密封，保护芯片和增强导热性能的作用。例如该封装体可以是对基板的表面、功率芯片、驱动芯片、导电部件进行塑封得到的塑封体。例如该封装体可以是封装层。
本申请的一些实施例中，功率结构体可以包括电子元件，该电子元件是功率结构体中所需要的元器件，例如功率结构体中的电子元件可以是一个或多个。例如电子元件可以是如下元器件中的至少一种：电阻、电容、电感。本申请实施例中对于电子的元件的实现方 式不做限定。当功率结构体中包括多个电子元件，例如包括两个电子元件时，这两个电子元件分别定义为第一电子元件和第二电子元件。第一电子元件和第二电子元件在功率结构体内的部署位置和所起的作用不同，详见后续实施例中的举例说明。
本申请的一些实施例中，第二基板是具有散热功能的基板，例如第二基板上设置有散热模块，该散热模块可用于功率芯片的散热。例如散热模块能为组装在上基板上的芯片提供散热渠道。本申请实施例中散热模块包括但不限于散热模块为散热材料，或者散热模块上设置有散热渠道等。
上述内容对本申请实施例中功率结构体的组成部分进行了说明，接下来结合附图对本申请实施例提供的功率结构体进行说明。
请参阅图1，本申请实施例提供的一种功率结构体，包括：第一基板，第二基板，驱动芯片，功率芯片和导电部件，其中，
第一基板的第一表面和第二基板的第二表面相对设置；
导电部件的第一端与第一表面连接，导电部件的第二端与第二表面连接；
驱动芯片设置于第一基板；
功率芯片设置于第二基板。
在本申请的一些实施例中，为了区别本申请实施例中的多个功率芯片，将“功率芯片设置于第二基板”中的功率芯片称为第一功率芯片。例如第一功率芯片位于第二表面，且朝向第一表面。
其中，图1所示的第一基板和第二基板之间存在一定的空间，导电部件起到导电和支撑的作用，第一基板的第一表面是设置芯片的主表面，例如第一基板的第一表面朝上。
在本申请的一些实施例中，如图1所示，驱动芯片设置于第一基板，例如驱动芯片位于第一表面，且朝向第二表面。第二基板的第二表面是设置芯片的主表面，例如第二基板的第二表面朝下，第一表面和第二表面之间存在空间，驱动芯片和第一功率芯片设置在第一基板和第二基板之间。例如第一功率芯片可以通过焊料和第二基板连接。导电部件具有第一端和第二端，第一端和第二端是导电部件的上下两端，第一端与第一表面连接，第二端与第二表面连接，从而导电部件可以导通第一基板和第二基板。图1所示的功率结构体中，驱动芯片和第一功率芯片设置在不同的平面上，该功率结构体为三维结构体。导电部件可以导通第一基板和第二基板，从而减少了第一基板和第二基板之间的传输路径，减少了功率结构体的寄生参数。基于图1所示的功率结构体，可以实现功率结构体的器件小型化和高集成度。
在本申请的一些实施例中，驱动芯片设置于第一基板的第一表面，或者嵌入于第一基板之内；功率芯片设置于所述第二基板的第二表面。例如，驱动芯片位于第一表面，且朝向第二表面。又如，驱动芯片可以埋嵌在第一基板中，详见后续实施例的说明。在上述方案中，驱动芯片和功率芯片设置在第一基板和第二基板之间，驱动芯片和功率芯片设置在不同的平面上，该功率结构体为三维结构体。可以实现功率结构体的器件小型化和高集成度。
需要说明的是，本申请实施例中不限定功率结构体中的导电部件的个数以及分布位置，不限定功率结构体中的驱动芯片的个数以及分布位置，不限定功率结构体中的第一功率芯 片的个数以及分布位置，具体可以结合应用场景确定，此处仅为举例说明。图1中以功率结构体中包括两个导电部件，两个导电部件中每个导电部件都起到对第一基板、第二基板的导电和支撑作用。例如两个导电部件为左右对称结构。
如图2所示，功率结构体包括1个导电部件，1个导电部件起到对第一基板、第二基板的导电和支撑作用。不限定的是，本申请实施例中功率结构体包括的导电部件还可以为其它个数。
本申请的一些实施例中，如图3所示，功率结构体还包括：封装体，其中，
封装体包覆于第一基板的第一表面，第二基板，驱动芯片，功率芯片和导电部件。
其中，封装体起到对功率结构体的内部结构的封装作用，例如，封装体对第一基板的第一表面，第二基板，驱动芯片，功率芯片和导电部件进行封装，从而可以得到封装后的功率结构体。其中，封装体对第二基板的包覆可以是包覆第二基板的一个表面或多个表面，例如，封装体包覆于第一基板的第一表面，第二基板的第二表面，驱动芯片，功率芯片和导电部件。又如，封装体包覆于第二基板的第二表面和侧面。又如该封装体对第一基板和第二基板之间的空间进行封装。驱动芯片，第一功率芯片和导电部件都被封装到该封装体中，从而可以得到密封的功率结构体。例如该功率结构体可以是通过导电部件互连双基板的三维高密封装结构。
本申请的一些实施例中，导电部件导通第一基板和第二基板，另外，导电部件还可以起到对基板的支撑作用，导电部件位于第一表面和第二表面之间。该导电部件可以是导电柱，导电柱位于第一表面和第二表面之间。本申请实施例中导电部件除了导电还可以起到支撑作用，使得功率芯片和驱动芯片可以设置在该第一基板和第二基板之间的空间中。又如，功率结构体还包括电子元件，该电子元件也可以设置在第一基板和第二基板之间的空间中。
本申请的一些实施例中，功率结构体还包括焊料，其中，第一端通过焊料与第一表面焊接，第二端通过焊料与第二表面焊接。为便于描述以及图例说明，根据焊料的使用位置不同，分别称为第一焊料和第二焊料，如图4所示，第一端通过第一焊料与第一表面连接，第二端通过第二焊料与第二表面连接。因此导电部件可以通过焊料实现与第一基板、第二基板的连接，通过使用焊料可以使得导电部件与第一基板、第二基板固定在一起，从而可以形成第一基板和第二基板之间的空间。
本申请的一些实施例中，功率结构体还包括：电子元件，其中，电子元件设置于第一基板的第一表面，和/或第二基板的第二表面。为便于描述以及图例说明，根据电子元件的分布位置以及连接关系的不同，分别称为第一电子元件、第二电子元件以及第三电子元件等。例如，该电子元件具体为第一电子元件，如图5所示，功率结构体还包括：第一电子元件，其中，
第一电子元件设置于第一表面，且朝向第二表面。
其中，第一电子元件可以和驱动芯片并排设置在第一基板的第一表面上，该第一电子元件可以设置在第一基板和第二基板之间的空间中，第一电子元件可以和第一功率芯片分布在不同的平面上，因此功率结构体为三维结构体，有利于功率结构体的小型化设计。本申请实施例中对于第一电子元件的个数不做限定。
需要说明的是，功率结构体还包括第一电子元件时，封装体包覆于第一基板的第一表面，第二基板，驱动芯片，第一功率芯片、导电部件和第一电子元件。
本申请的一些实施例中，如图6所示，以功率结构体包括4个第一电子元件为例进行说明，4个第一电子元件可以和驱动芯片并排设置，对于4个第一电子元件在第一基板的第一表面上的分布方式不做限定，另外对于4个第一电子元件的类型不做限定。
需要说明的是，功率结构体还包括4个第一电子元件时，封装体包覆于第一基板的第一表面，第二基板，驱动芯片，第一功率芯片、导电部件和4个第一电子元件。
本申请的一些实施例中，如图7所示，功率结构体还包括：第二电子元件，其中，
第二电子元件设置于第二表面，且朝向第一表面。
其中，第二电子元件可以和第一功率芯片并排设置在第二基板的第二表面上，该第二电子元件可以设置在第一基板和第二基板之间的空间中，第二电子元件可以和驱动芯片分布在不同的平面上，因此功率结构体为三维结构体，有利于功率结构体的小型化设计。本申请实施例中对于第二电子元件的个数不做限定。
需要说明的是，功率结构体还包括第二电子元件时，封装体包覆于第一基板的第一表面，第二基板，驱动芯片，第一功率芯片、导电部件和第二电子元件。
需要说明的是，图7和图5的区别在于电子元件的分布位置不同。例如第一电子元件分布在第一基板上，第二电子元件分布在第二基板中。
本申请的一些实施例中，如图8所示，以功率结构体包括4个第二电子元件为例进行说明，4个第二电子元件可以和驱动芯片并排设置，对于4个第二电子元件在第二基板的第二表面上的分布方式不做限定，另外对于4个第二电子元件的类型不做限定。
需要说明的是，功率结构体还包括4个第二电子元件时，封装体包覆于第一基板的第一表面，第二基板，驱动芯片，第一功率芯片、导电部件和4个第二电子元件。
本申请的一些实施例中，如图9所示，第二基板可以是带有散热功能的基板，例如第二基板可以是DBC，例如DBC包括陶瓷层和铜层。其中，陶瓷层可以被封装体封装，铜层的表面没有被封装体封装，因此DBC可以实现散热功能。
本申请的一些实施例中，如图10所示，功率结构体还包括：散热模块，其中，
散热模块设置于第二基板的第二表面的背面。
例如，第二基板具有第三表面，第二基板的第二表面和第三表面是相背的两个表面，第二基板的第三表面是第二基板的反面，例如第三表面用于设置散热模块。第一功率芯片和散热模块分别设置在第二基板的不同表面上，第一功率芯片被封装体封装，但是散热模块没有被封装体封装，因此散热模块可以用于对功率结构体的散热，例如该功率结构体可以是通过导电部件互连双基板的三维高密高导热封装结构。
本申请的一些实施例中，如图11所示，功率结构体还包括：焊盘，其中，
焊盘位于第一基板的第四表面，
第四表面为第一表面的背面。
其中，第一基板的第四表面和第一表面是相背的两个表面，第一基板的第四表面是第一基板的反面，例如第四表面用于设置焊盘。驱动芯片和焊盘分别设置在第一基板的不同表面上，驱动芯片被封装体封装，但是焊盘没有被封装体封装，该焊盘可用于功率结构体 与外界其它设备的电气连接。本申请实施例中对于焊盘在第四表面的分布位置和焊盘的个数不做限定。
本申请的一些实施例中，驱动芯片可以嵌入于第一基板之内。例如，如图12所示，第一基板为第一埋嵌式基板，其中，
在第一埋嵌式基板之内设有驱动芯片。
其中，如图12所示，驱动芯片埋设在第一埋嵌式基板中，因此在第一埋嵌式基板和第二基板之间只需要设置第一功率芯片和导电部件即可，可以进一步的缩小功率结构体的体积，有利于功率结构体的小型化设计。
本申请的一些实施例中，功率芯片可以嵌入于第一基板之内。例如，如图13所示，功率结构体还包括：第二功率芯片，
第一基板为第二埋嵌式基板，其中，
在第二埋嵌式基板之内设有第二功率芯片。
其中，如图13所示，驱动芯片可以设置在第二埋嵌式基板的第一表面上，在第二埋嵌式基板之内设有第二功率芯片，因此在第二埋嵌式基板和第二基板之间只需要设置第一功率芯片、导电部件和驱动芯片即可，可以进一步的缩小功率结构体的体积，有利于功率结构体的小型化设计。
需要说明的是，图12和图13的区别在于埋嵌式基板中埋嵌的单元不同。例如图12中在第一埋嵌式基板之内设驱动芯片，图13中在第二埋嵌式基板之内设第二功率芯片。不限定的是，功率结构体中的埋嵌式基板中还可以同时埋嵌驱动芯片和第二功率芯片，此处不做限定。
本申请的一些实施例中，电子元件可以嵌入于第一基板之内。例如，如图14所示，功率结构体还包括：第三电子元件，
第一基板为第三埋嵌式基板，其中，
在第三埋嵌式基板之内设有第三电子元件。
其中，如图14所示，驱动芯片可以设置在第三埋嵌式基板的第一表面上，在第三埋嵌式基板之内设有第三电子元件，因此在第三埋嵌式基板和第二基板之间只需要设置第一功率芯片、导电部件和驱动芯片即可，可以进一步的缩小功率结构体的体积，有利于功率结构体的小型化设计。
需要说明的是，图13和图14的区别在于埋嵌式基板中埋嵌的单元不同。例如图13中在第二埋嵌式基板之内设第二功率芯片，图14中在第三埋嵌式基板之内设第三电子元件。不限定的是，功率结构体中的埋嵌式基板中还可以同时埋嵌第二功率芯片和第三电子元件，此处不做限定。
本申请的一些实施例中，如图15所示，功率结构体还包括：第三功率芯片，其中，
第三功率芯片位于第一表面，且朝向第二表面。
其中，功率结构体中可以包括多个功率芯片，例如功率结构体中包括第一功率芯片和第三功率芯片，第一功率芯片设置在第二基板上，第三功率芯片设置在第一基板上。第三功率芯片可以和驱动芯片并排设置在第一基板的第一表面上，该第三功率芯片可以设置在第一基板和第二基板之间的空间中，第三功率芯片可以和第一功率芯片分布在不同的平面 上，因此功率结构体为三维结构体，有利于功率结构体的小型化设计。
前述实施例介绍了功率结构体，接下来介绍本申请实施例提供的交变电流模组，该交变电流模组包括：基于图1至图15所示的功率结构体。该交变电流模组具有体积小，集成度高，寄生参数小的优点。
接下来介绍本申请实施例提供的一种能源设备，该能源设备包括：基于图1至图15所示的功率结构体；
或者，
该能源设备包括前述的交变电流模组。
该能源设备具有体积小，集成度高，寄生参数小的优点。
接下来介绍本申请实施例提供的一种射频拉远单元，该射频拉远单元包括：前述的交变电流模组。该射频拉远单元具有体积小，集成度高，寄生参数小的优点。
通过前述实施例的举例说明可知，第一基板具有第一表面，第二基板具有第二表面，第一表面和第二表面相对设置，功率芯片设置于第二基板，从而功率芯片处于第一基板和第二基板之间，另外驱动芯片设置于第一基板，因此功率芯片和驱动芯片设置在两个基板上，功率芯片和驱动芯片属于基于两个基板的堆叠结构，提高了功率结构体的集成度。导电部件具有第一端和第二端，第一端与第一表面连接，第二端与第二表面连接，该导电部件可以将第一基板和第二基板连接起来，导电部件导通第一基板与第二基板，通过导电部件可实现第一基板和第二基板之间的电气传输，降低功率结构体的寄生参数，满足高频大功率领域的需求。
接下来以实际的应用场景对前述的功率结构体进行举例说明。
本申请实施例提供的功率结构体可以应用于无线5G增强型多进多出(massive multiple-input multiple-output)产品中，提高功率结构体的封装集成度，同时解决高频大功率器件的散热和寄生参数大的问题。
本申请实施例提供的功率结构体为利用导电部件互连双基板的三维高密高导热封装结构，将多个芯片堆叠合封，提高封装集成度，并且上下互连的结构减小了信号传输路径，堆叠结构的上基板设计有散热结构，适用于高频大功率领域。
如图16和图17所示，本申请实施例的功率结构体包含：带电路功能的下基板，带散热功能的上基板，驱动芯片(或者驱动功能芯片)，功率芯片，导电柱。可选的，功率结构体还可以包括：其他所需的电子元件以及封装体。
具体的，如图16所示，将多颗芯片组装在上基板上。如图17所示，下基板一面装配驱动芯片，如图11所示，下基板的另一面带有焊盘，实现功率结构体与其他部件的电气连接，可按需在上下基板组装其他元器件。如图1所示，利用导电柱将带散热功能的上基板和下基板互连。上基板芯片的电气传输通过导电柱实现，塑封后完成三维多芯片堆叠合封。
上基板带有散热功能，能为组装在上基板上的功率芯片提供散热渠道。利用导电柱互连上下基板为各信号的传输缩短路径，降低在高频领域应用的寄生参数，堆叠的功率结构体同时提高了封装的集成度。
上下基板通过倒扣的方式利用导电柱实现组装，该封装形式的加工工艺包括三大部分：上下基板的各自组装以及双基板的组装。上下基板的组装通过互连工艺，如D芯片贴装(die  attach)，引线键合(wire bond)，表面贴装技术(surface mount technology，SMT)完成芯片，元器件和基板的组装，双基板的组装通过导电柱(如铜柱)和互连结构(如焊料)实现上下基板的电气连接，最后一次塑封成型形成一个功率结构体。
如图10所示，为提高散热效果，可在上基板组装散热模块。
如图12和图13所示，为进一步提高封装集成度，下基板可以是埋嵌有芯片或其他电子元件的基板。
本申请实施例中，功率结构体为多芯片堆叠的双基板三维封装结构，提高了封装密度，降低了封装尺寸。带有散热功能的上基板提供良好的散热通道，解决了三维封装散热的难点；上下堆叠的封装结构，降低了寄生参数，拓展了在高频领域的应用，且上基板与外界无直接信号传输，有电气隔离的作用。
本申请实施例还提供一种功率结构体，所述功率结构体包括：第一基板，第二基板，驱动芯片，功率芯片和导电部件，其中，
所述第一基板的第一表面和所述第二基板的第二表面相对设置；
所述导电部件的第一端与所述第一表面连接，所述导电部件的第二端与所述第二表面连接；
所述功率芯片设置于所述第二基板；
所述驱动芯片设置于所述第二基板。
其中，驱动芯片可以设置在第二基板上，例如驱动芯片位于所述第二表面，且朝向所述第一表面。
通过前述实施例的举例说明可知，功率结构体包括：第一基板，第二基板，驱动芯片，功率芯片和导电部件。其中，第二基板具有第二表面，功率芯片位于第二表面，且朝向第一表面，从而功率芯片处于第一基板和第二基板之间，另外驱动芯片设置于第二基板，提高了功率结构体的集成度。导电部件具有第一端和第二端，第一端与第一表面连接，第二端与第二表面连接，该导电部件可以将第一基板和第二基板连接起来，导电部件导通第一基板与第二基板，通过导电部件可实现第一基板和第二基板之间的电气传输，降低功率结构体的寄生参数，满足高频大功率领域的需求。
前述实施例介绍了本申请实施例提供的一种功率结构体，接下来介绍本申请实施例提供另一种功率结构体，如图18所示，功率结构体包括：第一基板，第二基板，驱动芯片，功率芯片，导电线，第一封装体和粘性模，其中，
功率芯片位于第二基板的第二表面；
通过第一封装体对第二表面和第一功率芯片进行封装；
通过粘性模将第一基板粘贴在第一封装体上；
导电线，用于导通第一基板与第二基板；
驱动芯片设置于第一基板。
在本申请的一些实施例中，功率结构体还包括：导电部件，其中，所述导电部件的第一端与所述第二基板的第二表面连接。导电部件的第一端与第二基板的第二表面连接，从而第二基板可以通过导电部件进行电信号的输出。
在本申请的一些实施例中，为了区别本申请实施例中的多个功率芯片，将“功率芯片 位于第二基板的第二表面”中的功率芯片称为第一功率芯片。例如第一功率芯片位于第二表面。
其中，图18所示的第一基板和第二基板之间存在一定的空间，导电部件起到导电作用，第一表面为第一基板远离第一封装体的表面，例如第一基板的第一表面朝下。第四表面为第一基板靠近第一封装体的表面，例如第四基板的第四表面朝上。第二基板的第二表面是用于设置芯片的主表面，例如第二基板的第二表面朝下，第四表面和第二表面之间存在空间，第一功率芯片设置在第一基板和第二基板之间，第一基板与第一功率芯片固定在一起。其中，第一基板和第一功率芯片的固定方式有多种，例如第一基板和第一功率芯片直接固定在一起，或者第一功率芯片先封装之后再和第一基板固定。例如第一功率芯片可以通过焊料和第二基板连接。导电部件可以导通第一基板和第二基板。图18所示的功率结构体中，驱动芯片和第一功率芯片设置在不同的平面上，该功率结构体为三维结构体。导电部件可以导通第一基板和第二基板，从而减少了第一基板和第二基板之间的传输路径，减少了功率结构体的寄生参数。基于图18所示的功率结构体，可以实现功率结构体的器件小型化和高集成度。
其中，第一封装体包覆于第二基板的第二表面和第一功率芯片，第一封装体与前述的第二封装体的封装工艺可以相同或者不同。对第二基板的第二表面的第一功率芯片进行封装之后得到第一封装体，第一基板通过粘性模粘贴在第一封装体上，因此第一基板可以通过第一封装体与粘性模与第一功率芯片固定在一起，粘性模的材质和厚度不做限定。
需要说明的是，本申请实施例中不限定功率结构体中的导电部件的个数以及分布位置，不限定功率结构体中的驱动芯片的个数以及分布位置，不限定功率结构体中的第一功率芯片的个数以及分布位置，具体可以结合应用场景确定，此处仅为举例说明。
本申请的一些实施例中，如图19所示，功率结构体还包括：第二封装体，其中，第二封装体包覆于所述第一基板，所述第二基板的第二表面，所述驱动芯片和所述功率芯片。
本申请的一些实施例中，如图20所示，功率结构体还包括：导电部件，其中，所述导电部件的第一端与所述第二基板的第二表面连接。
第二封装体包覆于所述第一基板，所述第二基板的第二表面，所述驱动芯片，所述功率芯片和所述导电部件。其中，所述导电部件的第二端露出所述第二封装体。
其中，第二封装体起到对功率结构体的内部结构的封装作用，例如，第二封装体对第一基板，第二基板的第二表面，驱动芯片，第一功率芯片和导电线进行封装，从而可以得到封装后的功率结构体。又如该第二封装体对第一基板和第二基板之间的空间进行封装。第一功率芯片和导电线都被封装到该第二封装体中，从而可以得到密封的功率结构体。例如该功率结构体可以是通过导电部件互连双基板的三维高密封装结构。通过第二封装体的封装之后，导电部件的末端露出于第二封装体，因此导电部件可以用于功率结构体与外部器件的电气连接。
图20中以功率结构体包括两个导电部件为例，不限定的是，导电部件的个数还可以是1个或者多个，此处不做限定。
本申请的一些实施例中，功率结构体还包括：电子元件，其中，电子元件设置于第一基板的第一表面，和/或第二基板的第二表面。为便于描述以及图例说明，根据电子元件的 分布位置以及连接关系的不同，分别称为第一电子元件、第二电子元件以及第三电子元件等。例如，该电子元件具体为第一电子元件，如图21所示，功率结构体还包括：第一电子元件，其中，
第一电子元件设置于第四表面，且朝向第二表面。
其中，第一电子元件设置在第一基板的第四表面上，驱动芯片设置在第一基板的第一表面上，该第一电子元件可以设置在第一基板和第二基板之间的空间中，第一电子元件可以和第一功率芯片分布在不同的平面上，因此功率结构体为三维结构体，有利于功率结构体的小型化设计。本申请实施例中对于第一电子元件的个数不做限定。
需要说明的是，功率结构体还包括第一电子元件时，第二封装体包覆于第一基板，第二表面，驱动芯片，第一功率芯片、导电线，导电部件和第一电子元件。
本申请的一些实施例中，所述驱动芯片设置于所述第一基板的第一表面，或者嵌入于所述第一基板之内；所述功率芯片设置于所述第二基板的第二表面。例如，驱动芯片位于第一表面，且朝向第二表面。第一表面为所述第一基板远离所述第一封装体的表面。在上述方案中，驱动芯片和功率芯片设置在第一基板和第二基板之间，驱动芯片和功率芯片设置在不同的平面上，该功率结构体为三维结构体。可以实现功率结构体的器件小型化和高集成度。
在一种可能的实现方式中，驱动芯片设置于所述第二基板的第二表面；所述功率芯片设置于所述第二基板的第二表面。在上述方案中，功率结构体包括多个驱动芯片，有的驱动芯片设置于第一基板，有的驱动芯片设置于第二基板，驱动芯片和功率芯片设置在第一基板和第二基板之间，驱动芯片和功率芯片设置在不同的平面上，该功率结构体为三维结构体。可以实现功率结构体的器件小型化和高集成度。
如图22所示，功率结构体还包括：第二电子元件，其中，
第二电子元件设置于第二表面，且朝向第四表面。
其中，第二电子元件可以和第一功率芯片并排设置在第二基板的第二表面上，该第二电子元件可以设置在第一基板和第二基板之间的空间中，第二电子元件可以和驱动芯片分布在不同的平面上，因此功率结构体为三维结构体，有利于功率结构体的小型化设计。本申请实施例中对于第二电子元件的个数不做限定。
需要说明的是，功率结构体还包括第二电子元件时，第二封装体包覆于第一基板，第二表面，驱动芯片，第一功率芯片、导电部件和第二电子元件。
本申请的一些实施例中，如图23所示，功率结构体还包括：散热模块，其中，
散热模块设置于第二基板的第二表面的背面。
例如，第二基板具有第三表面，第二基板的第二表面和第三表面是相背的两个表面，第二基板的第三表面是第二基板的反面，例如第三表面用于设置散热模块。第一功率芯片和散热模块分别设置在第二基板的不同表面上，第一功率芯片被封装体封装，但是散热模块没有被封装体封装，因此散热模块可以用于对功率结构体的散热，例如该功率结构体可以是通过导电部件互连双基板的三维高密高导热封装结构。
本申请的一些实施例中，驱动芯片可以嵌入于第一基板之内。例如，如图24所示，第一基板为第一埋嵌式基板，其中，
在第一埋嵌式基板之内设有驱动芯片。
其中，如图24所示，驱动芯片埋设在第一埋嵌式基板中，因此在第一埋嵌式基板和第二基板之间只需要设置第一功率芯片和导电部件即可，可以进一步的缩小功率结构体的体积，有利于功率结构体的小型化设计。
本申请的一些实施例中，功率芯片可以嵌入于第一基板之内。例如，如图25所示，功率结构体还包括：第二功率芯片，
第一基板为第二埋嵌式基板，其中，
在第二埋嵌式基板之内设有第二功率芯片。
其中，如图25所示，驱动芯片可以设置在第二埋嵌式基板的第一表面上，在第二埋嵌式基板之内设有第二功率芯片，因此在第二埋嵌式基板和第二基板之间只需要设置第一功率芯片和导电部件即可，可以进一步的缩小功率结构体的体积，有利于功率结构体的小型化设计。
需要说明的是，图25和图24的区别在于埋嵌式基板中埋嵌的单元不同。例如图24中在第一埋嵌式基板之内设驱动芯片，图25中在第二埋嵌式基板之内设第二功率芯片。不限定的是，功率结构体中的埋嵌式基板中还可以同时埋嵌驱动芯片和第二功率芯片，此处不做限定。
本申请的一些实施例中，电子元件可以嵌入于第一基板之内。例如，如图26所示，功率结构体还包括：第三电子元件，
第一基板为第三埋嵌式基板，其中，
在第三埋嵌式基板之内设有第三电子元件。
其中，如图26所示，驱动芯片可以设置在第三埋嵌式基板的第一表面上，在第三埋嵌式基板之内设有第三电子元件，因此在第三埋嵌式基板和第二基板之间只需要设置第一功率芯片和导电部件即可，可以进一步的缩小功率结构体的体积，有利于功率结构体的小型化设计。
需要说明的是，图25和图26的区别在于埋嵌式基板中埋嵌的单元不同。例如图25中在第二埋嵌式基板之内设第二功率芯片，图26中在第三埋嵌式基板之内设第三电子元件。不限定的是，功率结构体中的埋嵌式基板中还可以同时埋嵌第二功率芯片和第三电子元件，此处不做限定。
本申请的一些实施例中，如图27所示，功率结构体还包括：第四电子元件，其中，
第四电子元件设置于第一基板的第一表面。
其中，第一基板的第四表面和第一表面是相背的两个表面，第一基板的第一表面是第一基板的反面，例如第四表面用于设置第四电子元件。第四电子元件可以设置在第一基板的第一表面上，第四电子元件和第一功率芯片分布在不同的平面上，因此功率结构体为三维结构体，有利于功率结构体的小型化设计。
本申请的一些实施例中，如图27所示，驱动芯片位于第一基板的第一表面。
其中，第一基板的第四表面和第一表面是相背的两个表面，驱动芯片可以设置在第一基板的第一表面上，驱动芯片和第一功率芯片分布在不同的平面上，因此功率结构体为三维结构体，有利于功率结构体的小型化设计。
本申请的一些实施例中，如图28所示，功率结构体还包括：第三功率芯片，其中，
第三功率芯片位于第四表面，且朝向第二表面。
其中，功率结构体中可以包括多个功率芯片，例如功率结构体中包括第一功率芯片和第三功率芯片，第一功率芯片设置在第二基板上，第三功率芯片设置在第一基板上。第三功率芯片设置在第一基板的第四表面上，该第三功率芯片可以设置在第一基板和第二基板之间的空间中，第三功率芯片可以和第一功率芯片分布在不同的平面上，因此功率结构体为三维结构体，有利于功率结构体的小型化设计。
前述实施例介绍了功率结构体，接下来介绍本申请实施例提供的交变电流模组，该交变电流模组包括：基于图18至图28所示的功率结构体。该交变电流模组具有体积小，集成度高，寄生参数小的优点。
接下来介绍本申请实施例提供的一种能源设备，该能源设备包括：基于图18至图28所示的功率结构体；
或者，该能源设备包括前述的交变电流模组。
该能源设备具有体积小，集成度高，寄生参数小的优点。
接下来介绍本申请实施例提供的一种射频拉远单元，该射频拉远单元包括：前述的交变电流模组。该射频拉远单元具有体积小，集成度高，寄生参数小的优点。
通过前述实施例的举例说明可知，第二基板具有第二表面，功率芯片位于第二表面，第一基板通过粘性模粘贴于第一封装体上，从而功率芯片处于第一基板和第二基板之间，另外驱动芯片设置于第一基板，因此功率芯片和驱动芯片设置在两个基板上，功率芯片和驱动芯片属于基于两个基板的堆叠结构，提高了功率结构体的集成度。导电线的两端分别连接第一基板与第二基板，通过导电线可实现第一基板和第二基板之间的电气传输，降低功率结构体的寄生参数，满足高频大功率领域的需求。
接下来介绍制备图18至图28所示的功率结构体的方法，如图29所示，该方法主要包括如下流程：
S01.将功率芯片置于第二基板的第二表面；
S02.将第一封装体包覆于所述第二基板的第二表面和所述功率芯片；
S03.通过粘性模将所述第一基板粘贴于所述第一封装体上；
S04.将驱动芯片置于所述第一基板；
S05.将导电线的一端连接第一基板，导电线的另一端连接第二基板。
本申请的一些实施例中，方法还包括：
将导电部件的第一端与所述第二基板的第二表面连接。
本申请的一些实施例中，方法还包括：
将第二封装体包覆于所述第一基板，所述第二基板的第二表面，所述驱动芯片，所述功率芯片和所述导电部件，
其中，所述导电部件的第二端露出所述第二封装体。
本申请的一些实施例中，将驱动芯片置于所述第一基板，包括：
将所述驱动芯片设置于所述第一基板的第一表面，或者嵌入于所述第一基板之内；
所述将功率芯片置于第二基板的第二表面，包括：
将所述功率芯片设置于所述第二基板的第二表面。
本申请的一些实施例中，方法还包括：
将电子元件置于所述第一基板的第一表面，和/或所述第二基板的第二表面，
其中，所述第一表面为所述第一基板远离所述第一封装体的表面。
本申请的一些实施例中，将散热模块置于所述第二基板的第二表面的背面。
可以理解的是，图29所示的方法可以制备得到图18至图28中所示的功率结构体，对于本申请实施例中功率结构体的制备过程的说明，详见前述实施例，在此处的方法实施例中不再赘述。
通过前述实施例的举例说明可知，第二基板具有第二表面，功率芯片位于第二表面，第一基板通过粘性模粘贴于第一封装体上，从而功率芯片处于第一基板和第二基板之间，另外驱动芯片设置于第一基板，因此功率芯片和驱动芯片设置在两个基板上，功率芯片和驱动芯片属于基于两个基板的堆叠结构，提高了功率结构体的集成度。导电线的两端分别连接第一基板与第二基板，通过导电线可实现第一基板和第二基板之间的电气传输，降低功率结构体的寄生参数，满足高频大功率领域的需求。
接下来以实际的应用场景对前述的功率结构体进行举例说明。
本申请实施例提供的功率结构体可以应用于无线5G增强型多进多出(massive multiple-input multiple-output)产品中，提高功率结构体的封装集成度，同时解决高频大功率器件的散热和寄生参数大的问题。
本申请实施例提供的功率结构体为利用导电部件互连双基板的三维高密高导热封装结构，将多个芯片堆叠合封，提高封装集成度，并且上下互连的结构减小了信号传输路径，堆叠结构的上基板设计有散热结构，适用于高频大功率领域。
如图30和图31所示，本申请实施例的功率结构体包含：带电路功能的下基板，带散热功能的上基板，驱动芯片(或者驱动功能芯片)，功率芯片，导电线。可选的，功率结构体还可以包括：其他所需的电子元件以及第二封装体、第一封装体、导电部件。
与前述图16、图17的实施例相比，如图30所示，此实施例改变了双基板倒扣的封装模式，将基板堆叠组装，功率芯片组装在具有散热功能的上基板上。而后进行功率芯片部分的塑封，得到第一封装体，如图31所示。并在第一封装体的表面粘贴一层粘性膜，再将贴装有驱动芯片的下基板组装在第一封装体上，按需完成电气互连工艺，最后使用第二封装体进行封装，得到图18所示的功率结构体。组装在上基板的导电部件用于功率芯片的信号传输，塑封后露出的导电部件用于功率结构体与外部的电气互连。
在申请实施例中，功率结构体为多芯片堆叠的双基板三维封装结构，提高了封装密度，降低了封装尺寸。带有散热功能的上基板提供良好的散热通道，解决了三维封装散热的难点；上下堆叠的封装结构，降低了寄生参数，拓展了在高频领域的应用，且上基板与外界无直接信号传输，有电气隔离的作用。
另外需说明的是，以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。另外，本申请提供的装 置实施例附图中，模块之间的连接关系表示它们之间具有通信连接，具体可以实现为一条或多条通信总线或信号线。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本申请可借助软件加必需的通用硬件的方式来实现，当然也可以通过专用硬件包括专用集成电路、专用CPU、专用存储器、专用元器件等来实现。一般情况下，凡由计算机程序完成的功能都可以很容易地用相应的硬件来实现，而且，用来实现同一功能的具体硬件结构也可以是多种多样的，例如模拟电路、数字电路或专用电路等。但是，对本申请而言更多情况下软件程序实现是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在可读取的存储介质中，如计算机的软盘、U盘、移动硬盘、ROM、RAM、磁碟或者光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述的方法。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。
所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存储的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘(Solid State Disk，SSD))等。

Claims (23)

  1. 一种功率结构体，其特征在于，所述功率结构体包括：第一基板，第二基板，驱动芯片，功率芯片和导电部件，其中，
    所述第一基板的第一表面和所述第二基板的第二表面相对设置；
    所述导电部件的第一端与所述第一表面连接，所述导电部件的第二端与所述第二表面连接；
    所述驱动芯片设置于所述第一基板；
    所述功率芯片设置于所述第二基板。
  2. 根据权利要求1所述的功率结构体，其特征在于，所述功率结构体还包括：封装体，所述封装体包覆于所述第一基板的第一表面，所述第二基板，所述驱动芯片，所述功率芯片和所述导电部件。
  3. 根据权利要求1或2所述的功率结构体，其特征在于，
    所述驱动芯片设置于所述第一基板的第一表面，或者嵌入于所述第一基板之内；
    所述功率芯片设置于所述第二基板的第二表面。
  4. 根据权利要求1至3中任一项所述的功率结构体，其特征在于，所述第一端与所述第一表面焊接，所述第二端与所述第二表面焊接。
  5. 根据权利要求1至4中任一项所述的功率结构体，其特征在于，所述功率结构体还包括：电子元件，其中，
    所述电子元件设置于所述第一基板的第一表面和/或所述第二基板的第二表面。
  6. 根据权利要求1至5中任一项所述的功率结构体，其特征在于，所述功率结构体还包括：散热模块，其中，
    所述散热模块设置于所述第二基板的第二表面的背面。
  7. 根据权利要求1至6中任一项所述的功率结构体，其特征在于，所述第二基板为陶瓷覆铜板。
  8. 一种功率结构体，其特征在于，所述功率结构体包括：第一基板，第二基板，驱动芯片，功率芯片，导电线，第一封装体和粘性模，其中，
    所述功率芯片位于所述第二基板的第二表面；
    所述第一封装体包覆于所述第二基板的第二表面和所述功率芯片；
    所述第一基板通过所述粘性模粘贴于所述第一封装体上；
    所述驱动芯片设置于所述第一基板；
    所述导电线的一端连接所述第一基板，所述导电线的另一端连接所述第二基板。
  9. 根据权利要求8所述的功率结构体，其特征在于，所述功率结构体还包括：导电部件，其中，
    所述导电部件的第一端与所述第二基板的第二表面连接。
  10. 根据权利要求9所述的功率结构体，其特征在于，所述功率结构体还包括：第二封装体，其中，
    所述第二封装体包覆于所述第一基板，所述第二基板的第二表面，所述驱动芯片，所述功率芯片和所述导电部件，
    其中，所述导电部件的第二端露出所述第二封装体。
  11. 根据权利要求8至10中任一项所述的功率结构体，其特征在于，
    所述驱动芯片设置于所述第一基板的第一表面，或者嵌入于所述第一基板之内；
    所述功率芯片设置于所述第二基板的第二表面。
  12. 根据权利要求8至11中任一项所述的功率结构体，其特征在于，所述功率结构体还包括：电子元件，其中，
    所述电子元件设置于所述第一基板的第一表面，和/或所述第二基板的第二表面，
    其中，所述第一表面为所述第一基板远离所述第一封装体的表面。
  13. 根据权利要求8至12中任一项所述的功率结构体，其特征在于，所述功率结构体还包括：散热模块，其中，
    所述散热模块设置于所述第二基板的第二表面的背面。
  14. 根据权利要求8至13中任一项所述的功率结构体，其特征在于，所述第二基板为陶瓷覆铜板。
  15. 一种功率结构体的制备方法，其特征在于，包括：
    将功率芯片置于第二基板的第二表面；
    将第一封装体包覆于所述第二基板的第二表面和所述功率芯片；
    通过粘性模将所述第一基板粘贴于所述第一封装体上；
    将驱动芯片置于所述第一基板；
    将导电线的一端连接所述第一基板，所述导电线的另一端连接所述第二基板。
  16. 根据权利要求15所述的方法，其特征在于，所述方法还包括：
    将导电部件的第一端与所述第二基板的第二表面连接。
  17. 根据权利要求16所述的方法，其特征在于，所述方法还包括：
    将第二封装体包覆于所述第一基板，所述第二基板的第二表面，所述驱动芯片，所述功率芯片和所述导电部件，
    其中，所述导电部件的第二端露出所述第二封装体。
  18. 根据权利要求15至17中任一项所述的方法，其特征在于，所述将驱动芯片置于所述第一基板，包括：
    将所述驱动芯片设置于所述第一基板的第一表面，或者嵌入于所述第一基板之内；
    所述将功率芯片置于第二基板的第二表面，包括：
    将所述功率芯片设置于所述第二基板的第二表面。
  19. 根据权利要求15至18中任一项所述的方法，其特征在于，所述方法还包括：
    将电子元件置于所述第一基板的第一表面，和/或所述第二基板的第二表面，
    其中，所述第一表面为所述第一基板远离所述第一封装体的表面。
  20. 根据权利要求15至19中任一项所述的方法，其特征在于，所述方法还包括：
    将散热模块置于所述第二基板的第二表面的背面。
  21. 一种交变电流模组，其特征在于，所述交变电流模组包括：如权利要求1至7中任一项所述的功率结构体，或者如权利要求8至14中任一项所述的功率结构体。
  22. 一种能源设备，其特征在于，所述能源设备包括：权利要求1至7中任一项所述的功率结构体，或者如权利要求8至14中任一项所述的功率结构体；
    或者，
    所述能源设备包括如权利要求21所述的交变电流模组。
  23. 一种射频拉远单元，其特征在于，所述射频拉远单元包括：如权利要求21所述的交变电流模组。
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