CN111033731B - 模制芯片组合 - Google Patents

模制芯片组合 Download PDF

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Publication number
CN111033731B
CN111033731B CN201880051822.9A CN201880051822A CN111033731B CN 111033731 B CN111033731 B CN 111033731B CN 201880051822 A CN201880051822 A CN 201880051822A CN 111033731 B CN111033731 B CN 111033731B
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semiconductor chip
chip
device region
physical device
interconnect
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CN111033731A (zh
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米林德·S·巴格瓦特
傅磊
伊沃·巴伯
梁家坚
拉胡尔·阿加瓦尔
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Abstract

公开了各种模制芯片组合以及其制造方法。在一个方面，提供一种模制芯片组合，所述模制芯片组合包括：第一半导体芯片(20)，所述第一半导体芯片具有第一PHY区(75)；第二半导体芯片(19)，所述第二半导体芯片具有第二PHY区(65)；互连芯片(85)，所述互连芯片将所述第一PHY区互连到所述第二PHY区；以及模制件(25)，所述模制件将所述第一半导体芯片、所述第二半导体芯片和所述互连芯片接合在一起。

Description

模制芯片组合
发明背景
常规类型的多芯片模块包括并排安装在载体基板上或在一些情况下安装在中介层(所谓的“2.5D”)上(即，依次安装在载体基板上)的两个半导体芯片。半导体芯片被倒装芯片地安装到载体基板，并且通过相应的多个焊料接头与其互连。载体基板具备多个电路径以为半导体芯片提供用于芯片间供电、接地和信号传播以及来自中介层自身的输入/输出的输入/输出路径。所述半导体芯片包括相应的底填材料层，以减少由于芯片、中介层和焊料接头的热膨胀系数的差异而引起的差分热膨胀的影响。
基于2.5D中介层的多芯片模块的一个常规变体使用具有多个内部导体迹线的硅中介层以实现中介层上的并排安装的两个芯片之间的互连。所述中介层被制造成具有许多穿硅通孔(TSV)，以提供所安装的芯片与在其上安装中介层的封装基板之间的路径。使用大量处理步骤来制造TSV和迹线。
另一常规的多芯片模块技术是2D晶片级扇出(或2D WLFO)。常规的2D WLFO技术是基于将裸片嵌入到模制晶片中，还称为“晶片重建”。通过标准的晶片级处理流来处理模制晶片以产生最终的集成电路组件结构。裸片的有效表面与模具化合物共面，从而允许使用常规的再分配层(RDL)处理将导电铜迹线和焊料球衬垫“扇出”到模制区域中。常规的3DWLFO使2D技术扩展到多芯片堆叠中，其中将第二封装基板安装在2D WLFO上。
一些其他常规设计使用嵌入式互连桥(EMIB)。这些通常是嵌入封装基板的上部段中的硅桥芯片(但偶尔是仅具有顶侧输入端/输出端的有机小芯片)。
附图说明
在阅读了以下详细描述并且参考附图之后，本发明的前述和其他优势将变得显而易见，附图中：
图1是包括示例性模制芯片组合的示例性半导体芯片装置的示图；
图2是在截面2-2处取得的图1的截面图；
图3是以增加的放大倍率示出的图2的一部分；
图4是描绘示例性临时多芯片安装的截面图；
图5是描绘示例性临时多芯片安装的截面图；
图6是描绘多个芯片的示例性模制的截面图；
图7是描绘芯片的额外处理的截面图；
图8是描绘芯片的额外处理的截面图；
图9是描绘芯片的额外处理的截面图；
图10是描绘芯片的额外处理的截面图；
图11是以更大的放大倍率描绘图10的一部分的截面图；
图12是描绘芯片的额外处理的截面图；
图13是描绘芯片的额外处理的截面图；
图14是以更大的放大倍率描绘图13的一部分的截面图；
图15是描绘芯片上的互连芯片的示例性安装的截面图；
图16是以更大的放大倍率描绘图15的一部分的截面图；
图17是描绘芯片的额外处理的截面图；
图18是描绘芯片的额外处理的截面图；
图19是描绘芯片的额外处理的截面图；
图20是描绘示例性电路板上的芯片的示例性安装的截面图；
图21是描绘芯片上的散热片的示例性安装的截面图；
图22是类似于图2的截面图，但是具有替代性示例性模制芯片组合的替代性示例性半导体芯片装置的截面图；
图23是描绘图22的装置上的示例性互连芯片安装的截面；
图24是描绘示例性板安装和模制的截面图；
图25是描绘模制芯片组合上的散热片的示例性安装的截面图；
图26是描绘半导体芯片的PHY区衬垫和非PHY区衬垫的小部分的示例性初始处理的截面图；
图27是在图26中描绘的PHY区和非PHY区的平面图；
图28是类似于图26的截面图，但描绘对芯片的示例性额外处理；
图29是类似于图28的截面图，但描绘对芯片的示例性额外处理；
图30是在图29中描绘的芯片的部分的平面图；
图31是在图30中描绘的遮掩层的示图；
图32是在图29中描绘的芯片的部分在额外的处理之后的平面图；
图33是描绘对芯片的额外处理的分解示图；
图34是类似于28的截面图，但描绘对芯片的示例性额外处理；
图35是在图34中描绘的芯片的一部分的平面图；以及
图36是示例性重建的模制芯片组合晶片的示图。
具体实施方式
芯片几何形状在过去的几年里已经不断下降。然而，芯片大小的收缩已经伴随着给定芯片的输入端/输出端的数目的相伴的增加。这已经导致需要极大地增加多芯片模块的芯片-芯片互连件的数目。当前2D和3D WLFO具有有限的最小行间距，大约2.0μm/行和空间。另外，常规的WLFO技术使用多个固化的聚酰亚胺膜来产生必要的RDL层。这些聚酰亚胺膜往往是机械应力，并且因此是翘曲源，并且它们的相对高的烘烤温度可能会不利地影响其他敏感装置。最后，WLFO和EMIB两者中的芯片的拾取和放置准确度仍然是个挑战。
根据本发明的一个方面，提供一种模制芯片组合，所述模制芯片组合包括：第一半导体芯片，所述第一半导体芯片具有第一PHY区；第二半导体芯片，所述第二半导体芯片具有第二PHY区；互连芯片，所述互连芯片将所述第一PHY区互连到所述第二PHY区；以及模制件，所述模制件将所述第一半导体芯片、所述第二半导体芯片和所述互连芯片接合在一起。
在所述模制芯片组合中，所述第一半导体芯片包括用于在将所述模制芯片组合安装在电路板上时连接到所述电路板的第一多个互连件，并且所述第二半导体芯片包括用于在将所述模制组合安装在所述电路板上时连接到所述电路板的第二多个互连件。
在所述模制芯片组合中，所述第一半导体芯片包括连接到所述第一互连件的第一非PHY区，并且所述第二半导体芯片包括连接到所述第二互连件的第二非PHY区。
在所述模制芯片组合中，所述模制件包括第一模制材料层和第二模制材料层。
所述模制芯片组合包括定位在所述第一模制材料层与所述第二模制材料层之间的聚合物层。
所述模制芯片组合包括电路板和安装在所述电路板上的所述模制芯片组合。
在所述模制芯片组合中，所述第一半导体芯片包括处理器并且所述第二半导体芯片包括存储器芯片。
根据本发明的另一方面，提供一种模制芯片组合，所述模制芯片组合包括：第一半导体芯片，所述第一半导体芯片具有第一PHY区；第二半导体芯片，所述第二半导体芯片具有第二PHY区；互连芯片，所述互连芯片将所述第一PHY区互连到所述第二PHY区；第一模制材料层，所述第一模制材料层将所述第一半导体芯片和所述第二半导体芯片接合在一起；以及第二模制材料层，所述第二模制材料层接合到所述第一模制材料层并且至少部分地封装所述互连芯片。
在所述模制芯片组合中，所述第一半导体芯片包括用于在将所述模制芯片组合安装在电路板上时连接到所述电路板的第一多个互连件，并且所述第二半导体芯片包括用于在将所述模制组合安装在所述电路板上时连接到所述电路板的第二多个互连件。
在所述模制芯片组合中，所述第一半导体芯片包括连接到所述第一互连件的第一非PHY区，并且所述第二半导体芯片包括连接到所述第二互连件的第二非PHY区。
所述模制芯片组合包括定位在所述第一模制材料层与所述第二模制材料层之间的聚合物层。
所述模制芯片组合包括电路板和安装在所述电路板上的所述模制芯片组合。
在所述模制芯片组合中，所述第一半导体芯片包括处理器并且所述第二半导体芯片包括存储器芯片。
根据本发明的另一方面，提供一种制造模制芯片组合的方法。所述方法包括使用互连芯片将第一半导体芯片的第一PHY区互连到第二半导体芯片的第二PHY区，并且将所述第一半导体芯片、所述第二半导体芯片和所述互连芯片模制在一起。
所述方法包括制造所述第一半导体芯片上的用于在将所述模制芯片组合安装在电路板上时连接到所述电路板的第一多个互连件，和所述第二半导体芯片上的用于在将所述模制组合安装在所述电路板上时连接到所述电路板的第二多个互连件。
在所述方法中，所述第一半导体芯片包括连接到所述第一互连件的第一非PHY区，并且所述第二半导体芯片包括连接到所述第二互连件的第二非PHY区。
在所述方法中，所述模制包括使用第一模制材料层将所述第一半导体芯片模制到所述第二半导体芯片，并且模制第二模制材料层以至少部分地囊封所述互连芯片。
所述方法包括在所述第一模制材料层与所述第二模制材料层之间施加聚合物层。
所述方法包括将所述模制芯片组合安装在电路板上。
在所述方法中，所述第一半导体芯片包括处理器并且所述第二半导体芯片包括存储器芯片。
在下文描述的图式中，在相同的元件在一个以上图中出现的情况下一般重复参考数字。现在转向图式，并且具体来说，转向图1，其为示例性半导体芯片装置10的示图。半导体芯片装置10包括模制芯片组合13，可以将所述模制芯片组合安装在电路板15上，所述电路板可以是系统板、电路卡、半导体芯片封装基板或其他。电路板15可以通过在此布置中构成焊料球的多个互连结构17与某一其他电气结构(例如，另一电路板或其他结构)电介接。然而，熟练技术人员将了解，可以使用除了焊料球之外的各种类型的互连结构，例如销、焊盘栅格阵列结构或其他类型的互连件。模制芯片组合13包括多个半导体芯片，其中的两者分别被示出和标记为19和20，并且其两者至少部分地被囊封在模制材料25中。在此布置中，模制材料25可以由两个模制层30和35组成。如在下文更详细地描述，可以通过另一半导体芯片电子地连接半导体芯片19和20，所述另一半导体芯片被模制材料25遮蔽，并且因此在图1中不可见，但将在下文描述并且在后续的图中示出。
可以通过现在还参看图2来理解半导体芯片装置10的额外细节，图2是在截面2-2处取得的图1的截面图。模制芯片组合13的模制材料25是由模制层30、模制层35和夹在模制层30和35之间的聚合物层50组成。模制层35横向地包围半导体芯片19和20，但半导体芯片19和20的相应的上表面55和60仍然暴露，以促进随后任选地将散热器放置在半导体芯片19和20上。合意的是，针对模制层30和35而选择的材料在适用的模制温度下展现合适的粘度并且具有比在模制过程时存在的焊料结构中的任一者的熔点低的模制温度。在示例性布置中，用于模制层30和35的材料可以具有约165℃的模制温度。两种商用变体是SumitomoEME-G750和G760。
半导体芯片19和20可以是多种集成电路中的任一者。示例的非详尽列表包括微处理器、图形处理单元、组合以上两者的各方面的应用处理单元、存储器装置、应用集成专用电路或其他。半导体芯片19构造有：物理装置或“PHY”区，其具有专用于传输芯片-芯片信号的各种内部和外部导体结构；以及非PHY区70，其具有更多地针对输送电力和接地和/或芯片-电路板信号而定制的导体结构。半导体芯片20类似地包括PHY区75和非PHY区80，其具有与半导体芯片19的PHY区65和非PHY区70相同的功能。如上文简述，通过另一半导体芯片，即，互连芯片85，将半导体芯片19和20电连接。半导体芯片19和20以及互连芯片85可以由硅、锗或其他半导体材料构造，并且可以是整块半导体、绝缘体上半导体或其他设计。互连芯片85包括多条内部导体迹线，所述多条内部导体迹线在需要时可以处于多个层级或单个层级上。示出所述迹线中的两者并且共同地标记为90。迹线90通过导电路径95与半导体芯片19和20的PHY区65和75的导体结构电介接，所述导电路径具有图2中的尺度和大小，使得交叉影线并非实际并且因此被描绘成每三个矩形的许多白色堆叠。然而，后续的图将描绘这些导电路径95的额外细节。半导体芯片19的非PHY区70可以通过多个导电支柱100与电路板15电介接。每种导电支柱100通过相应的导体衬垫105电连接到半导体芯片19并且通过焊料互连件110电连接到电路板15，所述焊料互连件在需要时可以是焊料凸块或微凸块。半导体芯片20的非PHY区80类似地通过可以与半导体芯片19的导电支柱100、衬垫105和焊料凸点110基本上类似的多个导电支柱115、导体衬垫120和焊料凸点125而电连接到电路板15。应注意，导电支柱100横越多个绝缘层，即，从下到上的模制层30、聚合物层50和钝化结构130。钝化结构130可以是各种绝缘材料的叠层，所述绝缘材料例如为二氧化硅、氮化硅或其他介电材料。导电支柱115类似地横越半导体芯片20的模制层30、聚合物层50和钝化结构135，所述钝化结构可以类似于刚刚描述的钝化结构130。导电支柱100和115可以由各种导体材料组成，所述导体材料例如为铜和将要在下文更详细地描述的其他导体材料。导电衬垫105和120可以由铝、铜或各种其他导体材料组成。焊料凸块110和125可以由各种众所周知的焊料组合物组成，例如锡银、锡银铜或其他。聚合物层50优选地由聚苯并恶唑组成，但可以使用其他聚合物材料，例如苯并环丁烯、低温聚酰亚胺或固化温度低于约200℃的其他聚合物。聚合物层50被设计成担当应力缓冲器、隔离膜并且可以实现再分配层布设。
电路板15可以是有机的或陶瓷的并且是单层，或更常见地是多层。为了缓冲失配的热膨胀系数的影响，底填材料140可以定位在模制层30与电路板15的上表面之间，并且可以在需要时横向地延伸超过模制层30的左边缘和右边缘(并且那些边缘不可见)。底填材料140可以由众所周知的聚合物底填材料组成。
可以通过现在参看还图3来理解PHY区65和75与互连芯片85之间的导电路径95的额外细节，图3描绘与互连芯片85和芯片19的PHY区65相关联的导电路径95中的一者的一部分。应理解，此描述还将说明其他导电路径95。与半导体芯片19相关联的导电路径95的部分可以包括：导体衬垫145，其连接到半导体芯片中的不可见的其他导体迹线或通孔；以及导电微型支柱150，其被镍金盖帽155加盖。镍金盖帽155充当屏障层和焊料可润湿表面。其他可能的材料包括镍钒、铂、钯、纯金等。凸块下金属化160定位在导电支柱150与导体衬垫145之间。导体衬垫145可以由铝、铜、金、银、这些的组合等构造。UBM结构160可以由溅镀的钛、钨和铜组成并且还可以包括镍、钒或其他材料。应注意，凸块下金属化160、导电微型支柱150和镍金盖帽155的组合横越半导体芯片19的钝化结构130和聚合物层50。与互连芯片85相关联的导电路径95的部分可以包括导体衬垫165，所述导体衬垫与导体衬垫145类似地电连接到设置在互连芯片85中但出于说明简单起见未示出的一条或多条导电迹线或通孔。由与在本文其他地方描述的钝化结构130和135相同类型的材料组成的钝化结构166部分地覆盖导体衬垫165。屏障层/粘附层167形成于导体衬垫165上，并且优选地由Ti-W和铜、接着是在图中继续向上的铜层170、镍层175和另一铜层180组成。铜层180被焊料微型凸块185加盖。熟练技术人员将了解，可以依据所涉及的成分来改变导体材料的选择。举例来说，镍、金和镍以及金或甚至钒可以用作屏障层以防止焊料成分迁移到其他导电层中或反之亦然。焊料微型凸块185可以由多种优选为无铅的焊料组成，例如锡铜银、锡银或其他类型的焊料。镍金盖帽155被设计成为焊料微型凸块185提供良好的焊料可润湿层，同时还提供屏障层功能性。如上文所述，在图3中描绘的导体路径95可以用于在图2中描绘以及在上文描述的其他导电路径95。
可以通过现在参看图4、图5、图6、图7、图8、图9、图10、图11、图12、图13、图14、图15、图16、图17、图18、图19和图20并且起初参看图4来理解用于制造在图1和图2中描绘的半导体芯片装置10的示例性过程。图4描绘半导体芯片19和20的截面以及在将所述半导体芯片组装为在图1和图2中描绘的模制芯片组合13之前它们将处于的状态下的自立式半导体芯片。应注意，在图4中，示出半导体芯片19和20从在图1和图2中描绘的定向翻转过来。可以将半导体芯片19和20一同制造在半导体晶片(未示出)中，随后将所述半导体晶片单体化以产生单独的半导体芯片19和20。在这些制造过程期间，可以构造各种电子结构，所述电子结构包括晶体管、电容器、电感器和对于芯片19和20来说适当的任何其他逻辑元件和电路结构，可以分别在芯片19和20中确立前述PHY区65和75和非PHY区70和80。在此方面，可以将半导体芯片19制造至以下状态：已经制造出导体衬垫105和145以及钝化结构130，和所述钝化结构130中的暴露下面的导体衬垫105的多个开口190，和穿过钝化结构130的通向导体衬垫145的多个开口195。可以类似地将半导体芯片20制造至以下状态：已经制造出非PHY区80中的导体衬垫120，并且已经确立PHY区75中的导体衬垫145以及钝化结构135中的开口200还有钝化结构135中的通向导体衬垫145的多个开口205。可以使用众所周知的材料沉积技术，例如镀敷、溅镀、化学气相沉积、这些的组合等，来制造导体衬垫105、120和145。可以使用众所周知的光刻和方向性蚀刻技术来形成开口190、195、200和205。
接下来并且如图5中所示，可以将半导体芯片19和20从在图4中示出的定向翻转过来并且安装到载体基板210。可以通过光激活粘合剂(未示出)或其他临时紧固技术将半导体芯片19和20固定到载体基板210，因为预期随后在各个处理步骤之后移除载体晶片210。
接下来并且如图6中描绘，通过在约165℃下对合适的化合物(例如，SumitomoEME-G750或G760)进行压缩模制达约60分钟至120分钟而形成模制层35。此压缩模制过程将起初囊封半导体芯片19和20并且覆盖载体基板210的另外未覆盖的部分。因为需要分别暴露半导体芯片19和20的上表面55和60，所以模制层35可以经历在图7中描绘的研磨过程以暴露那些表面55和60。此时，半导体芯片19和20仍然安装在载体基板210上，但通过模制层35被横向地机械接合。
接下来，并且如图8中所示，可以使半导体芯片19和20和模制层35与在图7中描绘的载体基板210分离，并且从在图7中描绘的定向翻转过来。此时，可以将聚合物层50施加在半导体芯片19和20和模制层35两者上。可以使用众所周知的旋涂和烘烤技术施加聚合物层50，并且因为可以使用毯覆式沉积过程，所以各个开口190、195、200和205此时可以填有聚合物层50材料。如图9中所示，为了重新暴露半导体芯片19的各个导体衬垫105和145以及半导体芯片20的导体衬垫120和145，可以适当地遮掩聚合物层50并且对其光刻图案化，即，通过光刻，以便分别确立至导体衬垫105的开口215、至导体衬垫145和半导体芯片19的开口220，以及至半导体芯片20的导体衬垫145和120的开口220和225。
接下来并且如图10中所示，将抗蚀剂掩模235施加在聚合物层50上并且适当地图案化以确立通向半导体芯片19的导体衬垫145的开口240和通向半导体芯片20的导体衬垫145的开口245。此处，抗蚀剂掩模235的用途是分别遮掩半导体芯片19和20的导体衬垫105和120，使得可以制造与芯片19和20中的每一者的导体衬垫145相关联的各种导体结构。可以通过现在还参看图11来理解此制造步骤的额外细节，图11是以更大的放大倍率示出的由虚线矩形250圈出的图10的部分。应注意，框250圈出半导体芯片19的PHY区65的一部分和因此导体衬垫105中的一者和导体衬垫145中的一者。应理解，在图11中说明的结构说明半导体芯片19的其他类似的导体结构和芯片20的PHY区75中的那些导体结构。还应理解，如图11中所示，在施加抗蚀剂掩模235之前，可以使用众所周知的溅镀和/或CVD技术来沉积UBM160(也在图3中描绘)。此溅镀过程可以毯覆式沉积如所示的UBM 160。其后，可以使用众所周知的技术通过旋涂和烘烤来施加抗蚀剂掩模235。可以在抗蚀剂掩模235中光刻图案化开口240(在图11中说明其中的一者)，且其后，可以使用上文结合图3以及镍金盖帽155所描述的技术来制造微型支柱150。通过开口240和类似的开口245来施加多种导体材料252。如上文所述，微型支柱150横越半导体芯片19的钝化结构130以及聚合物层50的一部分。应注意，在此所说明的布置中的导体衬垫145和105被制造成具有相应的横向尺寸(直径或可能其他形状)x1和x2，其中x2＞x1。然而，在下文描述的另一布置中，半导体芯片19被制造成其中x1和x2是大致相同大小。这种情况呈现出通过另一所公开的技术解决的技术问题。
接下来并且如图12中所示，使用众所周知的抛光和溶剂剥离技术来剥离在图11中示出的抗蚀剂掩模235，并且使用众所周知的旋涂和烘烤技术来施加另一抗蚀剂掩模260，并且进行图案化以便覆盖半导体芯片19和20中的每一者的导体衬垫145和微型支柱150，但具有通向半导体19的下面的导体衬垫105的开口265和通向半导体芯片20的下面的导体衬垫120的开口270。
接下来并且如图13中所示，执行多个材料沉积步骤以沉积由液滴275示意表示的导体材料，以分别制造半导体芯片19和20的导电支柱100和115。可以通过现在还参看图14来理解这些材料制造过程的额外细节，图14是以更大的放大倍率示出的由虚线矩形280圈出的图13的部分。如图14中所示，在施加抗蚀剂掩模260并且在其中图案化开口270之前，在图10中描绘的抗蚀剂掩模235之前沉积的前述UBM结构160仍然在原位。此处，可以使用众所周知的镀敷技术来制造导电支柱115，所述镀敷技术可以包括将UBM结构160用作镀敷电极的偏置镀敷过程。可以使用铜、铜和银、铜和锡或其他类型的材料。在镀敷导电支柱115之后，通过镀敷或可替代地通过模板和焊膏过程在支柱115上制造焊料盖帽285。应注意，UBM结构160如何定位在导体衬垫120上并且与所述导体衬垫欧姆接触，以及UBM结构160与导电支柱115的下段的组合如何垂直地延伸穿过半导体芯片20上的钝化结构135和聚合物层50的一部分。
现在将结合图15和图16来描述将互连芯片85安装到半导体芯片19和20。如图15中示出，使用众所周知的抛光和溶剂剥离技术来剥离在图13和图14中描绘的抗蚀剂掩模260，从而留下分别从半导体芯片19和20向上突出的导电支柱100和115。在安装互连芯片85之前，半导体芯片19和20与模制层35的组合可以经历材料移除过程，例如湿蚀刻，以移除定位在聚合物层50上但横向于支柱100和115的UBM结构150的多余部分。此蚀刻是必需的，以防止相邻支柱100和115之间的后续的电短接等。此时，使用各种众所周知的技术来制造互连芯片85，以不仅确立内部导电迹线90，而且确立与互连芯片85相关联的导电路径95的那个部分并且如图3中描绘。举例来说，图16描绘图15的部分，并且具体来说，以更大的放大倍率描绘由虚线正方形290圈出的互连芯片85的小部分。如上文描述，在图3中示出的导电路径95的与互连芯片85相关联的那个部分由以下各者组成：导体衬垫165、钝化结构166、种子层167以及各个层170、175和180和紧随其后的焊料盖帽185，其全部被描绘成从图3中反映的定向翻转过来。应注意，当将互连芯片85定位在聚合物层50上时，执行回流以便确立焊料盖帽185与定位在半导体芯片19和20的微型支柱150上的下面的镍金盖帽155之间的金相结合。
接下来并且如图17中示出，执行第二模制过程以在互连芯片85、导电支柱100和115以及聚合物层50的另外暴露的部分上形成模制层30。在约165℃下使用约60分钟到120分钟的压缩模制过程以及本文公开的Sumitomo EME-G750或G760或其他模制材料来制造模制层30。需要暴露导电支柱100和115，使得模制层30经受如图18中示出的研磨过程。此研磨过程被设计成暴露导电支柱100和115，并且依据互连芯片85的高度，还可以使互连芯片85的后侧变薄。在如图19中示出的所暴露的支柱100和115的情况下，在支柱100上制造焊料互连件110，在支柱115上制造焊料互连件125。可以通过众所周知的焊料镀敷和/或焊膏模板过程或其他技术通过对焊料凸块的拾取和放置布置来形成焊料互连件110和125。
接下来并且如图20中所示，现在可以将完成的模制芯片组合13从在图19中示出的定向翻转过来，并且通过焊料互连件110和125的回流过程安装到电路板15。其后，通过分配底填作为液体和毛细管作用来确立底填140。
出于热管理目的，可以将任选的散热器或散热片300安装在模制芯片组合13上并且放置成分别与如图21中示出的半导体芯片19和20热接触。合适的热界面材料，例如散热膏或热胶(未示出)，可以分别定位在散热器300与半导体芯片19和20的上表面55和60之间。
图22是类似于图2的截面图，但是替代性示例性半导体芯片装置10'的截面图。半导体芯片装置10'与在本文在其他地方描绘和描述的半导体芯片装置10共享大多数的属性。主要区别在于，半导体芯片装置10利用了如图2中所示的底填材料层140，而半导体芯片装置10'消除了底填材料层140以便增加替代性模制芯片组合13'的模制层30的总高度。如早先描述的布置来使用模制层35和聚合物层50。然而，如图22中所示，模制层30并非终止于导电支柱110和115的下端附近或所述下端处，而是向下延伸并模制到电路板15，而且还向上延伸以至少部分地囊封芯片19和20、模制材料35和聚合物层50的组合。在这里还使用了本文在其他地方描述的用于使用模制层35以及半导体芯片19的PHY区65和非PHY区70里面和周围的各种导体结构的构造来模制半导体芯片19和20的制造步骤。半导体芯片20的PHY区75和非PHY区80将是重复的，或者与本文在其他地方针对半导体芯片装置10描述的相同。类似地，将如本文在其他地方针对半导体芯片装置10大体上描述那般来构造互连芯片85。然而，在用于半导体芯片装置10和半导体芯片装置10'的制造过程之间存在一些过程流差异，现在将起初结合图23进行描述。图23描绘在制造了聚合物层50并且安装了互连芯片85之后的半导体芯片19和20与模制层35的模制组合。另外，已经使用上文描述的导致图15中的描绘的技术来制造和暴露了导电支柱100和115。然而，在此阶段，分别将焊料互连件110和125安装在导电支柱100和115上。这可以使用滴定过程来完成，所述滴定过程实质上是拾取和放置过程。还可以有可能定位模板(未示出)以便放置焊料互连件110和125。此时可以完成短暂回流以便确立焊料互连件110与导电支柱100之间以及焊料互连件125与导电支柱115之间的初始金相结合。接下来并且如图24中所示，可以将半导体芯片19和20和模制层35以及互连芯片85一起从在图23中示出的定向翻转过来并且安装到电路板15。这需要回流过程来确立焊料互连件110和125与电路板15的导电衬垫(未示出)之间的金相连接。接下来，可以使用转移模制或其他技术将模制材料30模制在聚合物层50与电路板15之间以确立在图22中示出为完成形式的模制层30。这确立完成的模制芯片组合13'。如图25中所示，可以将任选的散热器300安装在如上文描述的模制芯片组合13'上。应注意，在需要时，用于模制层30的模制过程可以可替代地使模制层30的横向边缘与模制层35和聚合物层50的横向边缘具有共同边界。同样，热界面材料(未示出)可以定位在散热片300与半导体芯片19和20之间。
在前述公开的布置中，半导体芯片19和20的PHY区65和75中的导体衬垫更多并且具有比非PHY区70和80的具有横向尺寸x2的导体衬垫略微更小的尺寸x1。然而，可以将半导体芯片19和20制造成所有导体衬垫具有单个横向尺寸x1，即，用于PHY区65和75以及非PHY区70和80两者的导体衬垫都具有单个横向尺寸。然而，这意味着技术复杂性，原因在于需要能够使用更大的导电支柱，例如支柱100和115，即使装置70和80的非PHY区具有更小的横向尺寸x1大小衬垫也如此。将结合图26、图27、图28、图29、图30、图31、图32、图33、图34和图35并且起初参考图26来说明和描述此问题的技术解决方案。图26是半导体芯片20以及其PHY区75的一部分和非PHY区80的一部分的截面图。此处，PHY区75包括已经如本文在其他地方大体上描述那般制造的具有某一横向尺寸x1的多个导体衬垫120。然而，替代本文在其他地方描绘的具有横向尺寸x2的更大的导体衬垫120，非PHY区80替代地具有横向尺寸为x1的额外的多个导体衬垫145。这可能在以下情况下出现：使用不需要构造和图案化具有两种单独的横向尺寸的顶部水平导体衬垫的过程来制造半导体芯片20。已经施加钝化结构135并且将其图案化成具有至PHY区75和非PHY区80两者中的所有导体衬垫145的多个开口225。图27示出钝化结构135、开口225以及一些下面的导体衬垫145的顶视图。应理解，仅描绘数个导体衬垫145，并且半导体芯片可以依据其复杂性而包括数百或数千个此类衬垫。图27中以及图中其他地方的虚线308表示PHY区75与非PHY区80之间的边界。两个虚线圆310表示将在那里形成既定与下面的导体衬垫145欧姆接触的稍后形成的导电支柱115的位置。应注意，将形成与PHY区75中的导体衬垫145进行欧姆接触的更小的微型支柱150。技术目标是能够在虚线圆310的位置处最终制造与下面的尺寸过小的导体衬垫145欧姆接触的较大的导电支柱115。起初并且如图28中所示，将聚合物层50施加到PHY区75和非PHY区80上的半导体芯片20的钝化结构135并且填充开口225。聚合物层50优选地包括光敏化合物。如图29中所示，将抗蚀剂掩模320施加到聚合物层50并且图案化成具有与PHY区75上的钝化结构135中的那些开口225对准的合适的开口322，以及与钝化结构135中的非PHY区80上的那些开口225对准的其他合适的开口323。分别在图30和图31中示出开口322和323的平面图和示图。应注意，开口322和开口323具有不同的占用面积。开口322具有与PHY区75中的下面的开口225相同的占用面积。然而，开口323由克里斯交叉连接部分340与开口345的组合组成，其中开口345与非PHY区80中的下面的开口225对准。在掩模320在原位并且被图案化的情况下，暴露并显影聚合物层50，并且如图32中的平面图中所示剥离掩模320，以产生PHY区75中的具有掩模开口322的占用面积(参见图31)的开口347，以及具有掩模开口323的占用面积(参见图31)的克里斯交叉连接部分350的开口349和非PHY区80中的开口352。现在暴露PHY区75和非PHY区80两者中的下面的导体衬垫145。
接下来并且如图33中描绘的分解示图中所示，将另一抗蚀剂掩模330施加到聚合物层50并且进行图案化以提供PHY区75上的与聚合物层50中的开口347对准的适当的开口354，和非PHY区80上的与钝化结构135中的开口349对准的另一组开口356。开口354具有与聚合物层50中的开口347相同的占用面积，并且开口356具有与聚合物层50中的开口349相同的占用面积。在掩模330在原位的情况下，使用镀敷和本文在其他地方描述的材料在开口347中制造分立的导电支柱150，并且在开口349中制造互连的导电支柱150'。导电支柱150和导电支柱150'将具有相同的金相组成，但具有不同的占用面积。导电支柱150'由支柱358组成，所述支柱358向下延伸穿过聚合物层50到达通过导体条359互连的下面的导体衬垫145(不可见)。应理解，通过后续的处理，将在非PHY区80中的导电支柱150'的顶部上制造更大直径的导电支柱370(呈虚线)。最终使用本文在其他地方描述的技术来剥离镀敷掩模330以留下导电支柱150和导电支柱150'。与导体条359一样，还可以通过此方式制造导体迹线(未示出)，使得聚合物层50实现再分配层迹线的制造。PHY区75中的导电支柱150的基本构造是在图11中针对导电支柱150描绘的相同的一般构造。虽然导电支柱150'还将具有相同的层，但其占用面积将不同于如图33中所示的导电支柱150。
接下来并且如图34中所示，在聚合物层50上制造镀敷掩模360，并且将所述镀敷掩模图案化成具有合适的开口365，所述开口被定位且大小被设计成与在图27中描绘的虚线圆310的大小和位置相对应。目的是实现后续的镀敷过程以确立与下面的互连的导电支柱150'欧姆接触的导电支柱370，所述互连的导电支柱由在图33中示出的互连的支柱358和条359组成。图35示出非PHY区80上的镀敷掩模360和镀敷的导电支柱370的顶视图。应注意，下面的分立的导电支柱150被镀敷掩模460遮蔽(且因此以虚线示出)，并且互连的导电支柱150被导电支柱370和镀敷掩模360的一部分两者遮蔽，并且导电支柱150类似地被遮蔽且因此以虚线示出。最终使用众所周知的技术剥离镀敷掩模360。
熟练技术人员将了解，可以将本文描述的模制芯片13制造成单个单元，或者一同制造成相当于晶片级过程的晶片状结构(重建晶片)380。举例来说，并且如作为示图的图36中所示，可以使用(例如)模制层35和30同时大量地一起模制多个模制芯片组合13，并且在需要时可以在此晶片级阶段将互连芯片85安装在模制芯片组合13上。其后，可以将模制芯片组合13单体化成在本文的其他图中描绘的单独的单元。
虽然本发明可能会有各种修改和替代形式，但已经通过附图中的示例示出特定实施例，并且已经在本文详细描述了所述特定实施例。然而，应理解，本发明无意受限于所公开的特定形式。而是，本发明将涵盖落入由所附权利要求界定的本发明的精神和范围内的所有修改、等效物和替代方案。

Claims (15)

1.一种模制芯片组合，所述模制芯片组合包括：
第一半导体芯片，所述第一半导体芯片具有第一物理装置区和第一非物理装置区，所述第一物理装置区具有第一组导体衬垫，所述第一组导体衬垫中的每个导体衬垫具有第一横向尺寸，并且所述第一非物理装置区具有第二组导体衬垫，所述第二组导体衬垫中的每个导体衬垫具有与所述第一组导体衬垫基本上相同的所述第一横向尺寸；
第二半导体芯片，所述第二半导体芯片具有第二物理装置区；
互连芯片，所述互连芯片将所述第一物理装置区互连到所述第二物理装置区；
第一模制层，所述第一模制层将所述第一半导体芯片和所述第二半导体芯片横向地接合在一起；
第二模制层，所述第二模制层至少部分地囊封所述互连芯片；以及
聚合物层，所述聚合物层定位在所述第一模制层与所述第二模制层之间，其中，所述聚合物层具有与所述第一组导体衬垫对准的多个开口和与所述第二组导体衬垫对准的多个互连开口，所述聚合物层具有所述开口中的每一者中的导电支柱和所述互连开口中的每一者中的互连的导电支柱，所述第一非物理装置区包括所述互连的导电支柱上的另一导电支柱，所述另一导电支柱具有大于所述第一横向尺寸的第二横向尺寸。
2.如权利要求1所述的模制芯片组合，其中所述第一半导体芯片包括用于在将所述模制芯片组合安装在电路板上时连接到所述电路板的第一多个互连件，并且所述第二半导体芯片包括用于在将所述模制芯片组合安装在所述电路板上时连接到所述电路板的第二多个互连件。
3.如权利要求2所述的模制芯片组合，其中所述第一半导体芯片包括连接到所述第一互连件的第一非物理装置区，并且所述第二半导体芯片包括连接到所述第二互连件的第二非物理装置区。
4.如权利要求1所述的模制芯片组合，所述模制芯片组合包括电路板，其中所述模制芯片组合安装在所述电路板上。
5.如权利要求1所述的模制芯片组合，其中所述第一半导体芯片包括处理器并且所述第二半导体芯片包括存储器芯片。
6.一种模制芯片组合，所述模制芯片组合包括：
第一半导体芯片，所述第一半导体芯片具有第一物理装置区和第一非物理装置区，其中所述第一半导体芯片物理装置区包括第一组导体衬垫，所述第一组导体衬垫中的每个导体衬垫具有第一横向尺寸，并且所述第一半导体芯片非物理装置区包括第二组导体衬垫，所述第二组导体衬垫中的每个导体衬垫具有与所述第一组导体衬垫基本上相同的所述第一横向尺寸；
第二半导体芯片，所述第二半导体芯片具有第二物理装置区和第二非物理装置区；
互连芯片，所述互连芯片将所述第一物理装置区互连到所述第二物理装置区；
第一模制层，所述第一模制层将所述第一半导体芯片和所述第二半导体芯片横向地接合在一起；
第二模制层，所述第二模制层接合到所述第一模制层并且至少部分地囊封所述互连芯片和所述第一模制层；以及
聚合物层，所述聚合物层定位在所述第一模制层与所述第二模制层之间，其中，所述聚合物层具有与所述第一组导体衬垫对准的多个开口和与所述第二组导体衬垫对准的多个互连开口，所述聚合物层具有所述开口中的每一者中的导电支柱和所述互连开口中的每一者中的互连的导电支柱，所述非物理装置区包括所述互连的导电支柱上的另一导电支柱，所述另一导电支柱具有大于所述第一横向尺寸的第二横向尺寸。
7.如权利要求6所述的模制芯片组合，其中所述第一半导体芯片包括用于在将所述模制芯片组合安装在电路板上时连接到所述电路板的第一多个互连件，并且所述第二半导体芯片包括用于在将所述模制芯片组合安装在所述电路板上时连接到所述电路板的第二多个互连件。
8.如权利要求7所述的模制芯片组合，其中所述第一半导体芯片第一非物理装置区连接到所述第一互连件，并且所述第二半导体芯片第二非物理装置区连接到所述第二互连件。
9.如权利要求6所述的模制芯片组合，所述模制芯片组合包括电路板，其中所述模制芯片组合安装在所述电路板上。
10.如权利要求6所述的模制芯片组合，其中所述第一半导体芯片包括处理器并且所述第二半导体芯片包括存储器芯片。
11.一种制造模制芯片组合的方法，所述方法包括：
使用互连芯片将第一半导体芯片的第一物理装置区互连到第二半导体芯片的第二物理装置区，其中所述第一物理装置区包括第一组导体衬垫，所述第一组导体衬垫中的每个导体衬垫具有第一横向尺寸，并且所述第一半导体芯片包括第一非物理装置区，所述第一非物理装置区包括第二组导体衬垫，所述第二组导体衬垫中的每个导体衬垫具有与所述第一组导体衬垫基本上相同的所述第一横向尺寸；
使用第一模制层将所述第一半导体芯片和所述第二半导体芯片模制在一起；
使用第二模制层至少部分地囊封所述互连芯片；以及
在所述第一模制层与所述第二模制层之间施加聚合物层，所述聚合物层具有与所述第一组导体衬垫对准的多个开口和与所述第二组导体衬垫对准的多个互连开口，所述聚合物层具有所述开口中的每一者中的导电支柱和所述互连开口中的每一者中的互连的导电支柱，所述第一非物理装置区包括所述互连的导电支柱上的另一导电支柱，所述另一导电支柱具有大于所述第一横向尺寸的第二横向尺寸。
12.如权利要求11所述的方法，所述方法包括制造所述第一半导体芯片上的用于在将所述模制芯片组合安装在电路板上时连接到所述电路板的第一多个互连件，和所述第二半导体芯片上的用于在将所述模制芯片组合安装在所述电路板上时连接到所述电路板的第二多个互连件。
13.如权利要求12所述的方法，其中所述第一非物理装置区连接到所述第一互连件，并且所述第二半导体芯片包括连接到所述第二互连件的第二非物理装置区。
14.如权利要求11所述的方法，所述方法包括将所述模制芯片组合安装在电路板上。
15.如权利要求11所述的方法，其中所述第一半导体芯片包括处理器并且所述第二半导体芯片包括存储器芯片。
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