TWI594397B - 具改良互連帶寬之堆疊半導體裝置封裝體 - Google Patents
具改良互連帶寬之堆疊半導體裝置封裝體 Download PDFInfo
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- TWI594397B TWI594397B TW104138262A TW104138262A TWI594397B TW I594397 B TWI594397 B TW I594397B TW 104138262 A TW104138262 A TW 104138262A TW 104138262 A TW104138262 A TW 104138262A TW I594397 B TWI594397 B TW I594397B
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Description
本揭示之實施例一般關於用於半導體裝置之封裝領域,並且尤其是,關於具改良互連帶寬之一堆疊半導體裝置封裝體。
具有用於可穿戴式和活動式應用之降低形式係數(平面和z-方向)、較低功率、以及較低成本的半導體裝置封裝體引發多種挑戰性。例如,於封裝體堆疊上之3D晶片堆疊和封裝體是用以降低平面(x,y-方向)形式係數之一般解決辦法。但是,這些堆疊方法可能導致對於產品設計之z-方向挑戰性。如另一範例,降低的功率消耗可以藉由相對於使用標準記憶體方法而被組配如一頂部封裝體的寬廣輸入-輸出記憶體而被得到。這堆疊方法通常在頂部和底部封裝體之間需要高互連帶寬。實現該帶寬可以使用用於晶粒堆疊方法之直通矽晶穿孔(TSV)或用於封裝方法上之封裝體的直通鑄模穿孔(TMV)和通孔柱而達成。但是,TSV通常是昂貴的,並且一扇出區域中之TMV和通孔柱通常是
受限定於互連帶寬。因此,對於堆疊半導體封裝之方法降低成本、z-高度、功率消耗、以及平面足跡,而維持可用以連接至一印刷電路板(PCB)的一高數量之互連可能是所需的。
依據本發明之一實施例,係特地提出一種堆疊半導體裝置封裝體,其包含:一基體,其具有一第一側與相對於該第一側之一第二側,其中該第一側具有複數個墊片並且該第二側具有包括於一第二側扇出區域中之墊片的複數個墊片,其中該基體具有電氣路由特點被組配用以電氣地耦合在該第一側上之該等複數個墊片的墊片與包括該第二側扇出區域之該等墊片的該第二側上之該等複數個墊片的墊片;一第一半導體裝置,其具有一第一裝置墊片側與該基體之該第一側上之該等複數個墊片的一墊片耦合;一第二半導體裝置,其具有一第二裝置墊片側與該基體之該第二側上之該等複數個墊片一墊片耦合,該第一半導體裝置和該第二半導體裝置是藉由該等電氣路由特點經由該基體而電氣地耦合在一起;以及一介電質層,其具有一第一側與該基體之該第二側耦合並且包覆該第二半導體裝置,其中該介電質層具有複數個導電通孔電氣地與該第二側扇出區域中之該等墊片耦合並且經組配用以在該介電質層的該第一側與該介電質層的一第二側之間安排該第一半導體裝置和該第二半導體裝置之電氣信號路由,該介電質層之該
第二側相對於該介電質層之該第一側。
100‧‧‧封裝體
102‧‧‧基體
102a‧‧‧基體第一側
102b‧‧‧基體第二側
102c‧‧‧電氣路由特點
102d、102g‧‧‧扇出區域
102e‧‧‧電氣連接點
102f‧‧‧電氣連接點
104‧‧‧第一半導體裝置
104a‧‧‧底部填膠材料側
104c‧‧‧晶粒不主動側/第二側
104d‧‧‧晶粒
104d.1、106d.1‧‧‧半導體基體
104d.2、106d.2‧‧‧裝置層
104d.3、106d.3‧‧‧互連層
104e‧‧‧鑄模複合物
104f‧‧‧第一半導體裝置第一側
104g‧‧‧底部填膠材料
104h‧‧‧晶粒-層級互連結構
106‧‧‧第二半導體裝置
106a‧‧‧基體與填膠材料接觸點
106c‧‧‧第二半導體裝置第二側
106d‧‧‧晶粒
106f‧‧‧第二半導體裝置第一側
106g‧‧‧底部填膠材料
106h‧‧‧晶粒-層級互連結構
108‧‧‧介電質層
108a‧‧‧介電質層第一側
108b‧‧‧介電質層第二側
108c‧‧‧電氣路由特點
200‧‧‧積體電路(IC)組件
202‧‧‧重新分配層
202a‧‧‧電氣信號佈線層
202b‧‧‧介電質層
204‧‧‧互連結構
206‧‧‧電路板
300‧‧‧第三半導體裝置封裝體
302‧‧‧第三半導體裝置
302a‧‧‧覆晶晶粒
302b‧‧‧主動表面
302c‧‧‧晶粒層級互連結構
400‧‧‧封裝體
402‧‧‧第四半導體裝置
404‧‧‧通孔
404a‧‧‧互連
406‧‧‧基體
408‧‧‧覆晶晶粒
410‧‧‧互連
412‧‧‧鑄模複合物
500‧‧‧第一封裝體裝置
502‧‧‧基體
504‧‧‧晶圓層級晶片尺度封裝體
504a‧‧‧晶粒
600‧‧‧堆疊半導體裝置封裝體製造方法
602-610‧‧‧堆疊半導體裝置封裝體製造步驟
700‧‧‧堆疊半導體裝置封裝體
702-710‧‧‧封裝體結構
720‧‧‧第一半導體裝置
722‧‧‧基體
724‧‧‧介電質層
724a、724b‧‧‧介電質層
726‧‧‧第二半導體裝置
728‧‧‧導電層
730‧‧‧附加的半導體裝置
732‧‧‧半導體裝置
734‧‧‧通孔
800‧‧‧計算裝置
802‧‧‧主機板
804‧‧‧處理器
806‧‧‧通訊晶片
808‧‧‧外殼
810‧‧‧攝影機
812‧‧‧晶片組
824‧‧‧放大器
820‧‧‧GPS
826‧‧‧圖形CPU
828‧‧‧觸控屏幕控制器
830‧‧‧控制器
832‧‧‧天線
834‧‧‧揚聲器
836‧‧‧觸控屏幕顯示器
838‧‧‧麥克風
840‧‧‧插口
842‧‧‧感測器
844‧‧‧電池/充電系統
實施例將藉由配合附圖之下面的詳細說明而容易地被了解。為了便利這說明,相同的參考號碼標明相同的結構元件。實施例藉由範例被例示並且不是作為對附圖之圖形的限制。
圖1圖解地例示,依據一些實施例之一堆疊半導體裝置封裝體範例之一截面側視圖。
圖2圖解地例示,依據一些實施例作為一積體電路(IC)組件之一堆疊半導體裝置封裝體範例的截面側視圖。
圖3圖解地例示,依據一些實施例而具有一第三半導體裝置之一堆疊半導體裝置封裝體範例的一截面側視圖。
圖4圖解地例示,依據一些實施例而具有一附加覆晶晶粒以及藉由通孔所連接的封裝體上之一堆疊封裝體的一堆疊半導體裝置封裝體範例之一截面側視圖。
圖5圖解地例示,依據一些實施例而具有如一第一封裝體裝置之一晶圓層級晶片尺度封裝體的一堆疊半導體裝置封裝體範例之一截面側視圖。
圖6圖解地例示,依據一些實施例而製造一堆疊半導體裝置封裝體之一方法。
圖7圖解地例示,依據一些實施例在各種製造階段期間一堆疊半導體裝置封裝體之一截面側視圖。
圖8圖解地例示,依據一些實施例而包括如此處所說明之一堆疊半導體裝置封裝體的一計算裝置。
本揭示實施例說明一堆疊半導體裝置封裝體以及相關聯的技術和組配。在下面的說明中,例示之實行例的各種論點藉由通常為那些熟習本技術者所採用的使用字詞而說明以傳達他們的工作要義至其他熟習本技術者。但是,那些熟習本技術者應明白,本揭示實施例可以僅藉由上述一些論點而實施。為了說明之目的,特定數量、材料、以及組配被提出,以便提供對於所例示的實行例之整體了解。但是,一熟習本技術者應明白,本揭示實施例不需特定細節而可以被實施。於其他實例中,為了不混淆所例示的實行例,因而習知的特點被省略或被簡化。
在下面的詳細的說明中,參考至形成其之一部份的附圖,其全文中相同於號碼標明相同部件,並且其中經由例示實施例所展示之本揭示主題標的可以被實施。應了解其他實施例可以被採用並且可以有結構或邏輯之改變而不脫離本揭示範疇。因此,該下面的詳細說明不是作為受限定之意,並且實施例範疇是藉由附加申請專利範圍以及它們的等效者所界定。
為本揭示之目的,詞語“A及/或B”表示(A)、(B)、或(A和B)。為本揭示之目的,詞語“A、B、及/或C”表示(A)、(B)、(C)、(A和B)、(A和C)、(B和C)、或(A、
B、以及C)。
本說明可能使用透視角度來說明,例如,頂部/底部、入/出、上/下、以及其類似者。這些說明僅是使用以便利於討論並且不欲限制此處所說明之實施例應用於任何特定方位。
本說明可能使用詞語“於一實施例中”或“於多個實施例中”,其各可以是涉及一個或多個相同或不同實施例。此外,詞語“包括”、“包含”、“具有”、以及其類似者,如相關於本揭示實施例之使用,是同義的。
詞語“耦合於”,與其之衍生詞,可以在此處一起使用。“耦合”可以表示一個或多個下面所述者。“耦合”可以表示二個或更多的元件是以直接實際或電氣方式接觸。但是,“耦合”也可以表示二個或更多的元件彼此非直接地接觸,但是仍然可以彼此配合或互動,並且可以表示一個或多個其他元件係耦合或連接在可以說是彼此耦合的元件之間。
在各種實施例中,詞語“一第一特點係形成、係放置、或此外係配置在一第二特點上”可以表示,該第一特點係形成、係放置、或係配置在第二特點之上,並且第一特點之至少一部份可以是與第二特點之至少一部份直接地接觸(例如,直接實際及/或電氣接觸)或非直接接觸(例如,有一個或多個其他特點在第一特點和第二特點之間)。
如此處所使用,詞語“模組”可以是涉及下列構
件之部件,或包含下列構件:如一特定應用積體電路(ASIC)、一電子電路、一系統單晶片(SoC)、一處理器(共用、專用、或群組)、一MEMS裝置、一整合被動裝置,及/或執行一個或多個軟體或韌體程式之記憶體(共用、專用、或群組)、一組合邏輯電路、及/或提供上述功能之其他適當構件。
圖1圖解地例示,依據一些實施例之一堆疊半導體裝置封裝體(封裝體)100範例之一截面側視圖。於一些實施例中,該封裝體100可以包括一基體102,其電氣地及/或實體地耦合於基體102之一第一側102a上之一第一半導體裝置104之一第一側104f以及於該基體102之一第二側102b上之一第二半導體裝置106之一第一側106f。該第一側102a和該第二側102b可以是在該基體102之相對側上。一介電質層108之第一側108a可以被耦合至基體102之第二側102b並且包覆該第二半導體裝置106。該介電質層108可以是接觸於第二半導體裝置106之一第二側106c。該介電質層可以具有電氣路由特點108c用以自該介電質層108之第一側108a安排電氣信號路由至該介電質層之一第二側108b並且可以被使用以在該第一半導體裝置104、該第二半導體裝置106、以及介電質層108第二側108b之間安排電氣信號路由。
於一些實施例中,基體102可以包含一多層半導體複合基體,其具有一核心、一薄核心、或沒有核心(無核心基體)、或用於封裝半導體裝置之任何適當基體。於
一些實施例中,適用於覆晶封裝體之任何基體型式可以被使用於該基體102。於一些實施例中,該基體102具有1.5和以上的層之一多層基體。於一些實施例中,該基體102可以藉由任何工業標準方法所製造,其包括,而不受限定於序列組裝和Z-堆疊方法。
基體102可以具有第一表面102a上之電氣路由特點102c以及第二表面102b上之電氣連接點102e和電氣連接點102f。該基體可以具有第二表面102b上之一扇出區域102g並且可以具有第一表面102a上之一扇出區域102d。基體102之電氣路由特點102c可以提供在第一半導體裝置104、第二半導體裝置106、以及包括扇出區域102d和102g的該等連接點102e、102f之間的電氣通訊。電氣連接點102e和102f可以是凸塊、墊片、柱狀物、以及用以連接半導體裝置至一基體之任何其他適當的連接器,包括前述之組合。該介電質層108之該等電氣路由特點108c可以是接觸於基體102扇出區域102g之該等電氣連接點102f。於一些實施例中,該基體102可以包括具有整合構件之一多層封裝體組件,其包括而不限定於無線通訊。例如,該基體102可以包括電氣路由特點(未展示於圖1中),例如,跡線、墊片、穿孔、通孔、或被組配以安排電氣信號路由至或自耦合於基體102之半導體裝置的線路。
第一半導體裝置104可以包含一晶粒104d,其可以被鑄模複合物104e、或一相似型式之複合物所包覆。晶粒104d可以代表一離散產品,其是使用半導體製造技術
(例如,薄膜沈積、平版印刷術、蝕刻、以及配合形成互補金屬氧化物-半導體(CMOS)裝置所使用之相同技術)而由一半導體材料(例如,矽)所構成。於一些實施例中,該晶粒104d可以是一射頻(RF)晶粒,包括一射頻(RF)晶粒,或是其之一部份。於其他實施例中,該晶粒可以是,包括,一處理器、記憶體、晶片上系統(SoC)、或特定應用積體電路(ASIC),或是其之一部份。
於一些實施例中,一底部填膠材料104g(有時被稱為一“密封劑”)可以被配置在晶粒104d和基體102之間以增進附著力及/或保護晶粒104d和基體102之特點。底部填膠材料104g可以是由一電氣地絕緣材料所組成並且如所見地,可以包覆至少一部份的晶粒104d及/或晶粒-層級互連結構104h。於一些實施例中,底部填膠材料104g是與晶粒-層級互連結構104h直接地接觸。於一些實施例中,底部填膠材料104g具有一側104a,其是直接地接觸於第一表面102a上之基體102。
晶粒104d可以依據多種適當的組配而附接至基體102,例如,如所展示地,包括以一覆晶組配方式而直接地被耦合於基體102。以該覆晶組配方式,一第一側104f是晶粒104d之一主動側並且包括主動電路(未展示)。該第一側104f是使用晶粒-層級互連結構104h,例如,凸塊、柱狀物、或可以電氣地耦合晶粒104d與基體102之其他適當的結構,被附接至基體102之表面102a。適當的結構包括,而不限定於,微銲接球、銅柱狀物、導電膠合
劑、和非導電膠合劑、以及其組合。於一些實施例中,回流可以被進行以構成隨著毛細管底部填膠或鑄模底部填膠之連接。熱壓縮結合或熱聲波結合可以被使用於一些實施例中。如所見地,晶粒104d之第一側104f可以包括電晶體裝置,以及一非主動側/第二側104c可以被配置而相對至第一側/主動側104f。
晶粒104d通常可以包括一半導體基體104d.1,一個或多個裝置層(此後稱為“裝置層104d.2”),以及一個或多個互連層(此後稱為“互連層104d.3”)。於一些實施例中,該半導體基體104d.1實質上可以是,例如,由一主體半導體材料所組成,例如,矽。裝置層104d.2可以代表一區域,其中主動裝置,例如,電晶體裝置被形成於該半導體基體104d.1上。裝置層104d.2可以,例如,包括結構,例如,通道本體及/或電晶體裝置之源極/汲極區域。互連層104d.3可以包括互連結構,其被組配以安排電氣信號路由至或自裝置層104d.2中之主動裝置。例如,該互連層104d.3可以包括溝槽及/或通孔以提供電氣路由及/或接觸。
於一些實施例中,晶粒-層級互連結構104h可以被組配以在晶粒104d和其他電氣裝置之間安排電氣信號路由。該等電氣信號可以包括,例如,配合晶粒104d之操作所使用的輸入/輸出(I/O)信號及/或電力/接地信號。
第二半導體裝置106可以包含一晶粒106d。該晶粒106d可以代表一離散產品,其是使用半導體製造技術
(例如,薄膜沈積、平版印刷術、蝕刻、以及相同於配合形成CMOS裝置所使用之技術者)由一半導體材料所構成。於一些實施例中,該晶粒104d可以是一RF晶粒,包括一RF晶粒,或是其之一部份。於其他實施例中,該晶粒可以是,或包括,一處理器、記憶體、SoC、MEMS、IPD、或ASIC,或是其之一部份。
於一些實施例中,一底部填膠材料106g可以被配置在晶粒106d和基體102之間以增進附著力及/或保護晶粒106d和基體102之特點。該底部填膠材料106g可以是由一電氣地絕緣材料所組成並且可以如所見地,包覆至少一部份的晶粒106d及/或晶粒-層級互連結構106h。於一些實施例中,該底部填膠材料106g是直接地接觸於晶粒-層級互連結構106h。於一些實施例中,該底部填膠材料106g是藉由第二表面102b上之基體102而直接地接觸106a。
如所展示地,晶粒106d可以依據多種適當的組配而被附接至基體102,例如,包括直接地以一覆晶組配方式而耦合於基體102。以該覆晶組配方式,一第一側106f是晶粒106d之一主動側並且包括主動電路。該第一側106f使用晶粒-層級互連結構106h,例如,凸塊、柱狀物、或可以電氣地耦合晶粒106d與基體102之其他適當的結構,被附接至基體102之表面102b。適當的結構包括,但不限定於,微銲接球、銅柱狀物、導電膠合劑、和非導電膠合劑、以及其組合。於一些實施例中,回流可以被進行以構成隨著毛細管底部填膠或鑄模底部填膠之連接。熱壓
縮結合或熱聲波結合可以被使用於一些實施例中。如所見地,晶粒106d之第一側106f可以包括電晶體裝置,並且一非主動側/第二側106c可以被配置而相對至第一側/主動側106f。
晶粒106d通常可以包括一半導體基體106d.1、一個或多個裝置層106d.2、以及一個或多個互連層106d.3。於一些實施例中,例如,該半導體基體106d.1實質上可以是由一主體半導體材料所製造,例如,矽。該裝置層106d.2可以代表主動裝置(例如,被形成於半導體基體106d.1上之電晶體裝置)之一區域。該裝置層106d.2可以,例如,包括結構,例如,通道本體及/或電晶體裝置之源極/汲極區域。該互連層106d.3可以包括互連結構,其被組配以安排電氣信號路由至或自裝置層106d.2中之主動裝置。例如,該互連層106d.3可以包括溝槽及/或通孔以提供電氣路由及/或接觸。
於一些實施例中,晶粒-層級互連結構106h可以被組配以在晶粒106d和其他電氣裝置之間安排電氣信號路由。該等電氣信號可以包括,例如,配合晶粒106d之操作所使用的輸入/輸出(I/O)信號及/或電力/接地信號。
於一些實施例中,第一半導體裝置104可以由具有如上述對於晶粒104d之相同或相似特點的二個或更多個晶粒所組成。於一些實施例中,第二半導體裝置106可以是由具有如上述對於晶粒106d之相同或相似特點的二個或更多個晶粒所組成。於一些實施例中,該等二個或更多個
晶粒被堆疊。於一些實施例中,該等二個或更多個晶粒是並排的。於一些實施例中,該等二個或更多個晶粒被堆疊並且是並排的。於一些實施例中,其中第二半導體裝置106是包含二個或更多個晶粒,介電質層108包覆該等二個或更多個晶粒。
於一些實施例中,第一半導體裝置104和第二半導體裝置106可以是一個或多個晶粒、封裝體、封裝體中系統、表面架設裝置(SMD)、整合主動裝置(IAD)、及/或整合被動裝置(IPD)。主動和被動裝置可以包括電容器、電感器、連接器、開關、中繼器、電晶體、運算放大器、二極體、震盪器、感應器、MEMS裝置、通訊和網路模組、記憶體模組、電力模組、介面模組、RF模組、及/或RFID模組。
於一些實施例中,第一半導體裝置104和基體102是具有一重新分配層之一晶圓層級晶片尺度封裝體(WLCSP)、具有一重新分配層之一扇出晶圓層級封裝體(FOWLP)、一嵌入式晶圓層級球形柵格陣列封裝體(eWLBGA)、或一晶圓層級扇出面板層級封裝體(WFOP)。
於一些實施例中,介電質層108是包含複數個介電質層。於一些實施例中,該介電質層108是包含介電質材料之一個或多個層壓層。於一些實施例中,該介電質層108是包含一個或多個塗層的塗層介電質材料。於一些實施例中,該介電質層108是鑄模。於一些實施例中,該介電質層108是下列材料之一個或多個層,如味之素
(Ajinomoto)建構薄膜(ABF)、耐燃劑FR4材料、耐燃劑FR2材料、樹脂塗層銅(RCC)膜、聚亞胺(PI)、聚對苯-6撑苯并二噁唑(poly-(p-phenylene-2,6-benzobisoxazole))(PBO)、雙苯環丁烯(bisbenzocyclobutene)(BCB)、被動薄膜、及鑄模複合物(液體、薄片、以及粉末)、以及其組合。於一些實施例中,被動薄膜是由JSR公司所製造之一WPR®薄膜。WPR是日本105-8640東京都港區東新橋一丁目之JSR公司的一註冊商標。於一些實施例中,該介電質層108以雷射鑽孔而產生開孔,其用以產生電氣路由特點108c。於一些實施例中,該等電氣路由特點108c藉由一金屬電鍍處理程序於該等開孔中被產生,其包括無電鍍及/或電鍍處理程序。
圖2圖解地例示,依據一些實施例如一積體電路(IC)組件200(IC組件200)之一堆疊半導體裝置封裝體範例的一截面側視圖。圖2之實施例可以與圖1之堆疊半導體裝置封裝體100的實施例一致而具有一重新分配層202、互連結構204、以及電路板206之加成。因此,在先前所提供用於圖1之堆疊半導體裝置封裝體100的構件、材料、以及方法之說明可以應用於圖2之IC組件200。
於一些實施例中,重新分配層202可以包含一電氣信號佈線層202a以及一介電質層202b。於一些實施例中,該重新分配層202可以包含電氣信號佈線層202a和介電質層202b之複數個交錯層。於一些實施例中,該介電質層202b是一銲料遮罩層。於一些實施例中,該等電氣信號
佈線層可以包含跡線、墊片、穿孔、通孔、或線路,其被組配以安排電氣信號路由至/自耦合於基體102和電路板206之半導體裝置。
於一些實施例中,電路板206可以是由一電氣地絕緣材料(例如,一環氧樹脂層壓)所製造之一印刷電路板(PCB)。例如,該電路板206可以包括電氣地絕緣層,例如,由下列材料所製造,例如,聚四氟乙烯、酚醛棉紙材料,例如,阻燃劑4(FR-4)、FR-1、棉紙、以及環氧樹脂材料,例如,CEM-1或CEM-3、或使用一環氧樹脂樹脂半固化片材料被層壓在一起之織物玻璃材料。互連結構(未展示),例如,跡線、溝槽或通孔可以通過電氣地絕緣層被形成以安排附接至基體102的半導體裝置104d和106d之電氣信號路由通過電路板206。於其他實施例中,電路板206可以是由其他適當的材料所製造。於一些實施例中,該電路板206是一主機板(例如,圖8之主機板802)。
於一些實施例中,互連結構204可以包含凸塊、柱狀物、及/或墊片。於一些實施例中,該等互連結構204可以包括銲接球。該等互連結構204可以耦合於基體102及/或電路板206以形成對應的銲料接合點,其被組配以進一步地在該基體102和該電路板206之間安排電氣信號路由。用以實體地及/或電氣地耦合該基體102與該電路板206之其他適當技術可以被使用於其他實施例中。
於其他實施例中,IC組件200可以包括多種其他適當的組配,例如,包括下列之適當的組合:覆晶及/或
接線黏合組配、中介板、多-晶片封裝體組配,包括封裝體中系統(SiP)及/或封裝體上封裝體(PoP)組配。在晶粒102和IC組件200的其他構件之間安排電氣信號路由的其他適當技術可以被使用於一些實施例中。
圖3圖解地例示,依據一些實施例具有一第三半導體裝置300(封裝體300)的一堆疊半導體裝置封裝體範例之一截面側視圖。圖3實施例可以是一致於圖2的IC組件200之實施例,為清楚起見,其具有一第三半導體裝置302的添加,但是移除基體206。因此,先前所提供用於圖1之堆疊半導體裝置封裝體100以及IC組件200的構件、材料、和方法之說明可以應用至圖3之封裝體300。
於一些實施例中,第三半導體裝置302可以是包含一覆晶晶粒302a,其具有藉由晶粒層級互連結構302c耦合至重新分配層202的主動表面302b,各如先前所述。於一些實施例中,該第三半導體裝置302包含二個或更多個半導體裝置。於一些實施例中,該第三半導體裝置302是包含一個或多個晶粒、封裝體、封裝體中系統,表面架設裝置(SMD)、整合主動裝置(IAD)、及/或整合被動裝置(IPD)。於一些實施例中,該第三半導體裝置302可以是一WLCSP、WLP、或一裸晶粒。
圖4圖解地例示,依據一些實施例而具有一附加的覆晶晶粒的一堆疊半導體裝置封裝體範例以及藉由通孔400(封裝體400)所連接的封裝體上之一堆疊封裝體的一截面側視圖。圖4實施例可以是一致於圖3封裝體300之實施
例,其具有堆疊於第一半導體裝置104上之一第四半導體裝置402的添加。因此,先前所提供用於圖3封裝體300的構件、材料、和方法之說明可以應用於圖4封裝體400。於一些實施例中,圖4之封裝體400不具有第三半導體裝置302。
於一些實施例中,第四半導體裝置402使用耦合至基體102之扇出區域102d中的連接點102e之通孔404而被耦合至第一半導體裝置104。於一些實施例中,互連404a連接該等通孔404至第四半導體裝置402之一基體406。基體406之電氣路由特點未被例示於圖4中。於一些實施例中,第四半導體裝置402包含一基體406上之一覆晶晶粒408,其具有互連410和包覆晶粒408之鑄模複合物412。於一些實施例中,該第四半導體裝置是一WLCSP或一eWLBGA。於一些實施例中,該第四半導體裝置402藉由直通矽晶穿孔或直通鑄模穿孔或其一組合而被耦合至該第一半導體裝置104。於一些實施例中,該第四半導體裝置包含一個或多個晶粒、封裝體、封裝體中系統、SMD、IAD、及/或IPD。於一些實施例中,銲接球可以被使用以耦合裝置402。
圖5圖解地例示,依據一些實施例,具有如一第一封裝體裝置500(封裝體500)之一晶圓層級晶片尺度封裝體的一堆疊半導體裝置封裝體範例之一截面側視圖。圖5實施例可以一致於圖2的IC組件200之實施例,其有電路板206的移除以及以具有晶粒504a和基體502的一WLCSP 504
而取代半導體裝置104和基體102。因此,先前所提供而用於圖3的IC組件200之構件、材料、和方法的說明可以應用於圖5之封裝體500。
於一些實施例中,圖5之封裝體500使用晶圓層級處理程序被製造。於一些實施例中,第二半導體裝置106d使用晶圓層級處理被耦合至WLCSP 504之基體502。於一些實施例中,裝置106d藉由銲接球、平板微凸塊、墊片印刷上之銲料、或銅柱狀物或其他適當的耦合結構和方法而耦合至基體502。於一些實施例中,回流處理被使用以耦合裝置106d。於一些實施例中,介電質層,例如,使用晶圓層級處理而耦合至基體502,例如,PI塗層上自旋、被動薄膜、及/或PBO。
於一些實施例中,如於圖1-3所展示之第一半導體裝置104是一FOWLP。於一些實施例中,一RDL是在一人造晶圓或面板上,其具有嵌入式矽晶粒,隨後接著使用銲接球、平板微凸塊、墊片印刷上銲料、或銅柱狀物、或其他適當的耦合結構和方法附接一懸掛晶粒於RDL頂部上。於一些實施例中,回流處理被使用以耦合裝置106d。於一些實施例中,該介電質層,例如,使用晶圓層級處理而被耦合至基體102,例如,PI塗層上自旋、被動薄膜、及/或PBO。於一些實施例中,人造面板基體技術被使用,其中ABF之疊層或相似介電質薄膜被使用以耦合介電質層108至基體102。
圖6圖解地例示,依據一些實施例而製造一堆疊
半導體裝置封裝體之一方法600。該方法600可以被使用以形成圖1-5所例示之實施例而用以附接實施例至圖2中展示之電路板206。使用的參考號碼是圖1-5中所使用的那些號碼。
在602,該方法600可以包括提供一基體102、502,其具有耦合至一第一側102a、502a的一第一半導體裝置104、504以及耦合至基體102、502之第二/相對側102b、502b的一第二半導體裝置106。於一些實施例中,半導體裝置104、504和106可以被耦合於,例如,面向一覆晶組配中之基體的主動側。於一些實施例中,晶圓層級處理可以在602被使用,其包括,例如,WLCSP、eWLBGA、或FOWLP、或其類似者,其中矽晶粒可以是開始點並且接著RDL-層可以被添加且可以是基體。
在604,方法600可以包括形成一介電質層108於第二側102b、502b上,其中該介電質層包覆第二半導體裝置106。於一些實施例中,晶圓層級處理可以被使用以形成介電質層108。於一些實施例中,該介電質層可以藉由疊層或自旋塗層或其組合被形成。於一些實施例中,雷射鑽孔或另一適當的方法可以被使用以於該介電質層108中產生開孔以供製成導電通孔。於一些實施例中,該等導電通孔可以藉由無電鍍或電鍍處理、或其一組合被形成。
在608,方法600可以耦合一重新分配層(RDL)202至介電質層108。於一些實施例中,該RDL層202可以是包含一導電層和一介電質層之二層或更多層,並且
可以藉由疊層或塗層或其一組合被形成。於一些實施例中,堆疊半導體裝置封裝體可以耦合至一電路板206。
在610,方法600可以耦合一個或多個附加的半導體裝置302至RDL 202。於一些實施例中,一個或多個附加的半導體裝置402可以耦合至第一半導體裝置104。於一些實施例中,用以耦合至一電路板206之一耦合區域可以包括RDL 202的所有區域,其包括在第二半導體裝置106之下而不是在扇出區域102g中的區域。
圖7圖解地例示,依據一些實施例以及如藉由圖1-5中所展示之範例和圖6之方法所例示,在各種製造階段期間的一堆疊半導體裝置封裝體之一截面側視圖。圖7之結構可以具有如圖1-5中的那些者之相似參考記號,並且除了其中有所表明之外,否則是意欲代表相似結構。結構702對應至方法600之602。結構702展示耦合至一基體722之一第一半導體裝置720以及耦合至基體722之一第二半導體裝置726。結構704對應至方法600中之602。於結構704中,結構702可以具有耦合至基體722且包覆該第二半導體裝置726之一介電質層724。結構706對應至方法600中之606。於結構706中,該介電質層724可以具有導電通孔通過,以形成介電質層724b。結構708對應至方法600之608。於結構708中,包含至少一導電層728和一介電質層724a之一重新分配層可以被呈現。結構708可以具有銲接球或在RDL上且耦合至一電路板之其他耦合結構,例如,圖8之主機板。結構710對應至方法600之610。於結構710
中,一附加的半導體裝置732可以耦合至RDL。結構712對應至方法600之610。於結構712中,一附加的半導體裝置730可以藉由通孔734耦合至裝置720。結構714對應至方法600之610。於結構714中,附加的半導體裝置730可以藉由通孔734耦合至裝置720並且另一個附加的半導體裝置732可以耦合至該RDL。
各種操作以最有助於了解所申請主題標的之一方式,依序地被說明如複數個離散操作。但是,說明順序不應被理解為暗喻這些操作必定得是順序依存的。
本揭示實施例可以使用任何適當的硬體及/或軟體依所需地組配而實行於一系統中。圖8圖解地例示依據一些實施例如於圖1-5之展示以及如先前所述地之一計算裝置,其包括如此處所說明之一堆疊半導體裝置封裝體。計算裝置800可以外罩一機板,例如,主機板802(例如,於外殼808中)。該主機板802可以包括一些構件,其包括,但是不受限定於一處理器804以及至少一通訊晶片806。該處理器804可以實體地和電氣地耦合至該主機板802。於一些實行例中,至少一通訊晶片806也可以是實體地和電氣地耦合至該主機板802。於進一步實行例中,該通訊晶片806可以是處理器804之部份。
取決於其之應用,計算裝置800可以包含其他構件,其可能是或可能不是實體地以及電氣地耦合至主機板802。這些其他構件可以包括,但是不受限定於,依電性記憶體(例如,DRAM)、非依電性記憶體(例如,ROM)、
快閃記憶體、一圖形處理器、一數位信號處理器、一密碼處理器、一晶片組、一天線、一顯示器、一觸控屏幕顯示器、一觸控屏幕控制器、一電池、一音訊編解碼器、一視訊編解碼器、一功率放大器、一全球定位系統(GPS)裝置、一羅盤、MEMS感應、一蓋格(Geiger)計數器、一加速器、一迴旋儀、一揚聲器、一攝影機、以及一大量儲存裝置(例如,硬碟驅動器、小型碟片(CD)、數位多功能碟片(DVD)、以及其它者)。
通訊晶片806可以致能用於轉移資料至與自計算裝置800之無線通訊。詞語“無線”以及其之衍生詞可以使用以說明電路、裝置、系統、方法、技術、通訊頻道、等等,其可以經由一非固態媒體經由調變電磁輻射之使用而通訊資料。該字詞並非喻指不包含任何電線之相關聯的裝置,雖然於一些實施例中,它們可能不包含。該通訊晶片806可以實行任何的一些無線標準或協定,其包括但是不受限定於電機電子工程師(IEEE)協會標準,如包含WiGig、Wi-Fi(IEEE 802.11家族)、IEEE 802.16標準(例如,IEEE 802.16-2005修訂版)、長期演進(LTE)與任何修訂、更新、及/或修訂版(例如,先進LTE方案、超級行動寬頻(UMB)方案(也稱為“3GPP2”)等等)。IEEE 802.16相容寬頻無線接取(BWA)網路一般係稱為WiMAX網路,其是代表全球互通微波接取之縮寫字,其是通過對於IEEE 802.16標準之遵行與互通測試的產品認證標誌。該通訊晶片806可以依據全球行動式通訊系統(GSM)、通用封裝無
線電服務(GPRS)、通用行動電信系統(UMTS)、高速封裝接取(HSPA)、進化HSPA(E-HSPA)、或LTE網路之一而操作。該通訊晶片806可以依據GSM演進增強資料(EDGE)、GSMEDGE無線電接取網路(GERAN)、通用陸地無線電接取網路(UTRAN)、或進化UTRAN(E-UTRAN)而操作。該通訊晶片806可以依據下列協定而操作,如分碼多重接取(CDMA)、分時多重接取(TDMA)、數位增強無線電信(DECT)、進化資料最佳化(EV-DO)、其衍生物件、以及標明作為3G、4G、5G、和以後者之任何其他無線協定。於其他實施例中,通訊晶片806可以依據其他無線協定而操作。
計算裝置800可以包括複數個通訊晶片806。例如,一第一通訊晶片806可以是專用於較短範圍無線通訊,例如,WiGig,Wi-Fi和藍芽,並且一第二通訊晶片806可以是專用於較長範圍之無線通訊,例如,GPS、EDGE、GPRS、CDMA、WiMAX、LTE、EV-DO、以及其他者。
計算裝置800之處理器804可以被封裝在如此處所說明且被例示於圖1-5中之一堆疊半導體裝置封裝體中。例如,圖2之電路板206可以是一主機板802並且處理器804可以是架設在如上述圖1-5中之一堆疊半導體裝置封裝體中的一晶粒104d、106d、408、504。該堆疊半導體裝置封裝體和該主機板802可以使用封裝層級互連(例如,銲料球、墊片、凸塊、或柱狀物、或其他適當的互連)而耦
合在一起。其他適當的組配也可以依據此處所說明之實施例而實行。字詞“處理器”可以涉及處理來自暫存器及/或記憶體之電子資料的任何裝置或一裝置之部份,以轉換電子資料成為可以儲存於暫存器及/或記憶體中之其他電子資料。
如此處所說明地,通訊晶片806也可以包括一晶粒(例如,RF晶粒),其可以被封裝於圖1-5之一堆疊半導體裝置封裝體中。於進一步實行例中,受罩在計算裝置800之內的另一構件(例如,記憶體裝置或其他積體電路裝置)可以包括一晶粒,如此處所說明地,其可以被封裝在圖1-5之一堆疊半導體裝置封裝體中。
於各種實行例中,計算裝置800可以是一膝上型電腦、一小筆電、一筆記型電腦、一超級書、一智慧型手機、一平板電腦、一個人數位助理(PDA)、一超級活動PC,一活動電話、一桌上型電腦、一伺服器、一印表機、一掃描器、一監視器、一機上盒、一娛樂遊藝控制單元、一數位攝影機、一輕便型音樂播放機、或一數位視訊記錄器。於一些實施例中,計算裝置800可以是一活動計算裝置。於進一步實行例中,該計算裝置800可以是處理資料之任何其他電子裝置。
範例
依據各種實施例,本揭示說明一堆疊半導體裝置封裝體。一堆疊半導體裝置封裝體(封裝體)之範例1可以包括一基體,其具有一第一側與相對於該第一側之一第二
側,其中該第一側具有複數個墊片且該第二側具有包括於一第二側扇出區域中之墊片的複數個墊片,其中該基體具有電氣路由特點,該等電氣路由特點被組配以電氣地耦合該第一側上之該等複數個墊片的墊片與包括該第二側扇出區域之該等墊片的該第二側上該等複數個墊片的墊片;一第一半導體裝置,其具有一第一裝置墊片側耦合於該基體之該第一側上之該等複數個墊片的一墊片;一第二半導體裝置,其具有一第二裝置墊片側耦合於該基體之該第二側上之該等複數個墊片一墊片,該第一半導體裝置和該第二半導體裝置是藉由該等電氣路由特點通過該基體而電氣地耦合在一起;以及一介電質層,其具有一第一側耦合於該基體之該第二側且包覆該第二半導體裝置,其中該介電質層具有複數個導電通孔電氣地耦合於該第二側扇出區域中之該等墊片且係組配以在該介電質層的該第一側與該介電質層的一第二側之間安排該第一半導體裝置和該第二半導體裝置之電氣信號路由,該介電質層之該第二側相對於該介電質層之該第一側。
範例2可以包括範例1之封裝體,其中該第一半導體裝置是一覆晶晶粒。
範例3可以包括範例1之封裝體,其中第一半導體裝置和基體是包含一個或多個半導體晶粒之一組合半導體封裝體。
範例4可以包括範例3之封裝體,其中該組合半導體封裝體包含一晶圓層級晶片尺度封裝體、一嵌入式扇
出晶圓層級封裝體、或一扇入晶圓層級封裝體。
範例5可以包括範例1之該封裝體,進一步地包含下列之至少一者:一個或多個附加的半導體裝置,其各具有耦合至該基體之該一側上的該等複數個墊片之一墊片的複數個墊片;以及一個或多個附加的半導體裝置,其各具有耦合至該基體之該第二側上的該等複數個墊片之一墊片的複數個墊片,該介電質層包覆該等一個或多個附加的半導體裝置。
範例6可以包括範例1之該封裝體,進一步地包括包覆該第一半導體裝置之一鑄模複合物。
範例7可以包括範例1-6之任何封裝體,其中該第二半導體裝置是一覆晶晶粒、一晶圓層級晶片尺度封裝體、一晶圓層級封裝體、一、嵌入式晶圓層級封裝體、或一面板層級封裝體。
範例8可以包括範例1之該封裝體,進一步地包括一重新分配層,其具有耦合於該介電質層之該第二側的一第一側,其中該重新分配層具有電氣地耦合該等複數個導電通孔至該重新分配層一第二側上之複數個墊片的複數個導電路徑,該重新分配層之該第二側相對於該重新分配層之該第一側,該重新分配層之該第二側上的該等複數個墊片包括在該第二半導體裝置之一區域下方的墊片。
範例9可以包括範例8之封裝體,其進一步地包括一個或多個附加的半導體裝置之至少一者,其各具有耦合至該重新分配層第二側上之該等複數個墊片的一墊片之
複數個墊片;以及一個或多個第二集合之附加的半導體裝置,其各具有複數個墊片,該等墊片之至少一者耦合至第一半導體裝置az第二側上的複數個墊片之一墊片,該第二側相對該第一裝置墊片側,該第一半導體裝置第二側上之該等複數個墊片藉由導電路徑之一第一裝置多數個而耦合至該基體。
範例10可以包括範例1之該封裝體,其中該第一半導體裝置和該第二半導體裝置各是選自由半導體晶粒、被動半導體裝置、主動半導體裝置、半導體封裝體、半導體模組、表面架設在半導體裝置、和整合被動裝置、以及其組合所構成的族群之一個或多個裝置。
範例11可以包括範例1之該封裝體,其中該介電質層是包含聚合物或聚合物複合材料的一個或多個層。
範例12可以包括範例11之封裝體,其中該等聚合物或聚合物複合材料是選自味之素(Ajinomoto)建構薄膜(ABF)、耐燃劑FR2、耐燃劑FR4、樹脂塗層銅(RCC)膜、聚亞胺、被動薄膜、聚苯并噻唑(PBZT)、聚苯并噁唑(PBO)、和鑄模複合物、以及其組合所構成的族群。
構成一堆疊半導體裝置封裝體之一方法的範例13(方法)可以包括下列步驟:提供具有一第一側與相對於該第一側之一第二側的一基體,該第一側具有複數個墊片,該第二側具有複數個墊片,及一第一半導體裝置,該第一半導體裝置具有一第一裝置墊片側耦合於該基體之該第一側上之該等複數個墊片的一墊片,和一第二半導體裝
置,該第二半導體裝置具有一第二裝置墊片側耦合於該基體該第二側上的該等複數個墊片之一墊片;以及形成一介電質層於該基體之該第二側上,該介電質層包覆該第二半導體裝置,該形成步驟進一步地包含層疊、塗層、或組合式層疊和塗層一個或多個聚合物或聚合物複合材料。
範例14可以包括範例13之方法,其中該等聚合物或聚合物複合材料是選自味之素(Ajinomoto)建構薄膜(ABF)、耐燃劑FR2、耐燃劑FR4、樹脂塗層銅(RCC)膜、聚亞胺、被動薄膜、聚苯并噻唑(PBZT)、聚苯并噁唑(PBO)、和鑄模複合物、以及其組合所構成的族群。
範例15可以包括範例13之方法,其中該介電質層之一第一側是耦合於該基體之該第二側,該方法進一步地包括:形成通過該介電質層之導電通孔以連接該基體之該第二側上的該等複數個墊片之至少一者至該介電質層之一第二側上的複數個墊片之至少一者,該介電質層之該第二側相對於該介電質層之該第一側。
範例16可以包括範例13之方法,其進一步地包括形成耦合於該介電質層之該第二側的一重新分配層。
範例17可以包括範例13之方法,進一步地包含一個或多個附加的半導體裝置之至少一者,其各具有耦合至該重新分配層第二側上之該等複數個墊片的一墊片之複數個墊片;以及一個或多個第二集合之附加的半導體裝置,其各具有複數個墊片,該等墊片之至少一者耦合至第一半導體裝置一第二側上的複數個墊片之一墊片,該第二
側相對該第一裝置墊片側,該第一半導體裝置第二側上之該等複數個墊片藉由導電路徑之一第一裝置多數個而耦合至該基體。
一計算裝置之範例18可以包括一電路板;以及一堆疊半導體裝置封裝體,其包括:一基體,其具有一第一側和相對於該第一側之一第二側,其中該第一側具有複數個墊片且該第二側具有包括於一第二側扇出區域中之墊片的複數個墊片,其中該基體具有電氣路由特點,該等電氣路由特點被組配以電氣地耦合該第一側上之該等複數個墊片的墊片與包括該第二側扇出區域之該等墊片的該第二側上該等複數個墊片的墊片;一第一半導體裝置,其具有一第一裝置墊片側耦合於該基體之該第一側上之該等複數個墊片的一墊片;一第二半導體裝置,其具有一第二裝置墊片側耦合於該基體之該第二側上之該等複數個墊片一墊片,該第一半導體裝置和該第二半導體裝置是藉由該等電氣路由特點通過該基體而電氣地耦合在一起;一介電質層,其具有一第一側耦合於該基體之該第二側且包覆該第二半導體裝置,其中該介電質層具有複數個導電通孔電氣地耦合於該第二側扇出區域中之該等墊片且係組配以在該介電質層的該第一側與該介電質層的一第二側之間安排該第一半導體裝置和該第二半導體裝置之電氣信號路由,該介電質層之該第二側相對於該介電質層之該第一側;以及一重新分配層,其具有耦合於該介電質層之該第二側的一第一側,其中該重新分配層具有電氣地耦合於該等複數個
導電通孔至該重新分配層之一第二側上之複數個墊片的複數個導電路徑,該重新分配層之該第二側相對於該重新分配層之該第一側,該重新分配層之該第二側電氣地耦合至該電路板,該重新分配層之該第二側上的該等複數個墊片包括在該第二半導體裝置之一區域下方的墊片。
範例19可以包括範例18之裝置,其中該第一半導體裝置是包覆於一鑄模複合物中之一覆晶晶粒。
範例20可以包括範例18之裝置,其中該第一半導體裝置和該基體是包含一個或多個半導體晶粒之一組合半導體封裝體。
範例21可以包括範例20之裝置,其中該組合半導體封裝體包括一晶圓層級晶片尺度封裝體、一嵌入式扇出晶圓層級封裝體、或一扇入晶圓層級封裝體。
範例22可以包括範例18之裝置,其進一步地包含一個或多個附加的半導體裝置,其各具有複數個墊片,該等墊片之至少一者耦合至該基體之該第一側上的該等複數個墊片之一墊片;以及一個或多個附加的半導體裝置,其各具有複數個墊片,該等墊片之至少一者耦合至該基體之該第二側上的該等複數個墊片之一墊片,該介電質層包覆該等一個或多個附加的半導體裝置。
範例23可以包括範例18之裝置,其進一步地包括包覆該第一半導體裝置之一鑄模複合物。
範例24可以包括範例18-23之任一者的裝置,其中該第二半導體裝置是一覆晶晶粒、一晶圓層級晶片尺度
封裝體、一晶圓層級封裝體、一嵌入式晶圓層級封裝體、或一面板層級封裝體。
範例25可以包括範例18之裝置,其進一步地包括一個或多個附加的半導體裝置之至少一者,其各具有耦合至該重新分配層第二側上之該等複數個墊片的一墊片之複數個墊片;以及一個或多個第二集合之附加的半導體裝置,其各具有複數個墊片,該等墊片之至少一者耦合至第一半導體裝置az第二側上的複數個墊片之一墊片,該第二側相對該第一裝置墊片側,該第一半導體裝置第二側上之該等複數個墊片藉由導電路徑之一第一裝置多數個而耦合至該基體。
範例26可以包括範例18之裝置,其中該第一半導體裝置和該第二半導體裝置各是選自由半導體晶粒、被動半導體裝置、主動半導體裝置、半導體封裝體、半導體模組、表面架設在半導體裝置、和整合被動裝置、以及其組合所構成的族群之一個或多個裝置。
範例27可以包括範例18之裝置,其中該介電質層是包含聚合物或聚合物複合材料的一個或多個層。
範例28可以包括範例27之裝置,其中該等材料是選自味之素(Ajinomoto)建構薄膜(ABF)、耐燃劑FR2、耐燃劑FR4、樹脂塗層銅(RCC)膜、聚亞胺、被動薄膜、聚苯并噻唑(PBZT)、聚苯并噁唑(PBO)、和鑄模複合物、以及其組合所構成的族群。
範例29可以包括範例18之裝置,其中該計算裝
置是一可穿戴式裝置或一行動式計算裝置,該可穿戴式裝置或該行動式計算裝置包括與該電路板耦合的一天線、一顯示器、一觸控屏幕顯示器、一觸控屏幕控制器、一電池、一音訊編解碼器、一視訊編解碼器、一功率放大器、一全球定位系統(GPS)裝置、一羅盤、一蓋革(Geiger)計數器、一加速器、一迴旋儀、一揚聲器、或一攝影機之一者或多者。
範例30可以包括範例18之裝置,其中該電路板是由一可撓性材料所組成。
100‧‧‧封裝體
102‧‧‧基體
102a‧‧‧基體第一側
102b‧‧‧基體第二側
102c‧‧‧電氣路由特點
102d、102g‧‧‧扇出區域
102e、102f‧‧‧電氣連接點
104‧‧‧第一半導體裝置
104a‧‧‧底部填膠材料側
104c‧‧‧晶粒不主動側/第二側
104d、106d‧‧‧晶粒
104d.1、106d.1‧‧‧半導體基體
104d.2、106d.2‧‧‧裝置層
104d.3、106d.3‧‧‧互連層
104e‧‧‧鑄模複合物
104f‧‧‧第一半導體裝置第一側
104g、106g‧‧‧底部填膠材料
104h、106h‧‧‧晶粒-層級互連結構
106‧‧‧第二半導體裝置
106a‧‧‧基體與填膠材料接觸點
106c‧‧‧第二半導體裝置第二側
106f‧‧‧第二半導體裝置第一側
108‧‧‧介電質層
108a‧‧‧介電質層第一側
108b‧‧‧介電質層第二側
108c‧‧‧電氣路由特點
Claims (20)
- 一種堆疊半導體裝置封裝體,其包含:一基體,其具有一第一側與相對於該第一側之一第二側,其中該第一側具有複數個墊片並且該第二側具有包括於一第二側扇出區域中之墊片的複數個墊片,其中該基體具有電氣路由特點被組配用以電氣地耦合在該第一側上之該等複數個墊片的墊片與包括該第二側扇出區域之該等墊片的該第二側上之該等複數個墊片的墊片;一第一半導體裝置,其具有一第一裝置墊片側與該基體之該第一側上之該等複數個墊片的一墊片耦合;一第二半導體裝置,其具有一第二裝置墊片側與該基體之該第二側上之該等複數個墊片的一墊片耦合,該第一半導體裝置和該第二半導體裝置是藉由該等電氣路由特點經由該基體而電氣地耦合在一起;以及一介電質層,其具有一第一側與該基體之該第二側耦合並且包覆該第二半導體裝置,其中該介電質層具有複數個導電通孔電氣地與該第二側扇出區域中之該等墊片耦合並且經組配用以在該介電質層的該第一側與該介電質層的一第二側之間安排該第一半導體裝置和該第二半導體裝置之電氣信號路由,該介電質層之該第二側相對於該介電質層之該第一側。
- 如請求項1之封裝體,其中該第一半導體裝置是一覆晶晶粒。
- 如請求項1之封裝體,其中該第一半導體裝置和該基體是包含一個或多個半導體晶粒之一組合半導體封裝體。
- 如請求項3之封裝體,其中該組合半導體封裝體包含一晶圓層級晶片尺度封裝體、一嵌入式扇出晶圓層級封裝體、或一扇入晶圓層級封裝體。
- 如請求項1之封裝體,其進一步地包含下列之至少一者:一個或多個附加的半導體裝置,其各具有複數個墊片耦合至該基體之該第一側上的該等複數個墊片之一墊片;以及一個或多個附加的半導體裝置,其各具有複數個墊片耦合至該基體之該第二側上的該等複數個墊片之一墊片,該介電質層包覆該等一個或多個附加的半導體裝置。
- 如請求項1之封裝體,其進一步地包含:包覆該第一半導體裝置之一鑄模複合物。
- 如請求項1之封裝體,其中該第二半導體裝置是一覆晶晶粒、一晶圓層級晶片尺度封裝體、一晶圓層級封裝體、一嵌入式晶圓層級封裝體、或一面板層級封裝體。
- 如請求項1之封裝體,其進一步地包含:一重新分配層,其具有與該介電質層之該第二側耦合的一第一側,其中該重新分配層具有電氣地耦合該等複數個導電通孔至該重新分配層之一第二側上之複數 個墊片的複數個導電路徑,該重新分配層之該第二側相對於該重新分配層之該第一側,該重新分配層之該第二側上的該等複數個墊片包括在該第二半導體裝置之一區域下方的墊片。
- 一種製造一堆疊半導體裝置封裝體之方法,該方法包含:提供具有一第一側與相對於該第一側之一第二側的一基體,該第一側具有複數個墊片,該第二側具有複數個墊片,及一第一半導體裝置具有一第一裝置墊片側耦合至該基體之該第一側上之該等複數個墊片的一墊片,和一第二半導體裝置具有一第二裝置墊片側耦合至該基體之該第二側上的該等複數個墊片的一墊片;以及形成一介電質層於該基體之該第二側上,該介電質層包覆該第二半導體裝置,形成進一步地包含層疊、塗層、或組合式層疊和塗層一個或多個聚合物或聚合物複合材料。
- 如請求項9之方法,其中該介電質層之一第一側是與該基體之該第二側耦合,該方法進一步地包含:形成經由該介電質層之導電通孔用以連接該基體之該第二側上的該等複數個墊片之至少一者至該介電質層之一第二側上的複數個墊片之至少一者,該介電質層之該第二側相對於該介電質層之該第一側。
- 如請求項9之方法,進一步地包含:形成耦合至該介電質層之該第二側的一重新分配 層。
- 一種計算裝置,其包含:一電路板;以及一堆疊半導體裝置封裝體,其包含:一基體,其具有一第一側和相對於該第一側之一第二側,其中該第一側具有複數個墊片並且該第二側具有包括於一第二側扇出區域中之墊片的複數個墊片,其中該基體具有電氣路由特點被組配用以電氣地耦合在該第一側上之該等複數個墊片的墊片與包括該第二側扇出區域之該等墊片的該第二側上之該等複數個墊片的墊片;一第一半導體裝置,其具有一第一裝置墊片側與該基體之該第一側上之該等複數個墊片的一墊片耦合;一第二半導體裝置,其具有一第二裝置墊片側與該基體之該第二側上之該等複數個墊片一墊片耦合,該第一半導體裝置和該第二半導體裝置是藉由該等電氣路由特點經由該基體而電氣地耦合在一起;一介電質層,其具有一第一側與該基體之該第二側耦合並且包覆該第二半導體裝置,其中該介電質層具有複數個導電通孔電氣地與該第二側扇出區域中之該等墊片耦合並且經組配用以在該介電質層的該第一側與該介電質層的一第二側之間安排該第一半導體裝置和該第二半導體裝置之電氣信號路由,該介電質層之該第二側相對於該介電質層之該第一側;以及 一重新分配層,其具有與該介電質層之該第二側耦合的一第一側,其中該重新分配層具有電氣地耦合於該等複數個導電通孔至該重新分配層之一第二側上之複數個墊片的複數個導電路徑,該重新分配層之該第二側相對於該重新分配層之該第一側,該重新分配層之該第二側電氣地耦合至該電路板,該重新分配層之該第二側上的該等複數個墊片包括在該第二半導體裝置之一區域下方的墊片。
- 如請求項12之計算裝置,其中該第一半導體裝置是包覆於一鑄模複合物中之一覆晶晶粒。
- 如請求項12之計算裝置,其中該第一半導體裝置和該基體是包含一個或多個半導體晶粒之一組合半導體封裝體。
- 如請求項14之計算裝置,其中該組合半導體封裝體包含一晶圓層級晶片尺度封裝體、一嵌入式扇出晶圓層級封裝體、或一扇入晶圓層級封裝體。
- 如請求項12之計算裝置,其進一步地包含下列之至少一者:一個或多個附加的半導體裝置,其各具有複數個墊片,該等墊片之至少一者耦合至該基體之該第一側上的該等複數個墊片之一墊片;以及一個或多個附加的半導體裝置,其各具有複數個墊片,該等墊片之至少一者耦合至該基體之該第二側上的該等複數個墊片之一墊片,該介電質層包覆該等一個或 多個附加的半導體裝置。
- 如請求項12之計算裝置,其進一步地包含:包覆該第一半導體裝置之一鑄模複合物。
- 如請求項12之計算裝置,其中該第二半導體裝置是一覆晶晶粒、一晶圓層級晶片尺度封裝體、一晶圓層級封裝體、一嵌入式晶圓層級封裝體、或一面板層級封裝體。
- 如請求項15之計算裝置,其中該計算裝置是一可穿戴式裝置或一行動式計算裝置,該可穿戴式裝置或該行動式計算裝置包括與該電路板耦合的下列中之一或多者:一天線、一顯示器、一觸控屏幕顯示器、一觸控屏幕控制器、一電池、一音訊編解碼器、一視訊編解碼器、一功率放大器、一全球定位系統(GPS)裝置、一羅盤、一蓋革計數器、一加速器、一迴旋儀、一揚聲器、或一攝影機。
- 如請求項15之計算裝置,其中該電路板是由一可撓性材料所組成。
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Also Published As
Publication number | Publication date |
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GB2548070B (en) | 2020-12-16 |
TW201633501A (zh) | 2016-09-16 |
JP2017507499A (ja) | 2017-03-16 |
KR20180006503A (ko) | 2018-01-17 |
KR20160088233A (ko) | 2016-07-25 |
BR112015029099A2 (pt) | 2017-07-25 |
US20160329272A1 (en) | 2016-11-10 |
JP6435556B2 (ja) | 2018-12-12 |
GB2548070A (en) | 2017-09-13 |
DE112014003166T5 (de) | 2016-10-20 |
GB201520317D0 (en) | 2015-12-30 |
CN105518860A (zh) | 2016-04-20 |
WO2016099523A1 (en) | 2016-06-23 |
KR102156483B1 (ko) | 2020-09-15 |
DE112014003166B4 (de) | 2021-09-23 |
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