TW201606955A - 可攀登之封裝體架構與相關聯技術及組態 - Google Patents

可攀登之封裝體架構與相關聯技術及組態 Download PDF

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TW201606955A
TW201606955A TW104118155A TW104118155A TW201606955A TW 201606955 A TW201606955 A TW 201606955A TW 104118155 A TW104118155 A TW 104118155A TW 104118155 A TW104118155 A TW 104118155A TW 201606955 A TW201606955 A TW 201606955A
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die
mold compound
assembly
package body
active
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TW104118155A
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TWI614847B (zh
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桑卡 葛尼森
巴森 奇亞戴
尼特西 尼姆卡
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英特爾公司
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Abstract

本發明之實施例描述積體電路(IC)總成之可攀登之封裝體架構與相關聯技術及組態。在一個實施例中，一積體電路(IC)總成包括：一封裝體基體，其具有一第一側面及與該第一側面對置安置之一第二側面；一第一晶粒，其具有與該封裝體基體之該第一側面耦接之一作用側面及與該作用側面對置安置之一非作用側面，該第一晶粒具有經組配以在該第一晶粒與一第二晶粒之間路由電信號之一或多個矽穿孔(TSV)；以及一模複合物，其安置於該封裝體基體之該第一側面上，其中該模複合物與該第一晶粒的在該作用側面與該非作用側面之間之一側壁直接接觸且其中該第一側面與該模複合物的離該第一側面最遠之一終止邊緣之間的一距離等於或小於該第一晶粒之該非作用側面與該第一側面之間的一距離。可描述及/或主張其他實施例。

Description

可攀登之封裝體架構與相關聯技術及組態 發明領域
本發明之實施例大體上係關於積體電路(IC)總成之領域，且更特定言之係關於可攀登之封裝體架構與相關聯技術及組態。
發明背景
目前，新興的積體電路(IC)總成可包括三維(3D)封裝體架構，其中一或多個晶粒(例如，記憶體晶粒)堆疊於另一晶粒(例如，系統單晶片晶粒)上。堆疊晶粒可以一些組態懸於下伏晶粒之上，此可產生諸如堆疊晶粒之開裂之缺陷的風險。目前，下伏晶粒或懸垂物之收縮縮放可不當地受限以便緩和此等風險。另外，隨著IC總成繼續收縮至較小尺寸，可能需要提供3D封裝體架構之較小Z高度以用於諸如行動裝置之較小裝置。
依據本發明之一實施例，係特地提出一種積體電路(IC)總成，其包含：一封裝體基體，其具有一第一側面及 與該第一側面對置安置之一第二側面；一第一晶粒，其具有與該封裝體基體之該第一側面耦接之一作用側面及與該作用側面對置安置之一非作用側面，該第一晶粒具有經組配以在該第一晶粒與一第二晶粒之間路由電信號之一或多個矽穿孔(TSV)；以及一模複合物，其安置於該封裝體基體之該第一側面上，其中該模複合物與該第一晶粒的在該作用側面與該非作用側面之間之一側壁直接接觸且其中該第一側面與該模複合物的離該第一側面最遠之一終止邊緣之間的一距離等於或小於該第一晶粒之該非作用側面與該第一側面之間的一距離。
100、200‧‧‧積體電路(IC)總成
102a‧‧‧第一晶粒
102b‧‧‧第二晶粒
102c‧‧‧記憶體晶粒
103‧‧‧第一晶粒之側壁
104、104a‧‧‧封裝體基體
104b‧‧‧電絕緣材料
105‧‧‧晶粒間互連件
105a‧‧‧再分配特徵
106‧‧‧阻焊層
107‧‧‧矽穿孔(TSV)
108‧‧‧模複合物
109‧‧‧晶粒級互連件
110‧‧‧環氧樹脂式薄膜
111‧‧‧焊球
112‧‧‧底部填充材料
113‧‧‧穿膜互連件
114‧‧‧開口
115‧‧‧可焊接材料
130a、130b、130c‧‧‧襯墊
132‧‧‧跡線
133、135‧‧‧方向
140‧‧‧IC裝置
300‧‧‧方法
400‧‧‧計算裝置
402‧‧‧主機板
404‧‧‧處理器
406‧‧‧通訊晶片
408‧‧‧外殼
D1、D2‧‧‧距離
E‧‧‧模複合物之終止邊緣
S1‧‧‧第一側面
S2‧‧‧第二側面
藉由以下詳細描述結合隨附圖式，將容易理解實施例。為了促進此描述，類似參考數字指定類似結構元件。在隨附圖式之各圖中藉助於實例而非限制性地展示實施例。
圖1根據一些實施例示意地說明實例積體電路(IC)總成之截面側視圖。
圖2a至圖2h根據一些實施例示意地說明實例積體電路(IC)總成在製造之各種階段期間的截面側視圖。
圖3根據一些實施例示意地說明用於製造積體電路(IC)總成之方法的流程圖。
圖4根據一些實施例示意地說明包括如本文中所描述之IC總成的計算裝置。
較佳實施例之詳細說明
本發明之實施例描述積體電路(IC)總成之可攀登之封裝體架構與相關聯技術及組態。在以下描述中，將使用熟習此項技術者通常所使用之術語來描述說明性實施之各種態樣以向熟習此項技術者傳達其工作之本質。然而，熟習此項技術者將顯而易見本發明之實施例可用所描述態樣中之僅一些來實踐。出於解釋之目的，陳述特定數字、材料及組態以便提供對說明性實施之透徹理解。然而，熟習此項技術者應清楚，本發明之實施例可在沒有此等特定細節之情況下實踐。在其他情況下，省略或簡化熟知特徵以便不混淆說明性實施。
在以下詳細描述中，參考形成此處一部分的隨附圖式，其中通篇類似數字表示類似部件，且其中藉助於圖示顯示其中可實踐本發明之標的之實施例。應理解，在不背離本發明範疇之情況下，可利用其他實施例且可進行結構或邏輯變化。因此，以下詳細描述不應以限制性意義來理解，且實施例之範疇由所附申請專利範圍及其等效物來界定。
出於本發明之目的，片語「A及/或B」意謂(A)、(B)或(A及B)。出於本發明之目的，片語「A、B及/或C」意謂(A)、(B)、(C)、(A及B)、(A及C)、(B及C)或(A、B及C)。
描述可使用基於視角之描述，諸如頂部/底部、內/外、上方/下方及類似者。此等描述僅用以有助於論述且不欲將本文中所描述的實施例之應用限於任何特定定向。
描述可使用片語「在一實施例中」或「在實施例中」，該等片語各自可指相同或不同實施例中之一或多個。此外，如就本發明之實施例而使用，術語「包含」、「包括」、「具有」及其類似者為同義的。
術語「與耦接(coupled with)」以及其派生詞可在本文中使用。「耦接」可意謂以下各者中之一或多者。「耦接」可意謂兩個或兩個以上元件直接實體或電氣接觸。然而，「耦接」亦可意謂兩個或兩個以上元件彼此間接地接觸，但仍彼此協作或相互作用，且可意謂一或多個其他元件耦接或連接於被稱為彼此耦接之元件之間。
在各種實施例中，片語「在第二特徵上形成、沈積或以其他方式安置之第一特徵」可意謂第一特徵在第二特徵上方形成、沈積或安置，且第一特徵之至少一部分可與第二特徵之至少一部分直接接觸(例如，直接實體及/或電氣接觸)或間接接觸(例如，在第一特徵與第二特徵之間具有一或多個其他特徵)。
如本文所使用，術語「模組」可指以下各者、可為以下各者之部分或包括以下各者：執行一或多個軟體或韌體程式的特殊應用積體電路(ASIC)、電子電路、系統單晶片(SoC)、處理器(共用、專用或群組)及/或記憶體(共用、專用或群組)、組合邏輯電路及/或提供所描述功能性之其他合適組件。
圖1根據一些實施例示意地說明實例積體電路(IC)總成100之截面側視圖。根據各種實施例，IC總成100 可表示三維(3D)封裝體架構，其中一或多個晶粒堆疊於另一晶粒上。舉例而言，在一些實施例中，第一晶粒102a可與封裝體基體104耦接，且第二晶粒102b可堆疊於第一晶粒102a上。所描繪IC總成100在一些實施例中可僅表示IC總成之一部分。
根據各種實施例，IC總成100可包括封裝體基體104，該封裝體基體具有第一側面S1及與第一側面S1對置安置之第二側面S2。在一些實施例中，封裝體基體104為具有核心及/或累積層的環氧樹脂基層壓基體，諸如味之素累積膜(Ajinomoto Build-up Film；ABF)基體。在其他實施例中，封裝體基體104可為電路板，諸如使用任何合適印刷電路板(PCB)技術形成之PCB。封裝體基體104在其他實施例中可包括其他合適類型之基體，包括(例如)由玻璃、陶瓷或半導體材料形成之基體。
封裝體基體104可包括經組配以將諸如輸入/輸出(I/O)信號之電氣信號或電源/接地路由至或自一或多個晶粒(例如，第一晶粒102a)之電氣路由特徵。該等電氣路由特徵可包括(例如)安置於封裝體基體104之一或多個表面上的襯墊130a、130b或跡線132及/或內部路由特徵(未圖示)，諸如用以經由封裝體基體104路由電氣信號之導電線、通孔或其他互連件。舉例而言，在所描繪實施例中，封裝體基體104包括第一側面S1上的經組配以接收晶粒102之晶粒級互連件109的襯墊130a(其亦可被稱作「連接盤(land)」)及經組配以接收另一IC裝置140之封裝體級互連件(例如，穿 模互連件113)的襯墊130b。如可見，在一些實施例中，阻焊層106可安置於封裝體基體104之第一側面S1之外表面上。封裝體基體104之內部路由特徵或跡線132可經組配以在第一晶粒102a及/或第二晶粒102b與IC裝置140之一或多個電氣裝置(例如，晶粒)之間路由電氣信號。
一或多個封裝體級互連件(諸如一或多個焊球111)可形成於封裝體基體104之第二側面S2上以有助於封裝體基體104與其他電氣裝置(諸如，一電路板(例如，圖4之主機板402))之耦接。雖然為了避免混淆所描繪實施例之態樣而未圖示，但焊球111可與安置於封裝體基體104之第二側面S2上之對應襯墊耦接。
第一晶粒102a可與封裝體基體104耦接。第一晶粒102a可根據廣泛多種合適組態而附接至封裝體基體104，如所描繪，包括(例如)以一覆晶組態與封裝體基體104直接耦接。在該覆晶組態中，第一晶粒102a的包括主動式電路之作用側面係使用晶粒級互連結構109(諸如凸塊、支柱或亦可電氣耦接第一晶粒102a與封裝體基體104之其他合適結構)附接至封裝體基體104之表面。一非作用側面可與第一晶粒102a之作用側面對置安置。
在一些實施例中，第一晶粒102a可包括經組配以在第一晶粒102a與第二晶粒102b(其與第一晶粒102a耦接)之間路由電氣信號的一或多個矽穿孔(TSV)107。舉例而言，TSV 107可電氣耦接第一晶粒102a之作用側面上之主動式電路與晶粒間互連件105(諸如凸塊、支柱或耦接第二晶 粒102b與第一晶粒102a之其他合適結構)。在所描繪實施例中，第二晶粒102b之作用側面係使用可與TSV 107電氣耦接之晶粒間互連件105以一覆晶組態附接至第一晶粒102a之非作用側面。
第一晶粒102a及/或第二晶粒102b可表示由半導體材料(例如，矽)使用半導體製造技術(諸如，結合形成互補金屬氧化物半導體(CMOS)裝置所使用之薄膜沈積、微影、蝕刻及類似者)製成之個別產品。在一些實施例中，第一晶粒102a及/或第二晶粒102b可包括或為處理器、記憶體、系統單晶片(SoC)或ASIC之一部分。在一個實施例中，第一晶粒102a可表示一SoC晶粒且第二晶粒102b可表示一記憶體晶粒。
根據各種實施例，模複合物108可形成於封裝體基體104之第一側面S1上。模複合物108可由一電絕緣材料組成，諸如經形成以囊封IC總成100之特徵且保護該等特徵使之免於諸如潮濕或氧化之環境危害之一聚合物。在一些實施例中，如可見，模複合物108在第一晶粒102a之作用側面與非作用側面之間可與第一晶粒102a之側壁103直接接觸。
在一些實施例中，封裝體基體104之第一側面S1與模複合物108的離第一側面S1最遠之終止邊緣E之間的距離D1等於或小於封裝體基體104之第一側面S1與第一晶粒102a之非作用側面之間的距離D2。提供以此方式組配之模複合物108可允許第二晶粒102b黏結至模複合物108。舉例 而言，在所描繪實施例中，第二晶粒102b在平行於大體上藉由封裝體基體104之第一側面S1界定之一平面的一方向(例如，藉由箭頭133指示)上延伸更遠。此外，在所描繪實施例中，模複合物108之終止邊緣E與第一晶粒102a之非作用側面實質上平面或齊平，以使得第二晶粒102b部分地安裝於模複合物108之終止邊緣E上。由模複合物108提供之結構支撐可減小第二晶粒102b之懸垂部分上之應力，此可減少諸如第二晶粒102b之開裂的缺陷，可允許第一晶粒102a及/或第二晶粒102b之收縮縮放，或允許第二晶粒102b之更大懸垂部分而不開裂，或允許該IC總成相對於不具有如所述組態之模複合物108之IC總成的Z高度(例如，在藉由箭頭135指示之方向上)的縮小。
在其他實施例中，第二晶粒102b之至少一部分可在與藉由第一側面S1界定之平面並行的其他方向上延伸(例如，進出圖1之頁面)。在其他實施例中，距離D1可小於D2且另一中間材料可安置於第二晶粒102b之懸垂部分與模複合物108(諸如，環氧樹脂基材料(例如，環氧樹脂式薄膜110)或其他合適材料)之間。
在一些實施例中，環氧樹脂式薄膜110在第一晶粒102a與第二晶粒102b之間可安置於第一晶粒102a之非作用側面上且在第二晶粒102b與模複合物108之終止邊緣E之間可進一步安置於模複合物108之終止邊緣E上。在一些實施例中，環氧樹脂式薄膜110可(例如)包括環氧樹脂焊劑膜。
在一些實施例中，底部填充材料112在第二晶粒 102b之作用側面與非作用側面之間可與第二晶粒102b之側壁直接接觸或覆蓋該側壁，如例如在所描繪實施例中可見。底部填充材料112可安置於模複合物108之終止邊緣E上。底部填充材料112可經組配以保護第二晶粒102b之邊緣使之免於環境或處置危害。在一些實施例中，底部填充材料112可由環氧樹脂基材料或任何其他合適材料組成。儘管未描繪，但在其他實施例中，底部填充材料可安置於第一晶粒102a之作用側面與替代模複合物108的封裝體基體104之第一側面S1之間。
在一些實施例中，一或多個穿模互連件(through-mold interconnect，TMI)113可穿過模複合物108形成以允許IC裝置140與封裝體基體104之耦接。該等一或多個TMI 113可包括穿過模複合物108形成的用導電材料(諸如可焊接材料115)填充之開口。可焊接材料115可包括(例如)經回焊以在封裝體基體上之襯墊130b與IC裝置上之襯墊130c之間形成焊接點的一或多個焊球。
IC裝置140可表示廣泛多種合適裝置，包括(例如)晶粒或諸如記憶體封裝體之其他封裝體總成。在所描繪實施例中，IC裝置140包括封裝體基體104a(其可與結合封裝體基體104所描述之實施例一致)及形成於封裝體基體104a上之阻焊層106。第一晶粒102a及第二晶粒102b可安置於封裝體基體104之第一側面S1與IC裝置140之間。在其他實施例中，IC裝置140可包括廣泛多種其他合適組態。
圖2a至圖2h根據一些實施例示意地說明實例積 體電路(IC)總成200在製造之各種階段期間的截面側視圖。IC總成200可與結合圖1之IC總成100所描述之實施例一致且反之亦然。在圖2a至圖2h中之每一者可不重複一些參考標記以避免混淆所描述實施例之態樣。
參看圖2a，在提供或製造封裝體基體104之後描繪IC總成200。封裝體基體104可包括(例如)與第二側面S2對置安置之第一側面S1、襯墊130a、130b、跡線132、阻焊層106、晶粒級互連件109及可焊接材料115，如結合圖1之IC總成100所描述。在一些實施例中，晶粒級互連件109可包括受控塌陷晶片連接(C4)且襯墊130b可被稱作疊層封裝體(PCP)連接盤。
參看圖2b，在使用晶粒級互連件109以覆晶組態耦接第一晶粒102a之作用側面與封裝體基體104之第一側面S1之後描繪IC總成200。在其他實施例中，可在耦接第一晶粒102a與襯墊130a之前將晶粒級互連件109(例如，可焊接材料)沈積於第一晶粒102a上。第一晶粒102a可包括經組配以在第一晶粒102a與第二晶粒(例如，圖2e之第二晶粒102b)之間路由電氣信號的一或多個TSV 107，以及再分佈特徵105a，(諸如形成於第一晶粒102a之非作用側面上以用於接收晶粒間互連件(諸如用於耦接第二晶粒與第一晶粒102a之邏輯至記憶體互連件(LMI))的襯墊及/或跡線。
參看圖2c，在於封裝體基體104之第一側面S1上形成模複合物108之後描繪IC總成200。在一些實施例中，模複合物108可形成至暴露晶粒模(ExDM)中，以使得第一 晶粒102a之非作用側面保持暴露且模複合物108之終止邊緣E與第一晶粒102a之非作用側面相對於封裝體基體之第一側面S1之位準相齊或在該位準以下。模複合物108可(例如)藉由壓縮或轉移模製、旋塗或滑塗、層疊或任何其他合適技術來沈積。
參看圖2d，在將環氧樹脂式薄膜110沈積於第一晶粒102a之非作用側面上之後描繪IC總成200。在一些實施例中，環氧樹脂式薄膜110可進一步沈積於模複合物108之終止邊緣E上。在一些實施例中，環氧樹脂式薄膜110可包括焊劑以有助於第一晶粒102a與待堆疊於第一晶粒102a上之第二晶粒之間的電氣連接之形成。在沈積環氧樹脂式薄膜110之後，可清潔再分佈特徵105a以及模複合物之終止邊緣E。環氧樹脂式薄膜110可(例如)藉由使用任何其他合適構件施配環氧樹脂焊劑或附著環氧樹脂焊劑膜來沈積。在其他實施例中，可在第一晶粒102a上沈積除環氧樹脂基材料外的合適電絕緣材料。
參看圖2e，在以堆疊覆晶組態耦接第二晶粒102b與第一晶粒102a之後描繪IC總成200。第二晶粒102b可使用(例如)用以形成晶粒間互連件105之熱壓黏結及/或環氧樹脂式薄膜110之原位固化與第一晶粒102a耦接。底部填充材料112可如可見地與第二晶粒102b之側壁直接接觸沈積，且與模複合物108直接接觸以在第二晶粒102b之邊緣處形成保護障壁。底部填充材料112可(例如)藉由毛細管施配程序沈積。
參看圖2f，在於模複合物108中形成開口114以暴露襯墊130b上之可焊接材料115以作為形成TMI(例如，圖1之TMI 113)之部分之後描繪IC總成200。在其他實施例中，可形成開口114以暴露襯墊130b(例如，無可焊接材料115可安置於襯墊130b上)。開口114可為(例如)藉由雷射鑽孔技術形成之雷射介層孔。在其他實施例中，開口114可根據其他合適技術形成。
參看圖2g，在施加焊劑及將可焊接材料115(例如，一或多個焊球)置放於開口114中以及回焊可焊接材料以融合可焊接材料115與已在開口114中之可焊接材料或與襯墊130b(若無可焊接材料已安置於襯墊130b上)之後描繪IC總成200。此外，在一些實施例中，一或多個焊球111或其他封裝體級互連件可附著或以其他方式形成於封裝體基體104之第二側面S2上以有助於封裝體基體104與其他電氣裝置(諸如，一電路板)之耦接。
參看圖2h，在經由該等一或多個TMI 113耦接IC裝置140與封裝體基體104之第一側面S1之後描繪IC總成200。在一些實施例中，IC裝置140可為具有封裝體基體104a及安置於封裝體基體104a上之一或多個記憶體晶粒102c的記憶體封裝體。在一些實施例中，該等一或多個記憶體晶粒102c可囊封於諸如模複合物或層合物或其他合適結構的電絕緣材料104b中。可使用回焊工藝耦接封裝體基體104a上之襯墊130c與封裝體基體104上之對應襯墊130b以使用可焊接材料115形成焊接點。IC裝置140可表示包括晶粒、 封裝體或其他合適電氣總成的廣泛多種合適IC裝置。
圖3根據一些實施例示意地說明用於製造積體電路(IC)總成之方法300的流程圖。方法300可與結合圖1至圖2h所描述之實施例一致，反之亦然。
在302，方法300可包括提供一封裝體基體(例如，圖2a之封裝體基體104)，其具有一第一側面(例如，圖2a之第一側面S1)及與該第一側面對置之一第二側面(例如，圖2a之第二側面S2)。
在304，方法300可包括耦接一第一晶粒(例如，圖2b之第一晶粒102a)之一作用側面與該封裝體基體之該第一側面。該第一晶粒可包括一或多個TSV(例如，圖2b之TSV 107)且可以一覆晶組態附接。
在306，方法300可包括在該封裝體基體之該第一側面上形成一模複合物(例如，圖2c之模複合物108)。在一些實施例中，該模複合物與該第一晶粒之一側壁(例如，圖1之側壁103)直接接觸。該第一側面與該模複合物的離該第一側面最遠之一終止邊緣(例如，圖1之終止邊緣E)之間的距離(例如，圖1之距離D1)可等於或小於該第一晶粒之非作用側面與該封裝體基體之第一側面之間的距離(例如，圖1之距離D2)。該終止邊緣在一些實施例中可為實質上平面的。
在308，方法300可包括以一堆疊組態耦接一第二晶粒(例如，圖2e之第二晶粒102b)與該第一晶粒。一環氧樹脂式薄膜(例如，圖2d之環氧樹脂式薄膜110)可沈積於該第 一晶粒之該非作用側面上以及該模複合物之該終止邊緣上。該第二晶粒可藉由熱壓(例如，使用晶粒間互連件(例如，圖2e之晶粒間互連件105))與該第一晶粒耦接。一底部填充材料(例如，圖2e之底部填充材料112)可與該第二晶粒之一側壁直接接觸地沈積並沈積於該模複合物之該終止邊緣上。
在310，方法300可包括穿過該模複合物形成一或多個穿模互連件(TMI)(例如，圖2h之TMI 113)。該等TMI可(例如)藉由使用雷射製程穿過該模複合物鑽出開口及用可焊接材料填充該等開口來形成。
在312，方法300可包括經由該等一或多個TMI耦接一積體電路(IC)裝置(例如，圖2h之IC裝置140)與該封裝體基體之該第一側面。該IC裝置可使用一焊料回焊製程與該封裝體基體耦接以在該等TMI中之可焊接材料與該IC裝置及該封裝體基體上之各別襯墊之間形成一接合。
以最有助於理解所主張之標的之方式依次將各種操作描述為多個離散操作。然而，描述之次序不應解釋為暗示此等操作必須依賴於次序。
可使用任何合適硬體及/或軟體視需要進行組配而將本發明之實施例實施至系統中。圖4根據一些實施例示意地說明計算裝置400，其包括如本文中所描述之IC總成(例如，圖1之IC總成100或圖2a至圖2h之IC總成200)。計算裝置400可容納諸如主機板402之板(例如，於外殼408中)。主機板402可包括許多組件，包括(但不限於)處理器404及至 少一個通訊晶片406。處理器404可實體地且電氣地耦接至主機板402。在一些實施中，至少一個通訊晶片406亦可實體地且電氣地耦接至主機板402。在其他實施中，通訊晶片406可為處理器404之部分。
視應用而定，計算裝置400可包括可以或可不實體地且電氣地耦接至主機板402之其他組件。此等其他組件可包括(但不限於)依電性記憶體(例如，DRAM)、非依電性記憶體(例如，ROM)、快閃記憶體、圖形處理器、數位信號處理器、密碼處理器、晶片組、天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電池、音訊編碼解碼器、視訊編碼解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、蓋革計數器、加速度計、陀螺儀、揚聲器、攝影機及大容量儲存裝置(諸如硬碟機、光碟(CD)、數位化通用光碟(DVD)等)。
通訊晶片406可實現無線通訊以用於傳送資料至及自計算裝置400。術語「無線」及其衍生詞可用以描述可經由非固體媒體經由使用經調變電磁輻射來傳達資料之電路、裝置、系統、方法、技術、通訊頻道等。該術語並不暗示相關聯裝置不含有任何導線，雖然在一些實施例中該等裝置可能不含導線。通訊晶片406可實施許多無線標準或協定中之任一者，包括(但不限於)電氣電子工程師學會(IEEE)標準，包括WiGig、Wi-Fi(IEEE 802.11家族)、IEEE 802.16標準(例如，IEEE 802.16-2005修正案)、長期演進(LTE)計劃以及任何修正案、更新及/或修訂(例如，進階LTE 計劃、超級行動寬頻(UMB)計劃(亦被稱作「3GPP2」)等)。IEEE 802.16相容之寬頻無線存取(BWA)網路大體上被稱作WiMAX網路(表示微波存取全球互通之縮寫字)，其係用於通過IEEE 802.16標準之一致性及互操作性測試之產品的證明標誌。通訊晶片406可根據全球行動通訊系統(GSM)、通用封包無線電服務(GPRS)、通用行動電信系統(UMTS)、高速封包存取(HSPA)、演進型HSPA(E-HSPA)或LTE網路來操作。通訊晶片406可根據增強型GSM演進資料(EDGE)、GSM EDGE無線電存取網路(GERAN)、通用陸地無線電存取網路(UTRAN)或演進型UTRAN(E-UTRAN)來操作。通訊晶片406可根據分碼多重存取(CDMA)、分時多重存取(TDMA)、數位增強型無線電信(DECT)、演進資料最佳化(EV-DO)、其衍生物以及表示為3G、4G、5G及更高之任何其他無線協定來操作。通訊晶片406在其他實施例中可根據其他無線協定操作。
計算裝置400可包括多個通訊晶片406。舉例而言，第一通訊晶片406可專用於諸如WiGig、Wi-Fi及藍芽之較短距離無線通訊，且第二通訊晶片406可專用於諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、EV-DO及其他之較長距離無線通訊。
計算裝置400之處理器404可如本文中所描述地封裝體於一IC總成(例如，圖1之IC總成100或圖2a至圖2h之IC總成200)中。舉例而言，處理器404可為圖1的安裝於封裝體基體104上之第一晶粒102a。封裝體基體104及主機板 402可使用諸如焊球111之封裝體級互連件耦接在一起。可根據本文中所描述之實施例實施其他合適組態。術語「處理器」可指任何裝置或裝置之部分，其處理來自暫存器及/或記憶體之電子資料以將彼電子資料變換成可存儲於暫存器及/或記憶體中之其他電子資料。
通訊晶片406亦可包括可封裝體於如本文中所描述之IC總成(例如，圖1之IC總成100或圖2a至圖2h之IC總成200)中的晶粒(例如，RF晶粒)。在其他實施中，容納於計算裝置400內之另一組件(例如，記憶體裝置或其他積體電路裝置)可包括可封裝體於如本文中所描述之IC總成(例如，圖1之IC總成100或圖2a至圖2h之IC總成200)中的晶粒。
在各種實施中，計算裝置400可為膝上型電腦、迷你筆記型電腦、筆記型電腦、超級本、智慧型電話、平板電腦、個人數位助理(personal digital assistant，PDA)、超級行動PC、行動電話、桌上型電腦、伺服器、印表機、掃描儀、監視器、機上盒、娛樂控制單元、數位攝影機、攜帶型音樂播放器或數位視訊錄製器。計算裝置400在一些實施例中可為行動計算裝置。在其他實施中，計算裝置400可為處理資料之任何其他電子裝置。
實例
根據各種實施例，本發明描述一裝置(例如，一積體電路(IC)總成)。IC總成之實例1可包括：一封裝體基體，其具有一第一側面及與該第一側面對置安置之一第二側面；一第一晶粒，其具有與該封裝體基體之該第一側面 耦接之一作用側面及與該作用側面對置安置之一非作用側面，該第一晶粒具有經組配以在該第一晶粒與一第二晶粒之間路由電信號之一或多個矽穿孔(TSV)；以及一模複合物，其安置於該封裝體基體之該第一側面上，其中該模複合物與該第一晶粒的在該作用側面與該非作用側面之間之一側壁直接接觸且其中該第一側面與該模複合物的離該第一側面最遠之一終止邊緣之間的一距離等於或小於該第一晶粒之該非作用側面與該第一側面之間的一距離。實例2可包括實例1之IC總成，其中該模複合物之該終止邊緣與該晶粒之該非作用側面係實質上平面的。實例3可包括實例1之IC總成，其進一步包含該第二晶粒，其中該第二晶粒係以一覆晶組態安裝於該第一晶粒上。實例4可包括實例3之IC總成，其中該封裝體基體之該第一側面大體上界定一平面且該第二晶粒之至少一部分在平行於該平面之一方向上比該第一晶粒延伸更遠。實例5可包括實例4之IC總成，其中該第二晶粒至少部分地安裝於該模複合物之該終止邊緣上。實例6可包括實例5之IC總成，其進一步包含一環氧樹脂式薄膜，該環氧樹脂式薄膜在該第一晶粒與該第二晶粒之間安置於該第一晶粒之該非作用側面上且在該第二晶粒與該模複合物之該終止邊緣之間進一步安置於該模複合物之該終止邊緣上。實例7可包括實例6之IC總成，其中該第二晶粒具有與該第一晶粒耦接之一作用側面及與該作用側面對置安置之一非作用側面，該IC總成進一步包含一底部填充材料，該底部填充材料在該第二晶粒之該作用側面與 該非作用側面之間與該第二晶粒之一側壁直接接觸且進一步與該模複合物之該終止邊緣直接接觸。實例8可包括實例1至7中任一者之IC總成，其進一步包含穿過該模複合物形成之一或多個穿模互連件以及一積體電路(IC)裝置，該IC裝置經由該等一或多個穿模互連件與該封裝體基體之該第一側面耦接，其中該第一晶粒及該第二晶粒安置於該封裝體基體之該第一側面與該IC裝置之間。實例9可包括實例8之IC總成，其中該第一晶粒為一系統單晶片(SoC)晶粒，該第二晶粒為一記憶體晶粒，且該IC裝置為一記憶體封裝體。
根據各種實施例，本發明描述製造一IC總成之一方法。方法之實例10可包括：提供一封裝體基體，其具有一第一側面及與該第一側面對置安置之一第二側面；耦接一第一晶粒之一作用側面與該封裝體基體之該第一側面，該第一晶粒包括與該作用側面對置安置之一非作用側面及經組配以在該第一晶粒與一第二晶粒之間路由電信號之一或多個矽穿孔(TSV)；以及於該封裝體基體之該第一側面上形成一模複合物，其中該模複合物與該第一晶粒的在該作用側面與該非作用側面之間之一側壁直接接觸且其中該第一側面與該模複合物的離該第一側面最遠之一終止邊緣之間的一距離等於或小於該第一晶粒之該非作用側面與該第一側面之間的一距離。
實例11可包括實例10之方法，其中該模複合物之該終止邊緣與該晶粒之該非作用側面係實質上平面的。實例12可包括實例10之方法，其進一步包含以一覆晶組態耦 接該第二晶粒與該第一晶粒。實例13可包括實例12之方法，其中該封裝體基體之該第一側面大體上界定一平面且該第二晶粒之至少一部分在平行於該平面之一方向上比該第一晶粒延伸更遠。實例14可包括實例13之方法，其中該第二晶粒與該模複合物之該終止邊緣耦接。實例15可包括實例14之方法，其進一步包含沈積一環氧樹脂式薄膜，以使得該環氧樹脂式薄膜在該第一晶粒與該第二晶粒之間安置於該第一晶粒之該非作用側面上且在該第二晶粒與該模複合物之該終止邊緣之間進一步安置於該模複合物之該終止邊緣上。實例16可包括實例15之方法，其中該第二晶粒具有與該第一晶粒耦接之一作用側面及與該作用側面對置安置之一非作用側面，該方法進一步包含沈積一底部填充材料，該底部填充材料在該第二晶粒之該作用側面與該非作用側面之間與該第二晶粒之一側壁直接接觸且進一步與該模複合物之該終止邊緣直接接觸。實例17可包括實例10至16中任一者之方法，其進一步包含穿過該模複合物形成一或多個穿模互連件以及經由該等一或多個穿模互連件耦接一積體電路(IC)裝置與該封裝體基體之該第一側面，其中該第一晶粒及該第二晶粒安置於該封裝體基體之該第一側面與該IC裝置之間。實例18可包括實例17之方法，其中該第一晶粒為一系統單晶片(SoC)晶粒，該第二晶粒為一記憶體晶粒，且該IC裝置為一記憶體封裝體。
根據各種實施例，本發明可描述一系統(例如，一計算裝置)。計算裝置之實例19可包括一電路板以及與該 電路板耦接之一積體電路(IC)總成，該IC總成包含：一封裝體基體，其具有一第一側面及與該第一側面對置安置之一第二側面；一第一晶粒，其具有與該封裝體基體之該第一側面耦接之一作用側面及與該作用側面對置安置之一非作用側面，該第一晶粒具有經組配以在該第一晶粒與一第二晶粒之間路由電信號之一或多個矽穿孔(TSV)；以及一模複合物，其安置於該封裝體基體之該第一側面上，其中該模複合物與該第一晶粒的在該作用側面與該非作用側面之間之一側壁直接接觸且其中該第一側面與該模複合物的離該第一側面最遠之一終止邊緣之間的一距離等於或小於該第一晶粒之該非作用側面與該第一側面之間的一距離。實例20可包括實例19之計算裝置，其中該計算裝置為一行動計算裝置，其包括與該電路板耦接之以下各者中之一或多者：一顯示器、一觸控螢幕顯示器、一觸控螢幕控制器、一電池、一音訊編碼解碼器、一視訊編碼解碼器、一功率放大器、一全球定位系統(GPS)裝置、一羅盤、一蓋革計數器、一加速度計、一陀螺儀、一揚聲器或一攝影機。
各種實施例可包括上述實施例之任何合適組合，包括(及)在上文以聯合形式描述的實施例之替代(或)實施例(例如，「及」可為「及/或」)。此外，一些實施例可包括一或多個製品(例如，非暫時性電腦可讀媒體)，該等一或多個製品上儲存有在執行時產生上述實施例中之任一者之動作的指令。此外，一些實施例可包括具有用於進行上述實施例之各種操作之任何合適構件的裝置或系統。
所說明實施之以上描述(包括發明摘要中所描述之內容)不欲為詳盡的或將本發明之實施例限於所揭示之精確形式。雖然特定實施及實例出於說明之目的而在本文中描述，但如熟習相關技術者將認識到，各種等效修改在本文中之範疇內係可能的。
可根據以上詳細描述對本發明之實施例進行此等修改。以下申請專利範圍中所使用之術語不應解釋為將本發明之各種實施例限於本說明書及申請專利範圍中所揭示之特定實施。實情為，範疇應完全由以下技術方案判定，該等技術方案將根據技術方案解釋之已建立原則來解釋。
100‧‧‧積體電路(IC)總成
102a‧‧‧第一晶粒
102b‧‧‧第二晶粒
103‧‧‧側壁
104、104a‧‧‧封裝體基體
105‧‧‧晶粒間互連件
106‧‧‧阻焊層
107‧‧‧矽穿孔(TSV)
108‧‧‧模複合物
109‧‧‧晶粒級互連件
110‧‧‧環氧樹脂式薄膜
111‧‧‧焊球
112‧‧‧底部填充材料
113‧‧‧穿膜互連件
115‧‧‧可焊接材料
130a、130b、130c‧‧‧襯墊
132‧‧‧跡線
133、135‧‧‧方向
140‧‧‧IC裝置
D1、D2‧‧‧距離
E‧‧‧模複合物之終止邊緣
S1‧‧‧第一側面
S2‧‧‧第二側面

Claims (20)

  1. 一種積體電路(IC)總成，其包含：一封裝體基體，其具有一第一側面及與該第一側面對置配置之一第二側面；一第一晶粒，其具有與該封裝體基體之該第一側面耦接之一作用側面及與該作用側面對置配置之一非作用側面，該第一晶粒具有經組配以在該第一晶粒與一第二晶粒之間路由電氣信號之一或多個矽穿孔(TSV)；以及一模複合物，其配置於該封裝體基體之該第一側面上，其中該模複合物與該第一晶粒的在該作用側面與該非作用側面之間之一側壁直接接觸，且其中該第一側面與該模複合物的離該第一側面最遠之一終止邊緣之間的一距離係等於或小於該第一晶粒之該非作用側面與該第一側面之間的一距離。
  2. 如請求項1之IC總成，其中：該模複合物之該終止邊緣與該晶粒之該非作用側面係實質上平面的。
  3. 如請求項1之IC總成，其進一步包含：該第二晶粒，其中該第二晶粒係以一覆晶組態安裝於該第一晶粒上。
  4. 如請求項3之IC總成，其中：該封裝體基體之該第一側面大體上界定一平面；且 該第二晶粒之至少一部分在平行於該平面之一方向上比該第一晶粒延伸更遠。
  5. 如請求項4之IC總成，其中該第二晶粒至少部分地安裝於該模複合物之該終止邊緣上。
  6. 如請求項5之IC總成，其進一步包含：一環氧樹脂式薄膜，其在該第一晶粒與該第二晶粒之間配置於該第一晶粒之該非作用側面上，且進一步在該第二晶粒與該模複合物之該終止邊緣之間配置於該模複合物之該終止邊緣上。
  7. 如請求項6之IC總成，其中該第二晶粒具有與該第一晶粒耦接之一作用側面及與該作用側面對置配置之一非作用側面，該IC總成進一步包含：一底部填充材料，其在該第二晶粒之該作用側面與該非作用側面之間與該第二晶粒之一側壁直接接觸，且進一步與該模複合物之該終止邊緣直接接觸。
  8. 如請求項1之IC總成，其進一步包含：穿過該模複合物所形成之一或多個穿模互連件；以及一積體電路(IC)裝置，其經由該等一或多個穿模互連件與該封裝體基體之該第一側面耦接，其中該第一晶粒及該第二晶粒係配置於該封裝體基體之該第一側面與該IC裝置之間。
  9. 如請求項8之IC總成，其中：該第一晶粒為一系統單晶片(SoC)晶粒； 該第二晶粒為一記憶體晶粒；且該IC裝置為一記憶體封裝體。
  10. 一種方法，其包含：提供一封裝體基體，其具有一第一側面及相對於該第一側面配置之一第二側面；耦接一第一晶粒之一作用側面與該封裝體基體之該第一側面，該第一晶粒包括與該作用側面對置配置之一非作用側面，及經組配以在該第一晶粒與一第二晶粒之間路由電氣信號之一或多個矽穿孔(TSV)；以及於該封裝體基體之該第一側面上形成一模複合物，其中該模複合物與該第一晶粒的在該作用側面與該非作用側面之間之一側壁直接接觸，且其中該第一側面與該模複合物的離該第一側面最遠之一終止邊緣之間的一距離等於或小於該第一晶粒之該非作用側面與該第一側面之間的一距離。
  11. 如請求項10之方法，其中：該模複合物之該終止邊緣與該晶粒之該非作用側面係實質上平面的。
  12. 如請求項10之方法，其進一步包含：以一覆晶組態耦接該第二晶粒與該第一晶粒。
  13. 如請求項12之方法，其中：該封裝體基體之該第一側面大體上界定一平面；且該第二晶粒之至少一部分在平行於該平面之一方向上比該第一晶粒延伸更遠。
  14. 如請求項13之方法，其中該第二晶粒與該模複合物之該終止邊緣耦接。
  15. 如請求項14之方法，其進一步包含：沈積一環氧樹脂式薄膜，以使得該環氧樹脂式薄膜在該第一晶粒與該第二晶粒之間配置於該第一晶粒之該非作用側面上，且進一步在該第二晶粒與該模複合物之該終止邊緣之間配置於該模複合物之該終止邊緣上。
  16. 如請求項15之方法，其中該第二晶粒具有與該第一晶粒耦接之一作用側面，及與該作用側面對置配置之一非作用側面，該方法進一步包含：沈積一底部填充材料，該底部填充材料在該第二晶粒之該作用側面與該非作用側面之間與該第二晶粒之一側壁直接接觸，且進一步與該模複合物之該終止邊緣直接接觸。
  17. 如請求項10之方法，其進一步包含：穿過該模複合物形成一或多個穿模互連件；以及經由該等一或多個穿模互連件耦接一積體電路(IC)裝置與該封裝體基體之該第一側面，其中該第一晶粒及該第二晶粒係配置於該封裝體基體之該第一側面與該IC裝置之間。
  18. 如請求項17之方法，其中：該第一晶粒為一系統單晶片(SoC)晶粒；該第二晶粒為一記憶體晶粒；且該IC裝置為一記憶體封裝體。
  19. 一種計算裝置，其包含：一電路板；以及與該電路板耦接之一積體電路(IC)總成，該IC總成包含：一封裝體基體，其具有一第一側面及與該第一側面對置配置之一第二側面；一第一晶粒，其具有與該封裝體基體之該第一側面耦接之一作用側面，及與該作用側面對置配置之一非作用側面，該第一晶粒具有經組配以在該第一晶粒與一第二晶粒之間路由電氣信號之一或多個矽穿孔(TSV)；以及一模複合物，其配置於該封裝體基體之該第一側面上，其中該模複合物與該第一晶粒的在該作用側面與該非作用側面之間之一側壁直接接觸且其中該第一側面與該模複合物的離該第一側面最遠之一終止邊緣之間的一距離等於或小於該第一晶粒之該非作用側面與該第一側面之間的一距離。
  20. 如請求項19之計算裝置，其中：該計算裝置為包括與該電路板耦接之以下各者中之一或多者的一行動計算裝置：一顯示器、一觸控螢幕顯示器、一觸控螢幕控制器、一電池、一音訊編碼解碼器、一視訊編碼解碼器、一功率放大器、一全球定位系統(GPS)裝置、一羅盤、一蓋革計數器、一加速度計、一陀螺儀、一揚聲器或一攝影機。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101640076B1 (ko) * 2014-11-05 2016-07-15 앰코 테크놀로지 코리아 주식회사 웨이퍼 레벨의 칩 적층형 패키지 및 이의 제조 방법
WO2018034667A1 (en) * 2016-08-18 2018-02-22 Intel Corporation Systems and methods for improved through-silicon-vias
CN110024115B (zh) 2016-10-04 2024-02-02 天工方案公司 具有包覆模制结构的双侧射频封装
US11201066B2 (en) 2017-01-31 2021-12-14 Skyworks Solutions, Inc. Control of under-fill using a dam on a packaging substrate for a dual-sided ball grid array package
CN111052374B (zh) 2017-09-29 2024-08-20 英特尔公司 多级分布式钳位器
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
US11410902B2 (en) * 2019-09-16 2022-08-09 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
CN113782496A (zh) * 2020-06-10 2021-12-10 讯芯电子科技（中山）有限公司 半导体封装装置和半导体封装装置制造方法
US11791326B2 (en) * 2021-05-10 2023-10-17 International Business Machines Corporation Memory and logic chip stack with a translator chip

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4028211B2 (ja) 2001-11-01 2007-12-26 ローム株式会社 半導体装置
US20050224978A1 (en) * 2002-06-24 2005-10-13 Kohichiro Kawate Heat curable adhesive composition, article, semiconductor apparatus and method
US7262077B2 (en) * 2003-09-30 2007-08-28 Intel Corporation Capillary underfill and mold encapsulation method and apparatus
JP4016984B2 (ja) * 2004-12-21 2007-12-05 セイコーエプソン株式会社 半導体装置、半導体装置の製造方法、回路基板、及び電子機器
JP2006196657A (ja) * 2005-01-13 2006-07-27 New Japan Radio Co Ltd 半導体装置の製造方法
JP2007180529A (ja) 2005-12-02 2007-07-12 Nec Electronics Corp 半導体装置およびその製造方法
JP5044189B2 (ja) * 2006-10-24 2012-10-10 リンテック株式会社 複合型半導体装置の製造方法、及び複合型半導体装置
TWI414580B (zh) * 2006-10-31 2013-11-11 Sumitomo Bakelite Co 黏著帶及使用該黏著帶而成之半導體裝置
TWI335059B (en) * 2007-07-31 2010-12-21 Siliconware Precision Industries Co Ltd Multi-chip stack structure having silicon channel and method for fabricating the same
US7973416B2 (en) * 2008-05-12 2011-07-05 Texas Instruments Incorporated Thru silicon enabled die stacking scheme
US7960840B2 (en) * 2008-05-12 2011-06-14 Texas Instruments Incorporated Double wafer carrier process for creating integrated circuit die with through-silicon vias and micro-electro-mechanical systems protected by a hermetic cavity created at the wafer level
US8178976B2 (en) * 2008-05-12 2012-05-15 Texas Instruments Incorporated IC device having low resistance TSV comprising ground connection
US20090294028A1 (en) * 2008-06-03 2009-12-03 Nanochip, Inc. Process for fabricating high density storage device with high-temperature media
TWI573201B (zh) * 2008-07-18 2017-03-01 聯測總部私人有限公司 封裝結構性元件
US9559046B2 (en) 2008-09-12 2017-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-in package-on-package structure using through silicon vias
US7915080B2 (en) * 2008-12-19 2011-03-29 Texas Instruments Incorporated Bonding IC die to TSV wafers
TWI499024B (zh) * 2009-01-07 2015-09-01 Advanced Semiconductor Eng 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
US8012797B2 (en) * 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
KR20100095268A (ko) * 2009-02-20 2010-08-30 삼성전자주식회사 반도체 패키지 및 그 제조 방법
JP2011061004A (ja) 2009-09-10 2011-03-24 Elpida Memory Inc 半導体装置及びその製造方法
TWI392069B (zh) * 2009-11-24 2013-04-01 Advanced Semiconductor Eng 封裝結構及其封裝製程
US8288849B2 (en) * 2010-05-07 2012-10-16 Texas Instruments Incorporated Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint
US8378477B2 (en) * 2010-09-14 2013-02-19 Stats Chippac Ltd. Integrated circuit packaging system with film encapsulation and method of manufacture thereof
US8313982B2 (en) * 2010-09-20 2012-11-20 Texas Instruments Incorporated Stacked die assemblies including TSV die
KR20120031697A (ko) * 2010-09-27 2012-04-04 삼성전자주식회사 패키지 적층 구조 및 그 제조 방법
US20120080787A1 (en) * 2010-10-05 2012-04-05 Qualcomm Incorporated Electronic Package and Method of Making an Electronic Package
KR101740483B1 (ko) 2011-05-02 2017-06-08 삼성전자 주식회사 고정 부재 및 할로겐-프리 패키지간 연결부를 포함하는 적층 패키지
US9391046B2 (en) * 2011-05-20 2016-07-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming 3D semiconductor package with semiconductor die stacked over semiconductor wafer
US8623763B2 (en) * 2011-06-01 2014-01-07 Texas Instruments Incorporated Protective layer for protecting TSV tips during thermo-compressive bonding
US20130001710A1 (en) * 2011-06-29 2013-01-03 Invensense, Inc. Process for a sealed mems device with a portion exposed to the environment
KR101632249B1 (ko) * 2011-10-31 2016-07-01 인텔 코포레이션 멀티 다이 패키지 구조들

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US10580758B2 (en) 2020-03-03
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CN105917465A (zh) 2016-08-31
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