CN105917465A - 可缩放封装架构及相关技术和配置 - Google Patents

可缩放封装架构及相关技术和配置 Download PDF

Info

Publication number
CN105917465A
CN105917465A CN201480003745.1A CN201480003745A CN105917465A CN 105917465 A CN105917465 A CN 105917465A CN 201480003745 A CN201480003745 A CN 201480003745A CN 105917465 A CN105917465 A CN 105917465A
Authority
CN
China
Prior art keywords
tube core
package substrate
active side
molding composite
assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201480003745.1A
Other languages
English (en)
Other versions
CN105917465B (zh
Inventor
S·加内桑
B·齐亚德
N·尼姆卡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN105917465A publication Critical patent/CN105917465A/zh
Application granted granted Critical
Publication of CN105917465B publication Critical patent/CN105917465B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0381—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/28105—Layer connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. layer connectors on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H01L2224/29006—Layer connector larger than the underlying bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H01L2224/32058—Shape in side view being non uniform along the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/32105—Disposition relative to the bonding area, e.g. bond pad the layer connector connecting bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/3301—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/33104—Disposition relative to the bonding areas, e.g. bond pads
    • H01L2224/33106—Disposition relative to the bonding areas, e.g. bond pads the layer connectors being bonded to at least one common bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33183—On contiguous sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/809—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding with the bonding area not providing any mechanical bonding
    • H01L2224/80901—Pressing a bonding area against another bonding area by means of a further bonding area or connector
    • H01L2224/80903—Pressing a bonding area against another bonding area by means of a further bonding area or connector by means of a bump or layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00012—Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本公开的实施例描述了集成电路(IC)组件的可缩放封装架构及相关技术和配置。在一个实施例中，集成电路(IC)组件包括具有第一侧以及与第一侧相对设置的第二侧的封装衬底，具有与封装衬底的第一侧耦合的有源侧和与有源侧相对设置的非有源侧的第一管芯，第一管芯具有被配置为在第一管芯和第二管芯之间路由电信号的一个或多个穿硅通孔(TSV)，以及被置于封装衬底的第一侧上的模塑复合物，其中模塑复合物在有源侧和非有源侧之间与第一管芯的侧壁直接接触，而其中第一侧和距离第一侧最远的模塑复合物的终端边缘之间的距离等于或小于第一管芯的非有源侧和第一侧之间的距离。其他实施例可被描述和/或要求保护。

Description

可缩放封装架构及相关技术和配置
领域
本公开的实施例主要涉及集成电路(IC)组件领域，更具体而言，涉及可缩放封装架构及相关技术和配置。
背景
目前，新兴的集成电路(IC)组件可包括三维(3D)封装架构，其中一个或多个管芯(例如，存储器管芯)被堆叠在另一个管芯(例如，片上系统管芯)上。在一些配置中，被堆叠的管芯可悬垂于下层管芯，这可导致缺陷的风险，诸如堆叠管芯开裂。目前，下层管芯或悬垂管芯的尺寸收缩会不合需要地被限制以缓解该风险。此外，由于IC组件不断缩小至更小的尺寸，需要为更小的设备(诸如移动设备)提供更小的3D封装架构的Z高度。
附图说明
通过以下结合附图的详细说明将很容易理解实施例。为了方便描述，相同的参考数字表示相同的结构元素。以示例的方式，而不是以受限于附图的图形的方式示出实施例。
图1示意性地示出了根据一些实施例的示例集成电路(IC)组件的截面侧视图。
图2a-h示意性地示出了根据一些实施例的示例集成电路(IC)组件在不同的生产阶段期间的截面侧视图。
图3示意性地示出了根据一些实施例的集成电路(IC)组件生产方法的流程图。
图4示意性地示出了根据一些实施例的包括本文中所描述IC组件的计算设备。
详细说明
本公开的实施例描述了集成电路(IC)组件的可缩放封装架构及相关技术和配置。在以下的描述中，示意性实现方式中的各个方面采用本领域技术人员通常使用的术语进行描述，以向其他领域技术人员传达其工作的实质。然而，对于本领域的技术人员而言，本公开的实施例显然可以只用所述的某些方面进行实施。出于解释的目的，为了提供示意性实现方式的透彻理解，给出了具体的数字、材料和配置。然而，对于本领域的技术人员而言，本公开中的实施例显然无需具体细节亦可实施。在其他实例中，为了不模糊示例性实现方式，众所周知的特征被忽略或简化。
在以下的详细说明中，对于附图的引用构成详细说明的一部分，其中相同的数字始终表示相同的部分，且其中是以本公开的主题可被实施的示例实施例的方式示出。需要了解的是，在不背离本公开的范围的情况下，可运用其他实施例，且可做出结构性或逻辑性的改变。因此，以下详细说明不应被认为具有限制意义，并且实施例的范围由所附的权利要求及其等效项所界定。
对于本公开的目的，短语“A和/或B”是指(A)，(B)，或(A和B)。对于本公开的目的，短语“A，B，和/或C”是指(A)，(B)，(C)，(A和B)，(A和C)，(B和C)，或(A，B和C)。
描述可采用基于透视法的描述，如顶/底，内/外，上/下，等等。这些描述仅仅用来方便讨论，并不旨在将本文描述的实施例的应用限制在任何特定的方向。
描述可采用短语“在一种实施例中，”或“在实施例中，”，其可分别涉及相同或不同的实施例中的一个或多个。此外，关于本公开中的实施例所采用的术语“包括(comprising)，”“包含(including)，”“具有(having)，”等都是同义词。
术语“与……耦合(coupled with)，”连同其衍生物可被用于本文。“耦合(coupled)”可有以下的一个或多个含义。“耦合(coupled)”可表示两个或多个元素直接的物理或电气接触。然而，“耦合(coupled)”也可表示两个或多个元素间接地彼此接触，但仍然彼此协作或相互作用，还可表示一个或多个其他元素在所述与彼此耦合的元素之间进行耦合或连接。
在各种实施例中，短语“形成、沉积、或以其他方式置于第二特征之上的第一特征，”可表示第一特征形成、沉积、或置于第二特征之上，且第一特征的至少一部分可与第二特征的至少一部分直接接触(例如，直接的物理和/或电气接触)或间接接触(例如，有一个或多个其他特征在第一特征和第二特征之间)。
如本文中所使用的，述语“模块”可指，作为其部分，或包括专用集成电路(ASIC)、电子电路、片上系统(SoC)、处理器(共享的、专用的、或分组的)，和/或执行一个或多个软件或固件程序的存储器(共享的、专用的、或分组的)、组合逻辑电路、和/或提供所述功能的其他适合元件。
图1示意性地示出了根据一些实施例的示例集成电路(IC)组件100的截面侧视图。根据不同的实施例，IC组件100可代表三维(3D)封装架构，其中一个或多个管芯被堆叠在另一个管芯上。例如，在一些实施例中，第一管芯102a可与封装衬底104耦合，而第二管芯102b可被堆叠在第一管芯102a上。在一些实施例中，所绘的IC组件100可仅代表IC组件的一部分。
根据不同的实施例，IC组件100可包括具有第一侧S1和与第一侧S1相对设置的第二侧S2的封装衬底104。在一些实施例中，封装衬底104是具有芯和/或积层的基于环氧的层压衬底，诸如，例如Ajinomoto积层膜(ABF)衬底。在另一些实施例中，封装衬底104可以是电路板，例如，举例而言，采用任何合适的PCB技术形成的印刷电路板(PCB)。封装衬底104在其他实施例中可包括其他合适类型的衬底，包括，例如由玻璃、陶瓷、或半导体材料形成的衬底。
封装衬底104可包括被配置为从/向一个或多个管芯(例如，第一管芯102a)路由电信号(例如，举例而言，输入/输出(I/O)信号或电源/接地)的电气路由特征。电气路由特征可包括，例如，被置于封装衬底104的一个或多个表面上的焊盘130a、130b或迹线132和/或内部路由特征(未示出)，诸如，举例而言，导线、通孔、或路由电信号穿过封装衬底104的其他互连结构。例如，在所绘的实施例中，封装衬底104包括被配置为接收管芯102的管芯级互连109的焊盘130a(其也可被称为“陆地”)以及被配置为在第一侧S1上接收其他IC器件140的封装级互连(例如，穿模互连113)的焊盘130b。如可所见，在一些实施例中，阻焊层106可被置于封装衬底104的第一侧S1的外部表面上。内部路由特征或封装衬底104的迹线132可被配置为在第一管芯102a和/或第二管芯102b与一个或多个IC设备140的电气器件(例如，管芯)之间路由电信号。
一个或多个封装级互连，例如，举例而言，一个或多个焊球111，可在封装衬底104的第二侧S2上形成以便封装衬底104与其他电气器件(例如，举例而言，电路板(例如，图4中的主板402))耦合。尽管为避免模糊所绘实施例的方面而未被示出，焊球111可与置于封装衬底104的第二侧S2上对应的焊盘耦合。
第一管芯102a可与封装衬底104耦合。根据各种合适的配置，包括例如，如所绘制，以倒装芯片的配置与封装衬底104直接耦合，第一管芯102a可被附加于封装衬底104。在倒装芯片的配置中，包括有源电路的第一管芯102a的有源侧采用管芯级互连结构109(例如凸块、焊柱、或其他也可将第一管芯102a与封装衬底104耦合的合适结构)被附加到封装衬底的表面。非有源侧可与第一管芯102a的有源侧的相对设置。
在一些实施例中，第一管芯102a可包括一个或多个被配置为在第一管芯102a和与第一管芯102a耦合的第二管芯102b之间路由电信号的穿硅通孔(TSV)107。例如，TSV 107可将第一管芯102a的有源侧上的有源电路与管芯至管芯互连105(例如，凸块、焊柱、或其他将第二管芯102b与第一管芯102a耦合的合适结构)进行耦合。在所绘的实施例中，第二管芯102b的有源侧采用管芯至管芯互连105(其可与TSV 107电气耦合)以倒装芯片的配置被附加于第一管芯102a的非有源侧。
第一管芯102a和/或第二管芯102b可代表由采用诸如薄膜沉积、光刻、蚀刻等用于与形成互补型金属氧化物半导体(CMOS)器件相关的半导体生产技术从半导体材料(例如，硅)制成的分立产品。在一些实施例中，第一管芯和/或第二管芯102b可以是、包括处理器、存储器、片上系统(SoC)、或ASIC、或者作为其一部分。在一实施例中，第一管芯102a可代表SoC管芯，而第二管芯102b可代表存储器管芯。
根据不同的实施例，模塑复合物108可被形成于封装衬底104的第一侧S1上。模塑复合物108可由电气绝缘材料组成，诸如，举例而言，为密封和保护IC组件100的特征免受诸如潮湿或氧化的环境危害所形成的聚合物。如可见，在一些实施例中，模塑复合物108可在第一管芯102a的有源侧和非有源侧之间与第一管芯102a的侧壁103直接接触。
在一些实施例中，封装衬底104的第一侧S1和离第一侧S1最远的模塑复合物108的终端边缘E之间的距离D1可等于或小于封装衬底104的第一侧S1和第一管芯102a的非有源侧之间的距离D2。提供以该方式配置的模塑复合物108可允许第二管芯102b结合至模塑复合物108。例如，在所绘实施例中，第二管芯102可在平行于封装衬底104的第一侧S1大致界定的平面的方向上(例如，由箭头133所指)延伸至更远。另外，在所绘实施例中，模塑复合物108的终端边缘E是与第一管芯102a的非有源侧大体呈平面或齐平，从而使得第二管芯102b部分地被安装在模塑复合物108的终端边缘E上。由模塑复合物108提供的结构支撑可减少第二管芯102b的悬垂部分上的应力，这可减少诸如第二管芯102b开裂的缺陷，或可允许第一管芯102a和/或第二管芯102b的缩小尺寸，或允许第二管芯102b有更大的悬垂部分而不会开裂，或相对于不具有如所描述配置的模塑复合物108的IC组件允许IC组件Z高度的缩小(例如，由箭头135所指的方向)。
在另一些实施例中，第二管芯102b的至少部分可在平行于由第一侧S1所界定的平面的其他方向延伸，诸如，举例而言，图1所在页向内或向外，。在另一些实施例中，距离D1可小于D2，而另一中间材料可被置于第二管芯102b的悬垂部分和模塑复合物108之间，诸如，举例而言，环氧系材料(例如，环氧系膜110)或其他合适的材料。
在一些实施例中，环氧系膜110可在第一管芯102a和第二管芯102b之间被置于第一管芯102a的非有源侧上，并且在第二管芯102b和模塑复合物108的终端边缘E之间还被置于模塑复合物108的终端边缘E上。在一些实施例中，环氧系膜110，例如，可包括环氧助焊剂膜。
例如在所绘实施例中可见，在一些实施例中，底部填充材料112可在第二管芯102b的有源侧和非有源侧之间与第二管芯102b的侧壁直接接触或将其覆盖。底部填充材料112可被置于模塑复合物108的终端边缘上。底部填充材料112可被配置为保护第二管芯102b的边缘免受环境或操作危害。在一些实施例中，底部填充材料112可由环氧系材料或任意其他适合的材料组成。尽管未绘出，在另一些实施例中，底部填充材料可被置于第一管芯102a的有源侧和封装衬底104的第一侧S1而非模塑复合物108之间。
在一些实施例中，一个或多个穿模互连(TMI)113可穿过模塑复合物108形成以允许IC设备140与封装衬底104耦合。一个或多个TMI可包括穿过模塑复合物108形成的开口，其填充有导电材料诸如，举例而言，可焊接材料115。可焊接材料115，例如，可包括回流以在封装衬底上的焊盘130b和IC设备上的焊盘130c之间形成焊接点的一个或多个焊球。
IC设备140可表示各种合适的设备，例如，包括管芯或其他封装组件，诸如存储器封装。在所绘的实施例中，IC设备140包括封装衬底104a，其可与封装衬底104相关描述的实施例一致，以及形成于封装衬底104a上的阻焊层106。第一管芯102a和第二管芯102b可被置于封装衬底104的第一侧S1和IC设备140之间。在另一些实施例中，IC设备140可包括各种其他适合的配置。
图2a-h示意性地示出了根据一些实施例的示例集成电路(IC)组件200在不同的生产阶段期间的截面侧视图。IC组件200可与所描述的图1的IC组件100相关的实施例相一致，反之亦然。一些引用标记可能不在图2a-h的每个中重复，以避免模糊所描述的实施例的各方面。
参考图2a，在提供或生产封装衬底104之后的IC组件200被绘出。封装衬底104可包括，例如，如与图1的IC组件100相关所描述的与第二侧S2相对设置的第一侧、焊盘130a、130b、迹线132、阻焊层106、管芯级互连109和可焊接材料115。在一些实施例中，管芯级互连109可包括可控坍塌芯片连接(C4)的焊料，以及焊盘130b可被称为叠层封装(POP)陆地。
参考图2b，在以倒装芯片配置采用管芯级互连109将第一管芯102a的有源侧与封装衬底104的第一侧S1耦合之后的IC组件200被绘出。在另一些实施例中，管芯级互连109(例如，可焊接材料)可先于将第一管芯102与焊盘130a耦合而被置于第一管芯102a上。第一管芯102a可包括被配置为在第一管芯102a和第二管芯(例如图2e的第二管芯102b)之间路由电信号的一个或多个TSV 107以及形成于第一管芯102a的非有源侧上以接收用以将第二管芯与第一管芯102a耦合的管芯至管芯互连(诸如逻辑-存储器互连(LMI))的再分布特征105a，诸如焊盘和/或迹线，。
参考图2c，在封装衬底104的第一侧S1上形成模塑复合物108之后的IC组件200被示出。在一些实施例中，模塑复合物108可被形成至裸露的管芯模具(ExDM)，从而使得第一管芯102a的非有源侧保持裸露而模塑复合物108的终端边缘E相对于封装衬底的第一侧S1与第一管芯102a的非有源侧齐平或之下。模塑复合物108可例如，通过压缩或传递模塑、旋涂或滑涂(slickcoating)、层压或其他任何适合的技术进行沉积。
参考图2d，在将环氧系膜110沉积于第一管芯102a的非有源侧上之后的IC组件200被示出。在一些实施例中，环氧系膜110可进一步被沉积于模塑复合物108的终端边缘E上。在一些实施例中，环氧系膜110可包括助焊剂以便于第一管芯102a和将要被堆叠于第一管芯102a上的第二管芯之间电气连接的形成。在沉积环氧系膜110之前，再分布特征105a以及模塑复合物的终端边缘E可被清理。环氧系膜110可例如，通过分配环氧助焊剂或采用其他任何适合的方法附加上环氧助焊剂膜进行沉积。在另一些实施例中，除环氧系材料以外，适合的电气绝缘材料可被沉积于第一管芯102a上。
参考图2e，在将第二管芯102b以堆叠的倒装芯片配置与第一管芯102a耦合之后的IC组件200被绘出。第二管芯102b可采用，例如，热压结合以形成管芯至管芯互连105和/或环氧系膜110的原位固化来与第一管芯102a进行耦合。正如可见，底部填充材料112可被沉积与第二管芯102b的侧壁直接接触，并与模塑复合物108直接接触以在第二管芯102b的边缘形成保护屏障。底部填充材料112可例如，通过毛细管分配过程进行沉积。
参考图2f，在模塑复合物108中形成开口114以在焊盘130b上露出可焊接材料115作为形成TMI的部分(例如，图1的TMI 113)之后的IC组件200被绘出。在另一些实施例中，开口114可被形成以露出焊盘130b(例如，没有可焊接材料115可在焊盘130b上被露出)。开口114可以是，例如，由激光钻孔技术形成的激光通孔。在另一些实施例中，开口114可根据其他适合的技术被形成。
参考图2g，在施加助焊剂以及将可焊接材料115(例如，一个或多个焊球)置于开口114中以及回流可焊接材料以将可焊接材料115与已经在开口114中的可焊接材料或(如果没有可焊接材料已被置于焊盘130b上)与焊盘130b进行熔接之后的IC组件200被绘出。另外，在一些实施例中，一个或多个焊球111或其他封装级互连可在封装衬底104的第二侧S2上被附加或形成，以便于将封装衬底104与其他电气设备(例如，电路板)进行耦合。
参考图2h，在将IC设备140与封装衬底104的第一侧S1通过一个或多个TMI 113耦合之后的IC组件200被示出。在一些实施例中，IC设备140可以是具有封装衬底104a和一个或多个被置于封装衬底104a上存储器管芯102c的存储器封装。在一些实施例中，一个或多个存储器管芯102c可被封装于电气绝缘材料104b(诸如模塑复合物或层压材料或其他适合的结构)中。封装衬底104a上的焊盘130c可采用用可焊接材料115以形成焊接点的回流过程，与封装衬底104上对应的焊盘130b耦合。IC设备140可代表各种适合的IC设备，包括管芯、封装或其他合适的电气组件。
图3示意性地示出了根据一些实施例的集成电路(IC)组件生产方法300的流程图。方法300可与所描述的图1-2h相关的实施例相一致，反之亦然。
在302处，方法300可包括提供具有第一侧(例如，图2a中的S1)和与第一侧相对的第二侧(例如，图2a中的S2)的封装衬底(例如图2a中的封装衬底104)。
在304处，方法300可包括将第一管芯(例如，图2b中的第一管芯102a)的有源侧与封装衬底的第一侧耦合。第一管芯可包括一个或多个TSV(例如图2b中的TSV 107)并且可以以倒装芯片的配置被附加。
在306处，方法300可包括在封装衬底的第一侧上形成模塑复合物(例如，图2c中的模塑复合物108)。在一些实施例中，模塑复合物与第一管芯的侧壁(例如，图1中的侧壁103)直接接触。第一侧和距离第一侧最远的模塑复合物的终端边缘(例如，图1中的终端边缘E)之间的距离(例如，图1中的距离D1)可等于或小于第一管芯的非有源侧和封装衬底的第一侧之间的距离(例如，图1中的距离D2)。在一些实施例中，终端边缘可大体呈平面。
在308处，方法300可包括将第二管芯(例如，图2e中的第二管芯102b)以堆叠配置与第一管芯耦合。环氧系膜(例如，图2d中的环氧系膜110)可被沉积于第一管芯的非有源侧上以及模塑复合物的终端边缘上。第二管芯可通过热压，例如，采用管芯至管芯互连(例如，图2e中的管芯至管芯互连105)与第一管芯耦合。底部填充材料(例如，图2e中的底部填充材料112)可被沉积与第二管芯的侧壁直接接触以及在模塑复合物的终端边缘上。
在310处，方法300可包括穿过模塑复合物形成一个或多个穿模互连(TMI)(例如，图2h中的TMI 113)。TMI可例如，通过采用激光工艺穿过模塑复合物钻孔开口并用可焊接材料填充开口来形成。
在312处，方法300可包括将集成电路(IC)设备(例如，图2h中的IC设备140)通过一个或多个TMI与封装衬底的第一侧耦合。IC设备可采用焊接回流工艺以在TMI中的可焊接材料与IC设备和封装衬底上的各自焊盘之间形成节点，来与封装衬底进行耦合。
不同的操作作为多个分立的操作被依次以最有助于理解权利要求主题内容的方式进行描述。然而，描述的顺序不应被理解为暗示这些操作一定是与顺序相关的。
本公开中的实施例可在使用任何适合的硬件和/或软件以完成所需配置的系统中实现。图4根据一些实施例示意性地示出了包括如本文中所描述的IC组件(例如，图1中的IC组件100或图2a-h中的IC组件200)的计算设备400。计算设备400可容纳板，诸如主板402(例如，在外壳408内)。主板402可包括数个元件，包括但不限于处理器404和至少一个通信芯片406。处理器404可物理及电气地耦合至主板402。在一些实现中，所述的至少一个通信芯片406也可物理及电气藕接至所述主板402。在进一步的实现中，所述的通信芯片406可以是所述处理器404的一部分。
根据其应用，计算设备400可包括可以或可以不物理及电气连接至所述主板402的其他元件。这些其他元件可包括，但不限于，易失性存储器(例如DRAM)、非易失性存储器(例如ROM)、闪存、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)设备、罗盘、盖革计数器、加速度计、陀螺仪、扬声器、摄像机以及大容量存储设备(诸如硬盘驱动器、紧致盘(CD)、数字多功能盘(DVD)等)。
通信芯片406可实现对于去往和来自计算设备400的数据传输的无线通信。术语“无线”及其衍生可被用于描述电路、设备、系统、方法、技术、通信通道等，其可通过使用调制的电磁辐射经由非固体介质进行数据通信。上述术语并不表示相关设备不含有任何导线，尽管在一些实施例中，它们可能没有。通信芯片406可实现多种无线标准或协议中的任一种，包括但不限于诸种电气和电子工程师协会(IEEE)标准，其包括WiGig、Wi-Fi(IEEE802.11族)、IEEE 802.16标准(例如IEEE 802.16-2005年修订版)、长期演进(LTE)项目以及任何修订、更新、和/或修改(例如，先进LTE项目，超移动宽带(UMB)项目(又称“3GPP2”)等)。IEEE 802.16兼容的宽带无线接入(BWA)网络通常被称为WiMAX网络，即全球微波接入互通的缩写，这是一个通过了IEEE802.16标准一致性和互通性测试的产品认证标识。通信芯片406可依照全球移动通信系统(GSM)、通用分组无线业务(GPRS)、通用移动电信系统(UMTS)、高速分组接入(HSPA)、进化的HSPA(E-HSPA)或LTE网络进行操作。通信芯片406可依照GSM增强型数据演进(EDGE)、GSM EDGE无线接入网络(GERAN)、通用地面无线接入网络(UTRAN)、或演进型UTRAN(E-UTRAN)进行操作。通信芯片406可依照码分多址(CDMA)、时分多址(TDMA)、数字增强无绳电信(DECT)、演进数据优化(EV-DO)及其衍生项以及其他任何标为3G、4G、5G等的无线协议进行操作。所述通信芯片406在其他实施例中可依照其他无线协议进行操作。
所述的计算机设备400可包括多个通信芯片406。例如，第一通信芯片406可专用于短距离无线通信，例如WiGig，Wi-Fi和蓝牙，而第二通信芯片406可专用于长距离无线通信，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、EV-DO等。
如本文所描述的，计算设备400的处理器404可被封装在IC封装组件(例如，图1中的IC组件100或图2a-h中的IC组件200)中。例如，处理器404可以是安装于图1中封装衬底104上的第一管芯102a。封装衬底104和主板402可采用诸如焊球111的封装级互连被耦合在一起。其他适合的配置可根据本文中描述的实施例来实现。术语“处理器”可指处理来自寄存器和/或存储器的电子数据以将该电子数据转换成其他可被储存在寄存器和/或存储器中的电子数据的任何设备或设备的一部分。
通讯芯片406也可包括可被封装在IC组件(例如，图1中的IC组件100或图2a-h中的IC组件200)中的管芯(例如，RF管芯)。在进一步的实现中，另一个包含于计算设备400中的元件(例如，存储器设备或其他集成电路设备)可包括可被封装在如本文所描述的IC组件(例如，图1中的IC组件100或图2a-h中的IC组件200)中的管芯。
在不同的实现中，计算设备400可以是膝上型计算机、上网本、笔记本、超级本、智能电话、平板、个人数字助理(PDA)、超级移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数码相机、便携式音乐播放器、或数字录像机。在一些实施例中，计算设备400可以是移动计算设备。在进一步的实现中，计算设备400可以是处理数据的任何其他电子设备。
实例
根据不同的实施例，本公开描述了一种装置(例如，集成电路(IC)组件)。示例1中的IC组件可包括具有第一侧以及与第一侧相对设置的第二侧的封装衬底，具有与封装衬底的第一侧耦合的有源侧和与有源侧相对设置的非有源侧的第一管芯，所述第一管芯具有被配置为在所述第一管芯和第二管芯之间路由电信号的一个或多个穿硅通孔(TSV)，以及被置于所述封装衬底的所述第一侧上的模塑复合物，其中所述模塑复合物在所述有源侧和所述非有源侧之间与所述第一管芯的侧壁直接接触，而其中所述第一侧和距离所述第一侧最远的所述模塑复合物终端边缘之间的距离等于或小于所述第一管芯的所述非有源侧和所述第一侧之间的距离。示例2可包括示例1中的IC组件，其中模塑复合物的终端边缘与管芯的非有源侧大致呈平面。示例3可包括示例1中的IC组件，还包括第二管芯，其中第二管芯以倒装芯片配置安装在第一管芯上。示例4可包括示例3中的IC组件，其中封装衬底的第一侧大致限定平面，并且第二管芯的至少部分在平行于该平面的方向上比第一管芯延伸得更远。示例5可包括示例4中的IC组件，其中第二管芯至少部分地安装在模塑复合物的终端边缘上。示例6可包括示例5中的IC组件，还包括在第一管芯和第二管芯之间被置于第一管芯的非有源侧上的环氧系膜，并且在第二管芯和模塑复合物的终端边缘之间还被置于模塑复合物的终端边缘上。示例7可包括示例6中的IC组件，其中第二管芯具有与第一管芯耦合的有源侧以及与有源侧相对设置的非有源侧，IC组件还包括在第二管芯的有源侧和非有源侧之间与第二管芯的侧壁直接接触的底部填充材料，且还与模塑复合物的终端边缘直接接触。示例8可包括示例1-7中任一项的IC组件，还包括穿过模塑复合物形成的一个或多个穿模互连以及通过一个或多个穿模互连与封装衬底的第一侧耦合的集成电路(IC)设备，其中第一管芯和第二管芯被置于封装衬底的第一侧和IC器件之间。示例9可包括示例8中的IC组件，其中第一管芯是片上系统(SoC)管芯，第二管芯是存储器管芯，而IC设备是存储器封装。
根据不同的实施例，本公开描述了一种制作IC组件的方法。示例10中的方法可包括提供具有第一侧以及与第一侧相对设置的第二侧的封装衬底，将第一管芯的有源侧与封装衬底的第一侧耦合，第一管芯包括与有源侧相对设置的非有源侧以及被配置为在所述第一管芯和第二管芯之间路由电信号的一个或多个穿硅通孔(TSV)，以及在所述封装衬底的所述第一侧上形成模塑复合物，其中所述模塑复合物在所述有源侧和所述非有源侧之间与所述第一管芯的侧壁直接接触，而其中所述第一侧和距离所述第一侧最远的模塑复合物终端边缘之间的距离等于或小于所述第一管芯的所述非有源侧和所述第一侧之间的距离。
示例11可包括示例10中的方法，其中模塑复合物的终端边缘与管芯的非有源侧大致呈平面。示例12可包括示例10中的方法，还包括将第二管芯以倒装芯片配置与第一管芯耦合。示例13可包括示例12中的方法，其中封装衬底的第一侧大致限定平面，并且第二管芯的至少部分在平行于该平面的方向上比第一管芯延伸得更远。示例14可包括示例13中的方法，其中第二管芯与模塑复合物的终端边缘耦合。示例15可包括示例14中的方法，还包括沉积环氧系膜以使环氧系膜在第一管芯和第二管芯之间被置于第一管芯的非有源侧上，并且在第二管芯和模塑复合物的终端边缘之间还被置于模塑复合物的终端边缘上。示例16可包括示例15中的方法，其中第二管芯具有与第一管芯耦合的有源侧以及与有源侧相对设置的非有源侧，IC组件还包括沉积在第二管芯的有源侧和非有源侧之间与第二管芯的侧壁直接接触且还与模塑复合物的终端边缘直接接触的底部填充材料。示例17可包括示例10-16中任一项的方法，还包括穿过模塑复合物形成一个或多个穿模互连以及通过一个或多个穿模互连将集成电路(IC)设备与封装衬底的第一侧耦合，其中第一管芯和第二管芯被置于封装衬底的第一侧和IC器件之间。示例18可包括示例17中的方法，其中第一管芯是片上系统(SoC)管芯，第二管芯是存储器管芯，而IC设备是存储器封装。
根据不同的实施例，本公开描述一种系统(例如，一种计算设备)。示例19中的计算设备可包括电路板和与电路板耦合的集成电路(IC)组件，IC组件包括具有第一侧以及与第一侧相对设置的第二侧的封装衬底，具有与封装衬底的第一侧耦合的有源侧和与有源侧相对设置的非有源侧的第一管芯，所述第一管芯具有一个或多个被配置为在所述第一管芯和第二管芯之间路由电信号的穿硅通孔(TSV)，以及被置于所述封装衬底的所述第一侧上的模塑复合物，其中所述模塑复合物在所述有源侧和所述非有源侧之间与所述第一管芯的侧壁直接接触，而其中所述第一侧和距离所述第一侧最远的所述模塑复合物终端边缘之间的距离等于或小于所述第一管芯的所述非有源侧和所述第一侧之间的距离。示例20可包括示例19中的计算设备，其中计算设备是包括与电路板耦合的显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)设备、罗盘、盖革计数器、加速度计、陀螺仪、扬声器或相机中的一个或多个的移动计算设备。
不同的实施例可包括上述实施例任意合适的组合，包括上述以结合的形式(和)描述的实施例中的替代(或)实施例，例如“和”可以是“和/或”。此外，一些实施例可包括一个或多个具有被执行时会引起任意上述实施例动作、储存于其上的指令的制品，例如非暂时性计算机可读介质。另外，一些实施例可包括具有用以执行上述实施例中各种不同操作的任意合适的方法的装置或系统。
以上示例性实现的描述，包括摘要中的描述，并非意于将本公开中的实施例穷举或限制于所公开的确切形式。由于具体的实现方式和实例在此以示意性的目的被描述，相关领域技术人员会意识到，在本公开范围内的各种不同的等效修改都是可能的。
根据以上的详细说明，这些修改可在本公开的实施例中进行。在以下权利要求中的术语不应被解释为将本公开中各种不同的实施例限制于说明书和权利要求中所公开的特定的实现方式。相反，范围完全是由以下的权利要求来确定，其应根据权利范围解读中确立的规则进行解释。

Claims (20)

1.一种集成电路(IC)组件包括：
封装衬底，所述封装衬底具有第一侧以及与第一侧相对设置的第二侧；
第一管芯，所述第一管芯具有与封装衬底的第一侧耦合的有源侧，以及与有源侧相对设置的非有源侧，所述第一管芯具有被配置为在所述第一管芯和第二管芯之间路由电信号的一个或多个穿硅通孔(TSV)；以及
模塑复合物，所述模塑复合物被置于所述封装衬底的所述第一侧上，其中所述模塑复合物在所述有源侧和所述非有源侧之间与所述第一管芯的侧壁直接接触，而其中所述第一侧和距离所述第一侧最远的所述模塑复合物的终端边缘之间的距离等于或小于所述第一管芯的所述非有源侧和所述第一侧之间的距离。
2.如权利要求1所述的IC组件，其中：
所述模塑复合物的所述终端边缘与所述管芯的所述非有源侧大致呈平面。
3.如权利要求1所述的IC组件，还包括：
所述第二管芯，其中所述第二管芯以倒装芯片的配置安装在所述第一管芯上。
4.如权利要求3所述的IC组件，其中：
所述封装衬底的所述第一侧大体限定平面；并且
所述第二管芯的至少一部分相比所述第一管芯在与所述平面平行的方向上延伸得更远。
5.如权利要求4所述的IC组件，其中所述第二管芯至少部分地安装在所述模塑复合物的所述终端边缘上。
6.如权利要求5所述的IC组件，还包括：
环氧系膜，所述环氧系膜在所述第一管芯和所述第二管芯之间被置于所述第一管芯的所述非有源侧上，并且在所述第二管芯和所述模塑复合物的所述终端边缘之间还被置于所述模塑复合物的所述终端边缘上。
7.如权利要求6所述的IC组件，其中所述第二管芯具有与所述第一管芯耦合的有源侧以及与所述有源侧相对设置的非有源侧，所述IC组件还包括：
底部填充材料，所述底部填充材料在所述第二管芯的所述有源侧和所述非有源侧之间与所述第二管芯的侧壁直接接触，并且还与所述模塑复合物的所述终端边缘直接接触。
8.如权利要求1-7中任一项所述的IC组件，还包括：
一个或多个穿模互连，所述穿模互连穿过所述模塑复合物而形成；以及
集成电路(IC)器件，所述集成电路器件通过一个或多个穿模互连与所述封装衬底的所述第一侧耦合，其中所述第一管芯和所述第二管芯被置于所述封装衬底的所述第一侧和所述IC器件之间。
9.如权利要求8所述的IC组件，其中：
所述第一管芯是片上系统(SoC)管芯；
所述第二管芯是存储器管芯；以及
所述IC器件是存储器封装。
10.一种方法，包括：
提供具有第一侧以及与第一侧相对设置的第二侧的封装衬底；
将第一管芯的有源侧与所述封装衬底的所述第一侧耦合，所述第一管芯包括与所述有源侧相对设置的非有源侧和被配置为在所述第一管芯和第二管芯之间路由电信号的一个或多个穿硅通孔(TSV)；以及
在所述封装衬底的所述第一侧上形成模塑复合物，其中所述模塑复合物在所述有源侧和所述非有源侧之间与所述第一管芯的侧壁直接接触，而其中所述第一侧和距离所述第一侧最远的所述模塑复合物的终端边缘之间的距离等于或小于所述第一管芯的所述非有源侧和所述第一侧之间的距离。
11.如权利要求10所述的方法，其中：
所述模塑复合物的所述终端边缘与所述管芯的所述非有源侧大致呈平面。
12.如权利要求10中的方法，还包括：
将所述第二管芯以倒装芯片的配置与所述第一管芯耦合。
13.如权利要求12所述的方法，其中：
所述封装衬底的所述第一侧大体限定平面；并且
所述第二管芯的至少一部分相比所述第一管芯在与所述平面平行的方向上延伸得更远。
14.如权利要求13所述的方法，其中所述第二管芯与所述模塑复合物的所述终端边缘耦合。
15.如权利要求14中的方法，还包括：
沉积环氧系膜，以使所述环氧系膜在所述第一管芯和所述第二管芯之间被置于所述第一管芯的所述非有源侧上，并且在所述第二管芯和所述模塑复合物的所述终端边缘之间还被置于所述模塑复合物的所述终端边缘上。
16.如权利要求15所述的方法，其中所述第二管芯具有与所述第一管芯耦合的有源侧以及与所述有源侧相对设置的非有源侧，所述方法还包括：
沉积底部填充材料，以在所述第二管芯的所述有源侧和所述非有源侧之间与所述第二管芯的侧壁直接接触，并且还与所述模塑复合物的所述终端边缘直接接触。
17.如权利要求10-16中任一项所述的方法，还包括：
穿过所述模塑复合物形成一个或多个穿模互连；以及
将集成电路(IC)器件通过一个或多个穿模互连与所述封装衬底的所述第一侧耦合，其中所述第一管芯和所述第二管芯被置于所述封装衬底的所述第一侧和所述IC器件之间。
18.如权利要求17所述的方法，其中：
所述第一管芯是片上系统(SoC)管芯；
所述第二管芯是存储器管芯；以及
所述IC器件是存储器封装。
19.一种计算设备包括：
电路板；以及
集成电路(IC)组件，所述IC组件与所述电路板耦合，所述IC组件包括：
封装衬底，所述封装衬底具有第一侧以及与第一侧相对设置的第二侧；
第一管芯，所述第一管芯具有与封装衬底的第一侧耦合的有源侧以及与有源侧相对设置的非有源侧，所述第一管芯具有被配置为在所述第一管芯和第二管芯之间路由电信号的一个或多个穿硅通孔(TSV)；以及
模塑复合物，所述模塑复合物被置于所述封装衬底的所述第一侧上，其中所述模塑复合物在所述有源侧和所述非有源侧之间与所述第一管芯的侧壁直接接触，而其中所述第一侧和距离所述第一侧最远的所述模塑复合物的终端边缘之间的距离等于或小于所述第一管芯的所述非有源侧和所述第一侧之间的距离。
20.如权利要求19所述的计算设备，其中：
所述计算设备是包括与电路板耦合的显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)设备、罗盘、盖革计数器、加速度计、陀螺仪、扬声器或相机中的一个或多个的移动计算设备。
CN201480003745.1A 2014-07-11 2014-07-11 可缩放封装架构及相关技术和配置 Active CN105917465B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2014/046417 WO2016007176A1 (en) 2014-07-11 2014-07-11 Scalable package architecture and associated techniques and configurations

Publications (2)

Publication Number Publication Date
CN105917465A true CN105917465A (zh) 2016-08-31
CN105917465B CN105917465B (zh) 2019-11-19

Family

ID=55064634

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480003745.1A Active CN105917465B (zh) 2014-07-11 2014-07-11 可缩放封装架构及相关技术和配置

Country Status (7)

Country Link
US (3) US9793244B2 (zh)
EP (1) EP3167485A4 (zh)
JP (1) JP2016526306A (zh)
KR (1) KR102108608B1 (zh)
CN (1) CN105917465B (zh)
TW (1) TWI614847B (zh)
WO (1) WO2016007176A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI763056B (zh) * 2020-06-10 2022-05-01 大陸商訊芯電子科技(中山)有限公司 半導體封裝裝置和半導體封裝裝置製造方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101640076B1 (ko) * 2014-11-05 2016-07-15 앰코 테크놀로지 코리아 주식회사 웨이퍼 레벨의 칩 적층형 패키지 및 이의 제조 방법
WO2018034667A1 (en) * 2016-08-18 2018-02-22 Intel Corporation Systems and methods for improved through-silicon-vias
CN110024115B (zh) 2016-10-04 2024-02-02 天工方案公司 具有包覆模制结构的双侧射频封装
US11201066B2 (en) 2017-01-31 2021-12-14 Skyworks Solutions, Inc. Control of under-fill using a dam on a packaging substrate for a dual-sided ball grid array package
WO2019066976A1 (en) * 2017-09-29 2019-04-04 Intel Corporation MULTINIVE DISTRIBUTED CLAMPS
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
US11410902B2 (en) * 2019-09-16 2022-08-09 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11791326B2 (en) * 2021-05-10 2023-10-17 International Business Machines Corporation Memory and logic chip stack with a translator chip

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110121442A1 (en) * 2009-11-24 2011-05-26 Advanced Semiconductor Engineering, Inc. Package structure and package process
US20120070939A1 (en) * 2010-09-20 2012-03-22 Texas Instruments Incorporated Stacked die assemblies including tsv die

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4028211B2 (ja) * 2001-11-01 2007-12-26 ローム株式会社 半導体装置
US20050224978A1 (en) * 2002-06-24 2005-10-13 Kohichiro Kawate Heat curable adhesive composition, article, semiconductor apparatus and method
US7262077B2 (en) * 2003-09-30 2007-08-28 Intel Corporation Capillary underfill and mold encapsulation method and apparatus
JP4016984B2 (ja) * 2004-12-21 2007-12-05 セイコーエプソン株式会社 半導体装置、半導体装置の製造方法、回路基板、及び電子機器
JP2006196657A (ja) * 2005-01-13 2006-07-27 New Japan Radio Co Ltd 半導体装置の製造方法
JP2007180529A (ja) * 2005-12-02 2007-07-12 Nec Electronics Corp 半導体装置およびその製造方法
JP5044189B2 (ja) * 2006-10-24 2012-10-10 リンテック株式会社 複合型半導体装置の製造方法、及び複合型半導体装置
TWI414580B (zh) 2006-10-31 2013-11-11 Sumitomo Bakelite Co 黏著帶及使用該黏著帶而成之半導體裝置
TWI335059B (en) * 2007-07-31 2010-12-21 Siliconware Precision Industries Co Ltd Multi-chip stack structure having silicon channel and method for fabricating the same
US7960840B2 (en) * 2008-05-12 2011-06-14 Texas Instruments Incorporated Double wafer carrier process for creating integrated circuit die with through-silicon vias and micro-electro-mechanical systems protected by a hermetic cavity created at the wafer level
US8178976B2 (en) * 2008-05-12 2012-05-15 Texas Instruments Incorporated IC device having low resistance TSV comprising ground connection
US7973416B2 (en) * 2008-05-12 2011-07-05 Texas Instruments Incorporated Thru silicon enabled die stacking scheme
US20090294028A1 (en) * 2008-06-03 2009-12-03 Nanochip, Inc. Process for fabricating high density storage device with high-temperature media
US8384203B2 (en) * 2008-07-18 2013-02-26 United Test And Assembly Center Ltd. Packaging structural member
US9559046B2 (en) 2008-09-12 2017-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-in package-on-package structure using through silicon vias
US7915080B2 (en) * 2008-12-19 2011-03-29 Texas Instruments Incorporated Bonding IC die to TSV wafers
US8012797B2 (en) * 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
TWI499024B (zh) * 2009-01-07 2015-09-01 Advanced Semiconductor Eng 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
KR20100095268A (ko) * 2009-02-20 2010-08-30 삼성전자주식회사 반도체 패키지 및 그 제조 방법
JP2011061004A (ja) 2009-09-10 2011-03-24 Elpida Memory Inc 半導体装置及びその製造方法
US8288849B2 (en) * 2010-05-07 2012-10-16 Texas Instruments Incorporated Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint
US8378477B2 (en) * 2010-09-14 2013-02-19 Stats Chippac Ltd. Integrated circuit packaging system with film encapsulation and method of manufacture thereof
KR20120031697A (ko) * 2010-09-27 2012-04-04 삼성전자주식회사 패키지 적층 구조 및 그 제조 방법
US20120080787A1 (en) * 2010-10-05 2012-04-05 Qualcomm Incorporated Electronic Package and Method of Making an Electronic Package
KR101740483B1 (ko) * 2011-05-02 2017-06-08 삼성전자 주식회사 고정 부재 및 할로겐-프리 패키지간 연결부를 포함하는 적층 패키지
US8623763B2 (en) * 2011-06-01 2014-01-07 Texas Instruments Incorporated Protective layer for protecting TSV tips during thermo-compressive bonding
US20130001710A1 (en) * 2011-06-29 2013-01-03 Invensense, Inc. Process for a sealed mems device with a portion exposed to the environment

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110121442A1 (en) * 2009-11-24 2011-05-26 Advanced Semiconductor Engineering, Inc. Package structure and package process
US20120070939A1 (en) * 2010-09-20 2012-03-22 Texas Instruments Incorporated Stacked die assemblies including tsv die

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI763056B (zh) * 2020-06-10 2022-05-01 大陸商訊芯電子科技(中山)有限公司 半導體封裝裝置和半導體封裝裝置製造方法

Also Published As

Publication number Publication date
KR20170005083A (ko) 2017-01-11
US20160260690A1 (en) 2016-09-08
US10037976B2 (en) 2018-07-31
US20180005997A1 (en) 2018-01-04
JP2016526306A (ja) 2016-09-01
EP3167485A4 (en) 2018-03-07
WO2016007176A1 (en) 2016-01-14
EP3167485A1 (en) 2017-05-17
TWI614847B (zh) 2018-02-11
US10580758B2 (en) 2020-03-03
US9793244B2 (en) 2017-10-17
CN105917465B (zh) 2019-11-19
KR102108608B1 (ko) 2020-05-07
US20180331075A1 (en) 2018-11-15
TW201606955A (zh) 2016-02-16

Similar Documents

Publication Publication Date Title
CN105917465A (zh) 可缩放封装架构及相关技术和配置
TWI657557B (zh) 具有打線結合的多晶粒堆疊的積體電路封裝
CN104900626B (zh) 管芯到管芯接合以及相关联的封装构造
CN104517953B (zh) 用于无源部件的具有叠置体基板的管芯封装
TWI727947B (zh) 用於堆疊式封裝之帶有凹入式傳導接點的積體電路結構
CN104733436B (zh) 具有嵌入式桥的集成电路封装
TWI710036B (zh) 用以互連封裝積體電路晶粒之方法及裝置
JP6859269B2 (ja) パッケージ構造にトレンチを形成する方法及びこの方法により形成された構造
JP6130880B2 (ja) キャプダクタアセンブリに関連する技術及び構成
TWI585931B (zh) 用於多晶粒之封裝總成組態及相關技術
TW201705401A (zh) 多層封裝技術
TWI582927B (zh) 積體電路封裝技術及用於小形狀因數或穿戴式裝置之組態
CN106133905A (zh) 集成电路封装衬底
TW201545319A (zh) 多裝置可撓電子系統單晶片（ｓｏｃ）的製程整合技術
US20170092618A1 (en) Package topside ball grid array for ultra low z-height
US20240071948A1 (en) Semiconductor package with stiffener basket portion

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant