CN106133905A - 集成电路封装衬底 - Google Patents
集成电路封装衬底 Download PDFInfo
- Publication number
- CN106133905A CN106133905A CN201480077398.7A CN201480077398A CN106133905A CN 106133905 A CN106133905 A CN 106133905A CN 201480077398 A CN201480077398 A CN 201480077398A CN 106133905 A CN106133905 A CN 106133905A
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- tube core
- hip
- electrically insulating
- insulating material
- density
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- G06—COMPUTING; CALCULATING OR COUNTING
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Abstract
本公开内容的实施例涉及用于设计并组装能够适于若干不同封装构造的管芯的技术和构造。在一个实施例中,集成电路(IC)管芯可以包括半导体衬底。所述管芯还可以包括:设置在所述半导体衬底上的电绝缘材料;设置在所述电绝缘材料中的多个电布线特征体,用于使电信号穿过所述电绝缘材料来进行传输;以及设置在所述电绝缘材料的表面中的多个金属特征体。在实施例中,所述多个金属特征体可以与所述多个电布线特征体电耦合。此外,所述多个金属特征体可以具有被设计为使所述管芯能够与多种不同封装构造集成的输入/输出(I/O)密度。可以描述和/或主张其他实施例。
Description
技术领域
本公开内容的实施例总体上涉及集成电路领域,并且更具体而言,涉及用于将管芯与不同封装构造集成的技术和构造。
背景技术
在很多情况下,一种集成电路(IC)管芯设计可以用于多种市场细分。这些市场细分中的每一个可以具有与它们相关联的不同成本目标。然而,在当前现有技术中,IC管芯可能限制于用于单个封装或电路板构造中。因为IC管芯可能限制于单个封装或电路板构造,所以与在多种市场细分中利用管芯相关联的成本可能需要包括利用为其设计管芯的封装或电路板构造的成本。结果,满足更低成本市场细分的裕度可能是困难的。
本文提供的背景技术描述用于总体上呈现本公开内容的上下文的目的。除非在本文中另行指出,否则在本节中描述的材料不是本申请中权利要求的现有技术,并且不会通过包括在本节中而被纳入现有技术中。
附图说明
通过以下具体实施方式并结合附图,将容易理解实施例。为了方便本描述,相似的附图标记指示相似的结构元件。通过举例而非限制的方式,在附图的各图中示出了实施例。
图1示意性地示出了根据本公开内容的各种实施例的示例性集成电路(IC)组件的截面侧视图。
图2是根据本公开内容的各种实施例的IC芯片设计过程一部分的例示性流程图。
图3是根据本公开内容的各种实施例的在多种构造中实施的单个管芯的例示性视图。
图4是根据本公开内容的各种实施例的管芯组装过程的例示性流程图。
图5是根据本公开内容的各种实施例的在管芯组装过程中所选择的程序的例示性截面视图。
图6是适于示例性封装构造的管芯的例示性截面视图。
图7是根据本公开内容的实施例的利用管芯的组装过程的例示性流程图。
图8示意性地示出了根据一些实施例的包括具有双表面抛光的封装衬底的计算装置。
具体实施方式
本公开内容的实施例描述用于对能够适于若干不同的封装构造的集成电路管芯进行组装的技术和构造。在以下描述中,将使用本领域技术人员在向本领域其他技术人员传达他们工作的实质时通常所采用的术语来描述例示性实施方式的各个方面。然而,对于本领域的技术人员而言显而易见的是,可以仅利用所述方面中的一些方面来实践本公开内容的实施例。出于解释的目的,阐述了具体的数字、材料和构造以便提供对例示性实施方式的透彻理解。然而,对于本领域技术人员显而易见的是,可以无需具体细节来实践本公开内容的实施例。在其他实例中,省略或简化了公知的特征,以便不使例示性实施方式难以理解。
在以下具体实施方式中,参考了形成其一部分的附图,其中,相似的附图标记在所有图中指示相似的部分,并且其中,通过例示的方式示出了可以实践本公开内容的主题的实施例。要理解,可以利用其他实施例并且可以做出结构或逻辑上的改变而不脱离本公开内容的范围。因此,不应以限制性意义理解以下具体实施方式,并且实施例的范围由所附权利要求及其等同物来限定。
出于本公开内容的目的,短语“A和/或B”表示(A)、(B)或(A和B)。出于本公开内容的目的,短语“A、B和/或C”表示(A)、(B)、(C)、(A和B)、(A和C)、(B和C)或(A、B和C)。
描述可以使用基于透视图的描述,例如顶部/底部、内/外、上方/下方等。这样的描述仅仅用于方便论述,并非要将本文所述实施例的应用限制到任何特定取向。
本描述可以使用短语“在一实施例中”或“在实施例中”,它们均可以指一个或多个相同或不同的实施例。此外,如关于本公开内容的实施例所用的,术语“包括”、“具有”等是同义的。
本文中可以使用术语“与……耦合”连同其派生词。“耦合”可以表示如下一个或多个。“耦合”可以表示两个或更多元件直接物理或电接触。然而,“耦合”也可以表示两个或更多元件间接彼此接触,但仍然彼此合作或交互,并可以表示一个或多个其他元件耦合或连接于被说成彼此耦合的元件之间。术语“直接耦合”可以表示两个或更多元件直接接触。
在各实施例中,短语“第一特征形成、沉积或以其他方式设置于第二特征上”可以表示第一特征形成、沉积或设置于第二特征上方,并且第一特征的至少一部分可以与第二特征的至少一部分直接接触(例如,直接物理和/或电接触)或间接接触(例如,在第一特征和第二特征之间具有一个或多个其他特征)。
如本文中所使用的,术语“模块”可以指代、或包括执行一个或多个软件或固件程序的专用集成电路(ASIC)、电子电路、芯片上系统(SoC)、处理器(共享、专用或组)和/或存储器(共享、专用或组)、组合逻辑电路、和/或提供所述功能的其他适当的部件,或者是其部分。
图1示意性地示出了示例性集成电路(IC)组件100的截面侧视图。在一些实施例中,可以看出,IC组件100可以包括与封装衬底104电和/或物理耦合的一个或多个管芯(例如,IC管芯102)。可以看出,封装衬底104还可以与电路板122电耦合。
管芯102从硅衬底开始可以包括若干层116,直到使得管芯102能够适于多种封装技术中的选定的封装技术的这些封装技术所共有的最后层。为了完成这个目标,可以在层116上设置一个或多个分布层118,分布层118被配置成使管芯102能够适于多种封装技术中的选定的一种,例如封装衬底104。可以根据多种适当构造,包括如所描绘的倒装芯片构造或、其他构造(例如,被嵌入在封装衬底104中或在丝焊布置中被配置),将管芯102附接到封装衬底104。在倒装芯片构造中,管芯102可以经由管芯互连结构106(例如凸起、柱、或者还可以将管芯102与封装衬底104电耦合的其他适当结构)而附接到封装衬底104的表面。
管芯102可以代表由半导体材料制造的分立芯片,并且在一些实施例中,可以包括处理器、存储器或ASIC或是其一部分。在一些实施例中,诸如模制化合物或底部填充材料(未示出)等电绝缘材料可以部分包封管芯102和/或互连结构106的一部分。管芯互连结构106可以被配置成在管芯102和封装衬底104之间传输电信号。
封装衬底104可以包括被配置成来往于管芯102传输电信号的电布线特征体。例如,电布线特征体可以包括设置于封装衬底104的一个或多个表面上的迹线和/或内部布线特征体,例如,沟槽、通孔或其他互连结构,以使电信号穿过封装衬底104进行传输。例如,在一些实施例中,封装衬底104可以包括被配置成接收管芯互连结构106并在管芯102和封装衬底104之间传输电信号的电布线特征体(例如,管芯接合焊盘108)。
在一些实施例中,封装衬底104是具有内核和/或堆积层的基于环氧树脂的层压衬底,例如,Ajinomoto堆积膜(ABF)衬底。在其他实施例中,封装衬底104可以包括其他适当类型的衬底,例如,包括由玻璃、陶瓷或半导体材料形成的衬底。
电路板122可以是由诸如环氧层压材料等电绝缘材料构成的印刷电路板(PCB)。例如,电路板12可以包括由诸如特氟隆的材料、酚醛棉纸材料(例如,阻燃剂4(FR-4)、FR-1、棉纸)、以及环氧树脂材料(例如,CEM-1或CEM-3)或使用环氧树脂预浸渍材料而层压在一起的玻璃织物材料构成的电绝缘层。可以通过电绝缘层形成例如通孔的结构(未示出)以通过电路板122传输管芯102的电信号。在其他实施例中,电路板122可以由其他适当材料构成。在一些实施例中,电路板122为母板(例如,图8的母板802)。
封装级互连(例如,焊球112或连接盘栅格阵列(LGA)结构)可以耦合到封装衬底104上的一个或多个连接盘(下文称为“连接盘110”)和电路板122上的一个或多个焊盘114,以形成对应的焊接接头,焊接接头被配置成进一步将电信号传输到封装衬底104和电路板122之间。在其他实施例中可以使用用以将封装衬底104与电路板122物理和/或电耦合的其他适当技术。
图2是根据本公开内容的各种实施例的管芯设计过程的一部分的例示性流程图。过程200可以开始于块201,其中,可以选择可以与IC管芯集成的若干不同的封装技术。如本文中使用的,除非上下文中清楚做出其他说明,否则可以同义地使用封装技术和封装构造。在图3的块302-310中示出了适于例示性封装技术的管芯,然而,本公开内容不仅限于本文所示的封装技术。本公开内容想到了任何封装技术,包括倒装芯片、扇入或扇出晶片级封装、直接芯片附接封装或任何其他适当的封装技术。
该过程然后可以进行到块203,其中可以收集与选定的封装技术相关联的设计规则。在实施例中,这些设计规则可以包括凸块间距、线/空间和/或层数。在块205,可以利用设计规则来为选定的封装技术计算边界条件。在一些实施例中,这些边界条件可以定义封装技术能够实现的输入/输出(I/O)密度。在块207,可以确定每种封装技术的边界条件之内的I/O密度。在实施例中,这可以是要用于所有封装技术的单个I/O密度。在其他实施例中,可以选择I/O密度,以使得要针对每种封装技术使用该I/O密度的倍数。例如,每毫米(mm)12.5个I/O的I/O密度可以被调整为每mm 25个I/O、每mm 37.5个I/O等。可以通过向IC管芯中集成多个硬知识产权(HIP)I/O块来实现这些更大的密度。下文进一步论述HIP I/O块。因为边界条件和产生的I/O密度基于与选定封装技术相关联的设计规则,所以IC管芯可以适于每种封装技术或构造,而无需对设计规则或封装技术的可制造性做出任何改变。
一旦已经确定了I/O密度,该过程就可以进行到块209,其中可以定义HIP I/O块以与所确定的I/O密度相匹配。如本文中使用的,HIP I/O块可以指在IC管芯中的晶体管层中实现的模拟电路、I/O电路或逻辑电路。在该行业中HIP I/O块也可以指硬IP内核。HIP I/O块可以包括已经得到验证并可以用于在管芯上设计逻辑放置的逻辑电路。HIP I/O块还可以存储于HIP I/O块的目录或库中。在块211,可以设计HIP分布层,直到选定的封装技术所共有的最后层。HIP分布层可以被配置成通过管芯往返于HIP I/O块传输信号。在块213,附加分布层可以被设计为,在其设置于选定的封装技术所共有的最后层上时,调整要以封装技术中的选定的封装技术集成的管芯。结果,可以在选定的封装技术之间使用该管芯,直到选定的封装技术所共有的最后层,而仅需要添加针对选定的封装技术的附加分布层。
在一些实施例中,被定义为与所确定的I/O密度相匹配的HIP I/O块可以通过若干不同的IC管芯构造而被集成,而其他HIP I/O块具有类似定义的I/O密度。通过这种方式,被定义为与所确定的I/O密度相匹配的HIP I/O块可以与具有类似定义的I/O密度的其他HIPI/O块互换。例如,被定义为与例如每mm 25个I/O的I/O密度相匹配的HIP I/O块可以与一个IC管芯中的一组HIP I/O块、以及另一个IC管芯中的不同组的HIP I/O块集成,其中这一组和不同组的I/O块也被定义为与每mm 25个I/O的I/O密度相匹配。这样一来,一个IC管芯和另一个IC管芯都可能能够满足多种选定的封装技术的设计规则。
图3是根据本公开内容的各种实施例的在适于多种封装构造的管芯中实施的HIP块312的例示性视图。如图所示,HIP块312可以包括一个或多个HIP I/O块和HIP分布层,例如参考图2所述的那些。如图所示,HIP块312被配置成提供每mm 25个I/O的I/O密度。该I/O密度仅仅是可以如参考图2所述的那样所确定的示例性I/O密度。可以利用任何I/O密度而不脱离本公开内容的范围。此外,可以如参考图2所述的那样来定义并设计HIP I/O块和HIP分布层。
管芯302-310中的每一个示出了HIP块312,其适于与不同的封装构造集成。块302示出了适于与倒装芯片球栅阵列(FCBGA)构造集成的HIP块312。这是通过集成凸块314-318来完成的,其中凸块314提供了信号从HIP块312的离开,而凸块318和316分别提供了电源和地。管芯304示出了在球栅阵列构造中彼此耦合的两个相同的HIP块312和320。因为每个HIP块具有每mm 25个I/O的I/O密度,所以两个HIP块312和320的集成为管芯304提供了每mm50个I/O的有效I/O密度。
管芯306展示了适于与具有线到线或键合线封装构造的倒装芯片尺度封装(FCCSP)集成的HIP块312,其中凸块318和316仍然向HIP块提供电源和地,但是迹线322提供了信号离开,而不是管芯302、304、308和310中所描绘的凸块314。管芯308描绘了适于与利用凸块314替代管芯306中所描绘的迹线的FCCSP构造集成的HIP块312。为了完成这个目的,再分布层(RDL)324已经与HIP块312集成。最后,管芯310描绘了通过增加RDL 326而适于直接芯片附接构造的HIP块312。
这些封装构造是仅仅用于例示的示例性封装构造。本公开内容想到了任何选择和/或数量的封装构造。
图4是根据本公开内容的实施例的用于对能够适于若干不同封装构造的管芯进行组装的管芯制造过程400的例示性流程图。图5提供了根据例示性实施例的示出封装衬底制造过程400中的各阶段的选定操作的截面视图。
过程400可以开始于操作401,其中,可以提供半导体衬底(例如,图5的半导体衬底502)。半导体衬底可以包括诸如硅、二氧化硅、氧化铝、蓝宝石、锗、砷化镓、硅锗合金和/或磷化铟等材料。
在操作403,可以在半导体衬底上形成晶体管层(例如,图5的晶体管层504)。在实施例中,该晶体管层可以形成一个或多个HIP I/O块。例如,可以通过任何常规方式,例如通过光刻工艺来形成晶体管层。
在操作405,可以在晶体管层上形成分布层(例如,图5的分布层506)。分布层可以被配置成往返于晶体管层传输信号。在实施例中,可以通过沉积一层或多层电绝缘材料(例如,图5的绝缘材料510),例如,电介质材料或模制化合物来形成分布层。可以在电绝缘材料中形成一个或多个电布线特征体(例如,图5的电布线特征体508)以往返于晶体管层传输电信号。这些电布线特征体可以包括铜或其合金或任何其他适当的导电材料。
在操作407,可以在电绝缘材料的表面中形成多个金属特征体(例如,图5的金属特征体516)。这些电布线特征体可以形成多种不同封装构造所共有的层(例如,图5的层514),以使得附加层可以设置在该公共层的顶部,以使管芯适于个体封装技术。该最后公共层可以具有诸如在图2中所确定的等I/O密度。在晶体管层形成一个或多个HIP I/O块的实施例中,分布层可以是HIP分布层,例如参考图2所讨论的那些。
图6是通过参考图4和5中所描述的过程制造的适于示例性封装构造的管芯的例示性截面视图。如图所示,可以制造通过该制造过程产生的管芯,直到多种封装技术所共有的层,如块612所示。该公共层可以具有一个或多个附加层,例如形成于其上的再分布层(RDL)610,以使管芯适于不同封装技术中的选定的一种。尽管这里被描绘为RDL,但这仅仅意在进行例示,被配置成使管芯符合选定封装技术的任何层都可以用于使块612适于选定的封装技术。这些层可以包括诸如凸块、支柱或焊球等互连结构。此外,对于线到线封装构造,这些层可以包括多条迹线,例如参考图3的管芯306所述的那些。
图7是根据本公开内容的实施例的利用IC管芯的组装过程700的例示性流程图。这样的IC管芯可以通过上文参考图2所描述的例示性方法来设计,并通过上文参考图4所述并在图5中所描绘的例示性方法来产生。
组装过程700开始于操作701,接收封装衬底(例如,图1的封装衬底104),该封装衬底在预定的衬底连接点处具有暴露的表面抛光。这样,在例示性实施例中,在封装衬底的表面上没有阻焊剂,并且在将芯片耦合到封装衬底之前,在表面抛光上不放置焊料。
在操作702,可以在管芯连接点上设置有焊料凸块的情况下接收IC管芯。尽管IC管芯一般可以是任何常规类型,在特定实施例中,IC管芯可以是具有大I/O数量的处理器,例如微处理器。在操作710,可以将IC管芯与表面抛光的衬底对准,以使带焊料的IC管芯连接点与表面抛光的衬底连接点对准。然后在操作720对管芯侧面焊料进行合金化,以将管芯固定到衬底连接点,这样完成了封装730。
可以使用任何适当的硬件和/或软件将本公开内容的实施例实施到系统中,以根据需要进行配置。图8示意性地示出了根据一些实施例的包括本文中所述的管芯的计算装置。计算装置800可以包容纳诸如母板802的板。母板802可以包括若干部件,包括但不限于处理器804和至少一个通信芯片806。处理器804可以物理和电耦合至母板802。在一些实施方式中,至少一个通信芯片806也可以物理和电耦合至母板802。在其他实施方式中,通信芯片806可以是处理器804的部分。
根据其应用,计算装置800可以包括其他部件,这些其他部件可以或可以不物理和电耦合至母板802。这些其他部件可以包括但不限于易失性存储器(例如,动态随机存取存储器(DRAM)808)、非易失性存储器(例如,只读存储器(ROM)810)、闪速存储器、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频解码器、视频编解码器、功率放大器、全球定位系统(GPS)装置、罗盘、盖格计数器、加速度计、陀螺仪、扬声器、摄像机和大容量存储装置(例如,硬盘驱动器、光盘(CD)、数字通用盘(DVD)等等)。
通信芯片806可以实现用于往返于计算装置800传输数据的无线通信。术语“无线”及其派生词可以用于描述可以通过使用经调制的电磁辐射经由非固体介质来传送数据的电路、装置、系统、方法、技术、通信信道等。该术语并非暗示相关联的装置不包含任何线路,尽管在一些实施例中它们可能不包含。通信芯片806可以实施若干无线标准或协议中的任一种,包括但不限于电气和电子工程师协会(IEEE)标准(包括Wi-Fi(IEEE 802.11族)、IEEE802.16标准(例如,IEEE 802.16-2005修改版))、长期演进(LTE)项目连同任何修改、更新和/或修订(例如,高级LTE项目、超级移动宽带(UMB)项目(也称为“3GPP2”等)。兼容IEEE802.16的BWA网络一般被称为WiMAX网络(代表微波接入全球互操作性的缩写),这是通过了IEEE 802.16标准的一致性和互操作性测试的产品的证明标志。通信芯片806可以根据全球移动通信系统(GSM)、通用分组无线电业务(GPRS)、通用移动电信系统(UMTS)、高速分组接入(HSPA)、演进的HSPA(E-HSPA)或LTE网络而工作。通信芯片806可以根据GSM演进的增强数据(EDGE)、GSM EDGE无线电接入网络(GERAN)、通用陆地无线电接入网络(UTRAN)或演进的UTRAN(E-UTRAN)而工作。通信芯片806可以根据码分多址(CDMA)、时分多址(TDMA)、数字增强无绳电信(DECT)、演进数据优化(EV-DO)、其衍生版本、以及被指定为3G、4G、5G和更高代的任何其他无线协议而工作。在其他实施例中,通信芯片806可以根据其他无线协议而工作。
计算装置800可以包括多个通信芯片806。例如,第一通信芯片806可以专用于较短距离的无线通信,例如Wi-Fi和蓝牙,而第二通信芯片806可以专用于较长距离的无线通信,例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
计算装置800的处理器804可以封装在包括如本文中所述的封装衬底的IC组件(例如,图1的IC组件100)中。例如,图1的电路板122可以是母板802,并且处理器804可以是安装在如本文中描述的封装衬底104上的管芯102。可以使用如本文中描述的封装级互连将封装衬底104和母板802耦合在一起。术语“处理器”可以指处理来自寄存器和/或存储器的电子数据以将该电子数据转换成可以存储在寄存器和/或存储器中的其他电子数据的任何器件或器件的部分。
通信芯片806还可以包括可以封装在包括如本文中所述的封装衬底104的IC组件(例如,图1的IC组件100)中的管芯(例如,图1的管芯102)。在其他实施方式中,计算装置800中容纳的另一个部件(例如,存储器件或其他集成电路器件)可以包括可以封装在包括如本文所述的封装衬底104的IC组件(例如,图1的IC组件100)中的管芯(例如,图1的管芯102)。
此外,计算装置800可以包括诸如DRAM 808或ROM 810的一个或多个计算机可读介质。这些计算机可读介质可以具有存储于其上的指令,所述指令在由处理器804执行时,可以使计算装置800执行本文所述的任何过程,例如上文参考图2所述的过程。
在各种实施方式中,计算装置800可以是膝上计算机、上网本、笔记本、超级本、智能电话、平板计算机、个人数字助理(PDA)、超级移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字摄像机、便携式音乐播放机或数字视频记录仪。在其他实施方式中,计算装置800可以是处理数据的任何其他电子装置。
示例
根据各实施例,本公开内容描述了若干示例。示例1是集成电路(IC)管芯,该IC管芯包括:半导体衬底;设置于半导体衬底上的电绝缘材料;多个电布线特征体,设置于电绝缘材料中,用于使电信号穿过电绝缘材料进行传输;以及与多个电布线特征体耦合的多个金属特征体,其中,多个金属特征体具有被设计为使管芯能够与多种不同封装构造集成的输入/输出(I/O)密度。
示例2可以包括示例1的主题,还包括:设置于衬底和电绝缘材料之间的晶体管层,该晶体管层形成一个或多个硬知识产权(HIP)输入/输出(I/O)块,其中,多个电布线特征体是HIP布线特征体,以使电信号穿过电绝缘材料从多个金属特征体传输到一个或多个HIPI/O特征体。
示例3可以包括示例2的主题,其中,一个或多个HIP I/O块包括各自的逻辑电路。
示例4可以包括示例2的主题,其中,一个或多个HIP I/O块被设计为与I/O密度相匹配。
示例5可以包括示例1-4中任一个的主题,其中,I/O密度至少部分基于分别与多种不同封装构造中的每个封装构造相关联的一个或多个边界条件。
示例6可以包括示例1-4中任一个的主题,还包括:设置于管芯上的多个互连结构,多个互连结构与多个金属特征体耦合,其中,互连结构要将管芯与多种不同封装构造中的选定的一种电耦合。
示例7可以包括示例6的主题,其中,多个互连结构与一个或多个再分布层(RDL)耦合,再分布层将多个互连结构与多个金属特征体电耦合。
示例8可以包括示例6的主题,其中,多个互连结构包括一个或多个支柱、凸块或焊球。
示例9可以包括示例1-4中任一个的主题,其中,多种不同封装构造包括一个或多个直接芯片附接(DCA)电路板构造。
示例10可以包括示例1-4中任一个的主题,其中,多种封装构造中的每种个体封装构造具有个体封装构造的相关联的I/O密度,并且其中,个体封装的相关联的I/O密度发生变化。
示例11是组装集成电路(IC)管芯的方法,包括:提供半导体衬底;在半导体衬底上沉积电绝缘材料;在电绝缘材料中形成多个电布线特征体以使电信号穿过该电绝缘材料进行传输;以及形成与多个电布线特征体耦合的多个金属,其中,多个金属特征体具有被设计为使管芯能够与多种不同封装构造集成的输入/输出(I/O)密度。
示例12可以包括示例11的主题,还包括:在沉积电绝缘材料之前,通过在所述半导体衬底上形成晶体管层来形成一个或多个硬知识产权(HIP)I/O块,其中,多个电布线特征体使电信号穿过电绝缘材料从多个金属特征体传输到一个或多个HIP I/O块。
示例13可以包括示例12的主题,还包括:设计一个或多个HIP I/O块以与I/O密度相匹配。
示例14可以包括示例12的主题,还包括:计算分别与多种不同封装构造中的每种封装构造相关联的一个或多个边界条件,其中,I/O密度的设计至少部分基于分别与多种不同封装构造中的每种封装构造相关联的一个或多个边界条件。
示例15可以包括示例14的主题,其中,计算分别与每种封装构造相关联的一个或多个边界条件基于与多种不同封装构造中的每种封装构造相关联的一个或多个设计规则。
示例16可以包括示例15的主题,其中,设计规则包括凸块间距、线间隔或层数中的至少一个或多个。
示例17可以包括示例11-16中任一个的主题,还包括:在管芯的表面上沉积多个互连结构,多个互连结构与多个金属特征体耦合,其中,互连结构将管芯与多种不同封装构造中的选定的一种电耦合。
示例18可以包括示例17的主题,其中,沉积多个互连结构还包括:沉积一个或多个再分布层(RDL),一个或多个RDL与多个互连结构电耦合。
示例19可以包括示例11-16中任一个的主题,其中,多种不同封装构造包括一个或多个直接芯片附接(DCA)电路板构造。
示例20是封装组件,包括:封装衬底;集成电路(IC)管芯,该集成电路(IC)管芯包括:半导体衬底;设置于半导体衬底上的晶体管层,其形成一个或多个硬知识产权(HIP)I/O块;设置于晶体管层上的电绝缘材料;设置于电绝缘材料中的多个电布线特征体,以使电信号穿过电绝缘材料往返于HIP I/O块来进行传输;与多个电布线特征体耦合的多个金属特征体,其中,多个金属特征体具有被设计为使得管芯能够与多种不同封装构造集成的输入/输出(I/O)密度,并且其中,HIP I/O块被设计为与I/O密度相匹配;以及设置于管芯上的多个互连结构,该多个互连结构与多个金属特征体耦合,其中,互连结构将IC管芯与封装衬底电耦合。
示例21可以包括示例20的主题,其中,IC管芯是处理器。
示例22可以包括示例20的主题,还包括:天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)装置、罗盘、盖格计数器、加速度计、陀螺仪、扬声器或与电路板耦合的摄像机中的一个或多个,其中,封装组件是膝上计算机、上网本、笔记本、超级本、智能电话、平板计算机、个人数字助理(PDA)、超级移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字摄像机、便携式音乐播放器或数字视频记录仪的部分。
示例23是一种或多种计算机可读存储介质,其上存储有指令,所述指令在由计算装置的处理器执行时,使计算装置:从计算装置的用户接受输入,该输入指示用于集成电路(IC)管芯的多种不同封装构造;至少部分基于与每种封装构造相关联的各自的设计规则来为封装构造中的每个封装构造计算一个或多个边界条件;以及为每种封装确定输入/输出(I/O)密度。
示例24可以包括示例23的主题,其中,设计规则包括凸块间距、线间隔或行数中的一个或多个。
示例25可以包括示例23的主题,其中,指令在由计算装置的处理器执行时,使计算装置定义与I/O密度相匹配的一个或多个硬知识产权(HIP)块。
示例26是计算装置,包括:用于从计算装置的用户接受输入的模块,该输入指示用于集成电路(IC)管芯的多种不同封装构造;用于至少部分基于与封装构造中的每种封装构造相关联的各自的设计规则来为每种封装构造计算一个或多个边界条件的模块;以及用于为每种封装确定输入/输出(I/O)密度的模块。
示例27可以包括示例26的主题,其中,设计规则包括凸块间距、线间隔或行数中的一个或多个。
示例28可以包括示例26的主题,还包括:用于定义与I/O密度相匹配的一个或多个硬知识产权(HIP)块的模块。
示例29是计算机实施的方法,包括:由计算装置从计算装置的用户接受输入,该输入指示用于集成电路(IC)管芯的多种不同封装构造;由计算装置至少部分基于与封装构造中的每种封装构造相关联的各自的设计规则来为每种封装构造计算一个或多个边界条件;以及由计算装置为每种封装确定输入/输出(I/O)密度。
示例30可以包括示例29的主题,其中,设计规则包括凸块间距、线间隔或行数中的一个或多个。
示例31可以包括示例29的主题,还包括:定义与I/O密度相匹配的一个或多个硬知识产权(HIP)块。
各实施例可以包括上述实施例的任何适当的组合,包括上文以连词形式(和)所描述的实施例的替代(或)实施例(例如,“和”可以是“和/或”)。此外,一些实施例可以包括一种或多种制品(例如,非暂态计算机可读介质),其上存储有指令,指令在被执行时,导致上述实施例中的任一个的动作。此外,一些实施例可以包括具有用于执行上述实施例的各种操作的任何适当模块的设备或系统。
为了本说明书的目的,计算机可用或计算机可读介质可以是能够包含、存储、传送、传播或传输程序以供指令执行系统、设备或装置使用、或与之结合使用的任何设备。该介质可以是电子、磁、光、电磁、红外或半导体系统(或设备或装置)或传播介质。计算机可读介质的示例包括半导体或固态存储器、磁带、可移除计算机盘、随机存取存储器(RAM)、只读存储器(ROM)、刚性磁盘和光盘。光盘的当前示例包括紧致磁盘-只读存储器(CD-ROM)、紧致磁盘-读/写(CD-R/W)和DVD。
图示实施方式的以上描述,包括摘要里描述的内容,并非要进行穷举或将本公开内容的实施例限制于所公开的精确形式。尽管出于例示的目的在本文中描述了具体实施方式和示例,但相关领域的技术人员将认识到,在本公开内容的范围内,各种等价修改都是可能的。
可以根据以上具体实施方式对本公开内容的实施例做出这些修改。以下权利要求中使用的术语不应被解释为将本公开内容的各个实施例限制到说明书和权利要求中所公开的特定实施方式。相反,范围要完全由以下权利要求来确定,权利要求要根据权利要求解释所建立的基本原则来解释。
Claims (25)
1.一种集成电路(IC)管芯,包括:
半导体衬底;
设置在所述半导体衬底上的电绝缘材料;
多个电布线特征体,其设置在所述电绝缘材料中,所述多个电布线特征体用于使电信号穿过所述电绝缘材料来进行传输;以及
与所述多个电布线特征体耦合的多个金属特征体,其中,所述多个金属特征体具有被设计为使得所述管芯能够与多种不同封装构造集成的输入/输出(I/O)密度。
2.根据权利要求1所述的IC管芯,还包括:设置在所述衬底和所述电绝缘材料之间的晶体管层,所述晶体管层形成一个或多个硬知识产权(HIP)输入/输出(I/O)块,其中,所述多个电布线特征体是HIP布线特征体,用于使电信号穿过所述电绝缘材料从所述多个金属特征体传输到所述一个或多个HIP I/O块。
3.根据权利要求2所述的IC管芯,其中,所述一个或多个HIP I/O块包括各自的逻辑电路。
4.根据权利要求2所述的IC管芯,其中,所述一个或多个HIP I/O块被设计为与所述I/O密度相匹配。
5.根据权利要求1-4中任一项所述的IC管芯,其中,所述I/O密度至少部分地基于分别与所述多种不同封装构造中的每种封装构造相关联的一个或多个边界条件。
6.根据权利要求1-4中任一项所述的IC管芯,还包括:设置在所述管芯上的多个互连结构,所述多个互连结构与所述多个金属特征体耦合,其中,所述互连结构将所述管芯与所述多种不同封装构造中的选定的一种封装构造电耦合。
7.根据权利要求6所述的IC管芯,其中,所述多个互连结构与一个或多个再分布层(RDL)耦合,所述再分布层(RDL)将所述多个互连结构与所述多个金属特征体电耦合。
8.根据权利要求6所述的IC管芯,其中,所述多个互连结构包括支柱、凸块或焊球中的一个或多个。
9.根据权利要求1-4中任一项所述的IC管芯,其中,所述多种不同封装构造包括一种或多种直接芯片附接(DCA)电路板构造。
10.根据权利要求1-4中任一项所述的IC管芯,其中,所述多种封装构造中的每种个体封装构造具有所述个体封装构造的相关联的I/O密度,并且其中,所述个体封装的相关联的I/O密度发生变化。
11.一种组装集成电路(IC)管芯的方法,包括:
提供半导体衬底;
在所述半导体衬底上沉积电绝缘材料;
在所述电绝缘材料中形成多个电布线特征体,用于使电信号穿过所述电绝缘材料来进行传输;以及
形成与所述多个电布线特征体耦合的多个金属,其中,所述多个金属特征体具有被设计为使得所述管芯能够与多种不同封装构造集成的输入/输出(I/O)密度。
12.根据权利要求11所述的方法,还包括:在沉积所述电绝缘材料之前,通过在所述半导体衬底上形成晶体管层来形成一个或多个硬知识产权(HIP)I/O块,其中,所述多个电布线特征体使电信号穿过所述电绝缘材料从所述多个金属特征体传输到所述一个或多个HIPI/O块。
13.根据权利要求12所述的方法,还包括:设计所述一个或多个HIP I/O块以与所述I/O密度相匹配。
14.根据权利要求12所述的方法,还包括:计算分别与所述多种不同封装构造中的每种封装构造相关联的一个或多个边界条件,其中,所述I/O密度的设计至少部分地基于分别与所述多种不同封装构造中的每种封装构造相关联的所述一个或多个边界条件。
15.根据权利要求14所述的方法,其中,计算分别与每种封装构造相关联的所述一个或多个边界条件基于与所述多种不同封装构造中的每种封装构造相关联的一个或多个设计规则。
16.根据权利要求15所述的方法,其中,所述设计规则包括凸块间距、线间隔或层数中的至少一个或多个。
17.根据权利要求11-16中任一项所述的方法,还包括:在所述管芯的表面上沉积多个互连结构,所述多个互连结构与所述多个金属特征体耦合,其中,所述互连结构将所述管芯与所述多种不同封装构造中的选定的一种封装构造电耦合。
18.根据权利要求17所述的方法,其中,沉积所述多个互连结构还包括沉积一个或多个再分布层(RDL),所述一个或多个RDL与所述多个互连结构电耦合。
19.根据权利要求11-16中任一项所述的方法,其中,所述多种不同封装配置包括一种或多种直接芯片附接(DCA)电路板构造。
20.一种封装组件,包括:
封装衬底;以及
集成电路(IC)管芯,其包括:
半导体衬底;
晶体管层,其设置在所述半导体衬底上,所述晶体管层形成一个或多个硬知识产权(HIP)I/O块;
设置在所述晶体管层上的电绝缘材料;
设置在所述电绝缘材料中的多个电布线特征体,用于使电信号穿过所述电绝缘材料往返于所述HIP I/O块来进行传输;
与所述多个电布线特征体耦合的多个金属特征体,其中,所述多个金属特征体具有被设计为使得所述管芯能够与多种不同封装构造集成的输入/输出(I/O)密度,并且其中,所述HIP I/O块被设计为与所述I/O密度相匹配;以及
设置在所述管芯上的多个互连结构,所述多个互连结构与所述多个金属特征体耦合,其中,所述互连结构将所述IC管芯与所述封装衬底电耦合。
21.根据权利要求20所述的封装组件,其中,所述IC管芯是处理器。
22.根据权利要求20所述的封装组件,还包括:天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)装置、罗盘、盖格计数器、加速度计、陀螺仪、扬声器、或与所述电路板耦合的摄像机中的一个或多个,其中,所述封装组件是膝上计算机、上网本、笔记本、超级本、智能电话、平板计算机、个人数字助理(PDA)、超级移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字摄像机、便携式音乐播放器或数字视频记录仪的一部分。
23.一种或多种计算机可读存储介质,具有存储于其上的指令,所述指令在由计算装置的处理器执行时,使所述计算装置:
从所述计算装置的用户接受输入,所述输入指示用于集成电路(IC)管芯的多种不同封装构造;
至少部分地基于与所述封装构造中的每种封装构造相关联的各自的设计规则来为每种封装构造计算一个或多个边界条件;以及
为每种封装确定输入/输出(I/O)密度。
24.根据权利要求23所述的一种或多种计算机可读存储介质,其中,所述设计规则包括凸块间距、线间隔或行数中的一个或多个。
25.根据权利要求23所述的一种或多种计算机可读存储介质,其中,所述指令在由所述计算装置的处理器执行时,使所述计算装置定义与所述I/O密度相匹配的一个或多个硬知识产权(HIP)块。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007015507A1 (ja) * | 2005-08-02 | 2007-02-08 | Osaka University | 電子回路装置とその製造方法 |
US20130313727A1 (en) * | 2012-05-23 | 2013-11-28 | Eng Huat Goh | Multi-stacked bbul package |
US20140070380A1 (en) * | 2012-09-11 | 2014-03-13 | Chia-Pin Chiu | Bridge interconnect with air gap in package assembly |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2560805B2 (ja) | 1988-10-06 | 1996-12-04 | 三菱電機株式会社 | 半導体装置 |
US7030481B2 (en) | 2002-12-09 | 2006-04-18 | Internation Business Machines Corporation | High density chip carrier with integrated passive devices |
US8124429B2 (en) | 2006-12-15 | 2012-02-28 | Richard Norman | Reprogrammable circuit board with alignment-insensitive support for multiple component contact types |
KR101622805B1 (ko) * | 2009-03-06 | 2016-05-20 | 유탁 홍콩 리미티드 | 다양한 ic 패키징 구성들을 가진 리드리스 어레이 플라스틱 패키지 |
CN102738024A (zh) * | 2011-04-01 | 2012-10-17 | 飞思卡尔半导体公司 | 半导体封装及其引线框 |
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US8860218B2 (en) * | 2011-10-10 | 2014-10-14 | Texas Instruments Incorporated | Semiconductor device having improved contact structure |
US8878182B2 (en) * | 2011-10-12 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Probe pad design for 3DIC package yield analysis |
US9209136B2 (en) * | 2013-04-01 | 2015-12-08 | Intel Corporation | Hybrid carbon-metal interconnect structures |
US9275955B2 (en) * | 2013-12-18 | 2016-03-01 | Intel Corporation | Integrated circuit package with embedded bridge |
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